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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -06002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Varun Wadekar6e6ce612018-06-20 13:43:43 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9#include <errno.h>
10#include <stddef.h>
11#include <string.h>
12
13#include <platform_def.h>
14
Varun Wadekarb316e242015-05-19 16:48:04 +053015#include <arch.h>
16#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <bl31/bl31.h>
18#include <common/bl_common.h>
19#include <common/debug.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053020#include <cortex_a53.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010021#include <cortex_a57.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053022#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/console.h>
24#include <lib/mmio.h>
25#include <lib/utils.h>
26#include <lib/utils_def.h>
27#include <plat/common/platform.h>
28
Varun Wadekarb316e242015-05-19 16:48:04 +053029#include <memctrl.h>
Varun Wadekar4967c3d2017-07-21 13:34:16 -070030#include <profiler.h>
Varun Wadekar82b0b182019-09-26 08:26:41 -070031#include <smmu.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080032#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080033#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053034#include <tegra_private.h>
35
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080036/* length of Trusty's input parameters (in bytes) */
37#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
38
Varun Wadekarb316e242015-05-19 16:48:04 +053039/*******************************************************************************
40 * Declarations of linker defined symbols which will help us find the layout
41 * of trusted SRAM
42 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -080043IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -060044
Varun Wadekarb316e242015-05-19 16:48:04 +053045extern uint64_t tegra_bl31_phys_base;
46
Varun Wadekar52a15982015-06-05 12:57:27 +053047static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053048static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarfda095f2019-01-02 10:48:18 -080049 .tzdram_size = TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053050};
Varun Wadekar1c4d5e42019-12-17 21:23:24 -080051#ifdef SPD_trusty
52static aapcs64_params_t bl32_args;
53#endif
Varun Wadekarb316e242015-05-19 16:48:04 +053054
55/*******************************************************************************
56 * This variable holds the non-secure image entry address
57 ******************************************************************************/
58extern uint64_t ns_image_entrypoint;
59
60/*******************************************************************************
61 * Return a pointer to the 'entry_point_info' structure of the next image for
62 * security state specified. BL33 corresponds to the non-secure image type
63 * while BL32 corresponds to the secure image type.
64 ******************************************************************************/
65entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
66{
Varun Wadekarfda095f2019-01-02 10:48:18 -080067 entry_point_info_t *ep = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +053068
Varun Wadekar197a75f2016-06-06 10:46:28 -070069 /* return BL32 entry point info if it is valid */
Varun Wadekarfda095f2019-01-02 10:48:18 -080070 if (type == NON_SECURE) {
71 ep = &bl33_image_ep_info;
72 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
73 ep = &bl32_image_ep_info;
74 }
Varun Wadekar52a15982015-06-05 12:57:27 +053075
Varun Wadekarfda095f2019-01-02 10:48:18 -080076 return ep;
Varun Wadekarb316e242015-05-19 16:48:04 +053077}
78
79/*******************************************************************************
80 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
81 * passes this platform specific information.
82 ******************************************************************************/
83plat_params_from_bl2_t *bl31_get_plat_params(void)
84{
85 return &plat_bl31_params_from_bl2;
86}
87
88/*******************************************************************************
89 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
90 * info.
91 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010092void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
93 u_register_t arg2, u_register_t arg3)
Varun Wadekarb316e242015-05-19 16:48:04 +053094{
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010095 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
96 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
Varun Wadekar4967c3d2017-07-21 13:34:16 -070097 int32_t ret;
Varun Wadekarbaf903e2015-09-22 15:00:06 +053098
Varun Wadekarb316e242015-05-19 16:48:04 +053099 /*
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700100 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
101 * there's no argument to relay from a previous bootloader. Platforms
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700102 * might use custom ways to get arguments.
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700103 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800104 if (arg_from_bl2 == NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100105 arg_from_bl2 = plat_get_bl31_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800106 }
107 if (plat_params == NULL) {
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700108 plat_params = plat_get_bl31_plat_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800109 }
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700110
111 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530112 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530113 * They are stored in Secure RAM, in BL2's address space.
114 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800115 assert(arg_from_bl2 != NULL);
116 assert(arg_from_bl2->bl33_ep_info != NULL);
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100117 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530118
Varun Wadekarfda095f2019-01-02 10:48:18 -0800119 if (arg_from_bl2->bl32_ep_info != NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100120 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800121#ifdef SPD_trusty
122 /* save BL32 boot parameters */
123 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args));
124#endif
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800125 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530126
127 /*
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800128 * Parse platform specific parameters
Varun Wadekarb316e242015-05-19 16:48:04 +0530129 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800130 assert(plat_params != NULL);
Varun Wadekar6bb62462015-10-06 12:49:31 +0530131 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
132 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530133 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800134 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800135 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
136 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
Varun Wadekard2014c62015-10-29 10:37:28 +0530137
138 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700139 * It is very important that we run either from TZDRAM or TZSRAM base.
140 * Add an explicit check here.
141 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800142 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
143 (TEGRA_TZRAM_BASE != BL31_BASE)) {
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700144 panic();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800145 }
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700146
147 /*
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700148 * Enable console for the platform
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800149 */
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700150 plat_enable_console(plat_params->uart_id);
Varun Wadekard2014c62015-10-29 10:37:28 +0530151
Varun Wadekar5118b532016-06-04 22:08:50 -0700152 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700153 * The previous bootloader passes the base address of the shared memory
154 * location to store the boot profiler logs. Sanity check the
Andreas Färberd829cd42019-06-17 00:06:43 +0200155 * address and initialise the profiler library, if it looks ok.
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700156 */
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700157 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
158 PROFILER_SIZE_BYTES);
159 if (ret == (int32_t)0) {
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700160
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700161 /* store the membase for the profiler lib */
162 plat_bl31_params_from_bl2.boot_profiler_shmem_base =
163 plat_params->boot_profiler_shmem_base;
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700164
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700165 /* initialise the profiler library */
166 boot_profiler_init(plat_params->boot_profiler_shmem_base,
167 TEGRA_TMRUS_BASE);
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700168 }
169
170 /*
171 * Add timestamp for platform early setup entry.
172 */
173 boot_profiler_add_record("[TF] early setup entry");
174
175 /*
Steven Kao27e64312016-10-21 14:16:59 +0800176 * Initialize delay timer
177 */
178 tegra_delay_timer_init();
179
Varun Wadekardbe67c72017-09-20 15:09:38 -0700180 /* Early platform setup for Tegra SoCs */
181 plat_early_platform_setup();
182
Steven Kao27e64312016-10-21 14:16:59 +0800183 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700184 * Add timestamp for platform early setup exit.
185 */
186 boot_profiler_add_record("[TF] early setup exit");
187
Sandrine Bailleuxfff61b62018-06-21 11:41:43 +0200188 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
189 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
190 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530191}
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800192
193#ifdef SPD_trusty
194void plat_trusty_set_boot_args(aapcs64_params_t *args)
195{
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800196 /*
197 * arg0 = TZDRAM aperture available for BL32
198 * arg1 = BL32 boot params
199 * arg2 = EKS Blob Length
200 * arg3 = Boot Profiler Carveout Base
201 */
202 args->arg0 = bl32_args.arg0;
203 args->arg1 = bl32_args.arg2;
Varun Wadekarc2099802018-12-28 13:50:20 -0800204
205 /* update EKS size */
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800206 args->arg2 = bl32_args.arg4;
Varun Wadekar7a1ba292019-01-02 16:30:01 -0800207
208 /* Profiler Carveout Base */
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800209 args->arg3 = bl32_args.arg5;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800210}
211#endif
Varun Wadekarb316e242015-05-19 16:48:04 +0530212
213/*******************************************************************************
214 * Initialize the gic, configure the SCR.
215 ******************************************************************************/
216void bl31_platform_setup(void)
217{
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700218 /*
219 * Add timestamp for platform setup entry.
220 */
221 boot_profiler_add_record("[TF] plat setup entry");
222
Varun Wadekarb7b45752015-12-28 14:55:41 -0800223 /* Initialize the gic cpu and distributor interfaces */
224 plat_gic_setup();
225
Varun Wadekarb316e242015-05-19 16:48:04 +0530226 /*
227 * Setup secondary CPU POR infrastructure.
228 */
229 plat_secondary_setup();
230
231 /*
232 * Initial Memory Controller configuration.
233 */
234 tegra_memctrl_setup();
235
236 /*
Dilan Lee1f66f3d2017-10-27 09:51:09 +0800237 * Late setup handler to allow platforms to performs additional
238 * functionality.
239 * This handler gets called with MMU enabled.
240 */
241 plat_late_platform_setup();
242
243 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700244 * Add timestamp for platform setup exit.
245 */
246 boot_profiler_add_record("[TF] plat setup exit");
247
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530248 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530249}
250
251/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800252 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
253 ******************************************************************************/
254void bl31_plat_runtime_setup(void)
255{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700256 /*
Harvey Hsieh359be952017-08-21 15:01:53 +0800257 * During cold boot, it is observed that the arbitration
258 * bit is set in the Memory controller leading to false
259 * error interrupts in the non-secure world. To avoid
260 * this, clean the interrupt status register before
261 * booting into the non-secure world
262 */
263 tegra_memctrl_clear_pending_interrupts();
264
265 /*
Varun Wadekarc92050b2017-03-29 14:57:29 -0700266 * During boot, USB3 and flash media (SDMMC/SATA) devices need
267 * access to IRAM. Because these clients connect to the MC and
268 * do not have a direct path to the IRAM, the MC implements AHB
269 * redirection during boot to allow path to IRAM. In this mode
270 * accesses to a programmed memory address aperture are directed
271 * to the AHB bus, allowing access to the IRAM. This mode must be
272 * disabled before we jump to the non-secure world.
273 */
274 tegra_memctrl_disable_ahb_redirection();
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700275
Varun Wadekar82b0b182019-09-26 08:26:41 -0700276#if defined(TEGRA_SMMU0_BASE)
277 /*
278 * Verify the integrity of the previously configured SMMU(s) settings
279 */
280 tegra_smmu_verify();
281#endif
282
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700283 /*
284 * Add final timestamp before exiting BL31.
285 */
286 boot_profiler_add_record("[TF] bl31 exit");
287 boot_profiler_deinit();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800288}
289
290/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530291 * Perform the very early platform specific architectural setup here. At the
292 * moment this only intializes the mmu in a quick and dirty way.
293 ******************************************************************************/
294void bl31_plat_arch_setup(void)
295{
Varun Wadekarfda095f2019-01-02 10:48:18 -0800296 uint64_t rw_start = BL31_RW_START;
Kalyani Chidambaram425155a2018-12-19 11:06:14 -0800297 uint64_t rw_size = BL_END - BL31_RW_START;
298 uint64_t rodata_start = BL_RO_DATA_BASE;
299 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
300 uint64_t code_base = BL_CODE_BASE;
301 uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
Varun Wadekarb316e242015-05-19 16:48:04 +0530302 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarfda095f2019-01-02 10:48:18 -0800303 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530304
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700305 /*
306 * Add timestamp for arch setup entry.
307 */
308 boot_profiler_add_record("[TF] arch setup entry");
309
Varun Wadekar922550a2018-01-23 14:38:51 -0800310 /* add MMIO space */
311 plat_mmio_map = plat_get_mmio_map();
312 if (plat_mmio_map != NULL) {
313 mmap_add(plat_mmio_map);
314 } else {
315 WARN("MMIO map not available\n");
316 }
317
Varun Wadekarb316e242015-05-19 16:48:04 +0530318 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800319 mmap_add_region(rw_start, rw_start,
320 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530321 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800322 mmap_add_region(rodata_start, rodata_start,
323 rodata_size,
324 MT_RO_DATA | MT_SECURE);
325 mmap_add_region(code_base, code_base,
326 code_size,
327 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530328
Varun Wadekar922550a2018-01-23 14:38:51 -0800329 /* map TZDRAM used by BL31 as coherent memory */
330 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
331 mmap_add_region(params_from_bl2->tzdram_base,
332 params_from_bl2->tzdram_base,
333 BL31_SIZE,
334 MT_DEVICE | MT_RW | MT_SECURE);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800335 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530336
337 /* set up translation tables */
338 init_xlat_tables();
339
340 /* enable the MMU */
341 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530342
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700343 /*
344 * Add timestamp for arch setup exit.
345 */
346 boot_profiler_add_record("[TF] arch setup exit");
347
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530348 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530349}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530350
351/*******************************************************************************
352 * Check if the given NS DRAM range is valid
353 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -0800354int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
Varun Wadekar7a269e22015-06-10 14:04:32 +0530355{
Varun Wadekarc74343c2017-07-20 09:43:28 -0700356 uint64_t end = base + size_in_bytes - U(1);
Varun Wadekar7a269e22015-06-10 14:04:32 +0530357
358 /*
Varun Wadekar11f5db52020-06-02 21:16:00 -0700359 * Sanity check the input values
360 */
361 if ((base == 0U) || (size_in_bytes == 0U)) {
362 ERROR("NS address 0x%llx (%lld bytes) is invalid\n",
363 base, size_in_bytes);
364 return -EINVAL;
365 }
366
367 /*
Varun Wadekar7a269e22015-06-10 14:04:32 +0530368 * Check if the NS DRAM address is valid
369 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700370 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
371 (end > TEGRA_DRAM_END)) {
372
Andreas Färber90bbade2019-06-16 23:32:20 +0200373 ERROR("NS address 0x%llx is out-of-bounds!\n", base);
Varun Wadekar11f5db52020-06-02 21:16:00 -0700374 return -EFAULT;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530375 }
376
377 /*
378 * TZDRAM aperture contains the BL31 and BL32 images, so we need
379 * to check if the NS DRAM range overlaps the TZDRAM aperture.
380 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700381 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
Andreas Färber90bbade2019-06-16 23:32:20 +0200382 ERROR("NS address 0x%llx overlaps TZDRAM!\n", base);
Varun Wadekar11f5db52020-06-02 21:16:00 -0700383 return -ENOTSUP;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530384 }
385
386 /* valid NS address */
Varun Wadekar11f5db52020-06-02 21:16:00 -0700387 return 0;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530388}