Tegra: init normal/crash console for platforms
The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.
This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.
Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index f762d6a..3a9514b 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -55,6 +55,7 @@
extern unsigned long __BL31_END__;
extern uint64_t tegra_bl31_phys_base;
+extern uint64_t tegra_console_base;
/*
* The next 3 constants identify the extents of the code, RO data region and the
@@ -114,17 +115,6 @@
#if DEBUG
int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
#endif
- /*
- * Configure the UART port to be used as the console
- */
- console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ,
- TEGRA_CONSOLE_BAUDRATE);
-
- /* Initialise crash console */
- plat_crash_console_init();
-
- INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
- "Denver" : "ARM", read_mpidr());
/*
* Copy BL3-3, BL3-2 entry point information.
@@ -142,6 +132,27 @@
assert(plat_params);
plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
+ plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
+
+ /*
+ * Get the base address of the UART controller to be used for the
+ * console
+ */
+ assert(plat_params->uart_id);
+ tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
+
+ /*
+ * Configure the UART port to be used as the console
+ */
+ assert(tegra_console_base);
+ console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
+ TEGRA_CONSOLE_BAUDRATE);
+
+ /* Initialise crash console */
+ plat_crash_console_init();
+
+ INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
+ "Denver" : "ARM", read_mpidr());
}
/*******************************************************************************