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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <errno.h>
9#include <stddef.h>
10#include <string.h>
11
12#include <platform_def.h>
13
Varun Wadekarb316e242015-05-19 16:48:04 +053014#include <arch.h>
15#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <bl31/bl31.h>
17#include <common/bl_common.h>
18#include <common/debug.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053019#include <cortex_a53.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010020#include <cortex_a57.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053021#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/console.h>
23#include <lib/mmio.h>
24#include <lib/utils.h>
25#include <lib/utils_def.h>
26#include <plat/common/platform.h>
27
Varun Wadekarb316e242015-05-19 16:48:04 +053028#include <memctrl.h>
Varun Wadekar4967c3d2017-07-21 13:34:16 -070029#include <profiler.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080030#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080031#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053032#include <tegra_private.h>
33
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080034/* length of Trusty's input parameters (in bytes) */
35#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
36
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010037extern void memcpy16(void *dest, const void *src, unsigned int length);
Varun Wadekarb41a4142016-05-23 15:56:14 -070038
Varun Wadekarb316e242015-05-19 16:48:04 +053039/*******************************************************************************
40 * Declarations of linker defined symbols which will help us find the layout
41 * of trusted SRAM
42 ******************************************************************************/
Joel Hutton5cc3bc82018-03-21 11:40:57 +000043
Varun Wadekarfda095f2019-01-02 10:48:18 -080044IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
45IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
46IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
47IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
48IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
49IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
Varun Wadekarb316e242015-05-19 16:48:04 +053050
Varun Wadekarb316e242015-05-19 16:48:04 +053051extern uint64_t tegra_bl31_phys_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053052extern uint64_t tegra_console_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053053
Varun Wadekar52a15982015-06-05 12:57:27 +053054static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053055static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarfda095f2019-01-02 10:48:18 -080056 .tzdram_size = TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053057};
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080058static unsigned long bl32_mem_size;
59static unsigned long bl32_boot_params;
Varun Wadekarb316e242015-05-19 16:48:04 +053060
61/*******************************************************************************
62 * This variable holds the non-secure image entry address
63 ******************************************************************************/
64extern uint64_t ns_image_entrypoint;
65
66/*******************************************************************************
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070067 * The following platform setup functions are weakly defined. They
68 * provide typical implementations that will be overridden by a SoC.
69 ******************************************************************************/
70#pragma weak plat_early_platform_setup
Varun Wadekard22d4ad2016-05-23 11:41:07 -070071#pragma weak plat_get_bl31_params
72#pragma weak plat_get_bl31_plat_params
Dilan Lee1f66f3d2017-10-27 09:51:09 +080073#pragma weak plat_late_platform_setup
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070074
75void plat_early_platform_setup(void)
76{
77 ; /* do nothing */
78}
79
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010080struct tegra_bl31_params *plat_get_bl31_params(void)
Varun Wadekard22d4ad2016-05-23 11:41:07 -070081{
82 return NULL;
83}
84
85plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
86{
87 return NULL;
88}
89
Dilan Lee1f66f3d2017-10-27 09:51:09 +080090void plat_late_platform_setup(void)
91{
92 ; /* do nothing */
93}
94
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070095/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +053096 * Return a pointer to the 'entry_point_info' structure of the next image for
97 * security state specified. BL33 corresponds to the non-secure image type
98 * while BL32 corresponds to the secure image type.
99 ******************************************************************************/
100entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
101{
Varun Wadekarfda095f2019-01-02 10:48:18 -0800102 entry_point_info_t *ep = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530103
Varun Wadekar197a75f2016-06-06 10:46:28 -0700104 /* return BL32 entry point info if it is valid */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800105 if (type == NON_SECURE) {
106 ep = &bl33_image_ep_info;
107 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
108 ep = &bl32_image_ep_info;
109 }
Varun Wadekar52a15982015-06-05 12:57:27 +0530110
Varun Wadekarfda095f2019-01-02 10:48:18 -0800111 return ep;
Varun Wadekarb316e242015-05-19 16:48:04 +0530112}
113
114/*******************************************************************************
115 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
116 * passes this platform specific information.
117 ******************************************************************************/
118plat_params_from_bl2_t *bl31_get_plat_params(void)
119{
120 return &plat_bl31_params_from_bl2;
121}
122
123/*******************************************************************************
124 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
125 * info.
126 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100127void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
128 u_register_t arg2, u_register_t arg3)
Varun Wadekarb316e242015-05-19 16:48:04 +0530129{
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100130 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
131 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
Varun Wadekarb41a4142016-05-23 15:56:14 -0700132 image_info_t bl32_img_info = { {0} };
133 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800134 uint32_t console_clock;
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700135 int32_t ret;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530136
Varun Wadekarb316e242015-05-19 16:48:04 +0530137 /*
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700138 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
139 * there's no argument to relay from a previous bootloader. Platforms
140 * might use custom ways to get arguments, so provide handlers which
141 * they can override.
142 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800143 if (arg_from_bl2 == NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100144 arg_from_bl2 = plat_get_bl31_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800145 }
146 if (plat_params == NULL) {
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700147 plat_params = plat_get_bl31_plat_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800148 }
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700149
150 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530151 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530152 * They are stored in Secure RAM, in BL2's address space.
153 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800154 assert(arg_from_bl2 != NULL);
155 assert(arg_from_bl2->bl33_ep_info != NULL);
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100156 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530157
Varun Wadekarfda095f2019-01-02 10:48:18 -0800158 if (arg_from_bl2->bl32_ep_info != NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100159 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
160 bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
161 bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800162 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530163
164 /*
Varun Wadekar6bb62462015-10-06 12:49:31 +0530165 * Parse platform specific parameters - TZDRAM aperture base and size
Varun Wadekarb316e242015-05-19 16:48:04 +0530166 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800167 assert(plat_params != NULL);
Varun Wadekar6bb62462015-10-06 12:49:31 +0530168 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
169 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530170 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800171 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
Varun Wadekard2014c62015-10-29 10:37:28 +0530172
173 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700174 * It is very important that we run either from TZDRAM or TZSRAM base.
175 * Add an explicit check here.
176 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800177 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
178 (TEGRA_TZRAM_BASE != BL31_BASE)) {
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700179 panic();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800180 }
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700181
182 /*
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800183 * Reference clock used by the FPGAs is a lot slower.
184 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800185 if (tegra_platform_is_fpga()) {
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800186 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
187 } else {
188 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
189 }
190
191 /*
Varun Wadekard2014c62015-10-29 10:37:28 +0530192 * Get the base address of the UART controller to be used for the
193 * console
194 */
Varun Wadekard2014c62015-10-29 10:37:28 +0530195 tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
196
Varun Wadekarfda095f2019-01-02 10:48:18 -0800197 if (tegra_console_base != 0U) {
Damon Duan777baa52016-11-07 19:37:50 +0800198 /*
199 * Configure the UART port to be used as the console
200 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800201 (void)console_init(tegra_console_base, console_clock,
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800202 TEGRA_CONSOLE_BAUDRATE);
Damon Duan777baa52016-11-07 19:37:50 +0800203 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530204
Varun Wadekar5118b532016-06-04 22:08:50 -0700205 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700206 * The previous bootloader passes the base address of the shared memory
207 * location to store the boot profiler logs. Sanity check the
208 * address and initilise the profiler library, if it looks ok.
209 */
210 if (plat_params->boot_profiler_shmem_base != 0ULL) {
211
212 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
213 PROFILER_SIZE_BYTES);
214 if (ret == (int32_t)0) {
215
216 /* store the membase for the profiler lib */
217 plat_bl31_params_from_bl2.boot_profiler_shmem_base =
218 plat_params->boot_profiler_shmem_base;
219
220 /* initialise the profiler library */
221 boot_profiler_init(plat_params->boot_profiler_shmem_base,
222 TEGRA_TMRUS_BASE);
223 }
224 }
225
226 /*
227 * Add timestamp for platform early setup entry.
228 */
229 boot_profiler_add_record("[TF] early setup entry");
230
231 /*
Steven Kao27e64312016-10-21 14:16:59 +0800232 * Initialize delay timer
233 */
234 tegra_delay_timer_init();
235
Varun Wadekardbe67c72017-09-20 15:09:38 -0700236 /* Early platform setup for Tegra SoCs */
237 plat_early_platform_setup();
238
Steven Kao27e64312016-10-21 14:16:59 +0800239 /*
Varun Wadekar5118b532016-06-04 22:08:50 -0700240 * Do initial security configuration to allow DRAM/device access.
241 */
242 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
Varun Wadekarfda095f2019-01-02 10:48:18 -0800243 (uint32_t)plat_bl31_params_from_bl2.tzdram_size);
Varun Wadekar5118b532016-06-04 22:08:50 -0700244
Varun Wadekarb41a4142016-05-23 15:56:14 -0700245 /*
246 * The previous bootloader might not have placed the BL32 image
247 * inside the TZDRAM. We check the BL32 image info to find out
248 * the base/PC values and relocate the image if necessary.
249 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800250 if (arg_from_bl2->bl32_image_info != NULL) {
Varun Wadekarb41a4142016-05-23 15:56:14 -0700251
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100252 bl32_img_info = *arg_from_bl2->bl32_image_info;
Varun Wadekarb41a4142016-05-23 15:56:14 -0700253
254 /* Relocate BL32 if it resides outside of the TZDRAM */
255 tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
256 tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
257 plat_bl31_params_from_bl2.tzdram_size;
258 bl32_start = bl32_img_info.image_base;
259 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
260
261 assert(tzdram_end > tzdram_start);
262 assert(bl32_end > bl32_start);
263 assert(bl32_image_ep_info.pc > tzdram_start);
264 assert(bl32_image_ep_info.pc < tzdram_end);
265
266 /* relocate BL32 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800267 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
Varun Wadekarb41a4142016-05-23 15:56:14 -0700268
269 INFO("Relocate BL32 to TZDRAM\n");
270
Varun Wadekarfda095f2019-01-02 10:48:18 -0800271 (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
Varun Wadekarb41a4142016-05-23 15:56:14 -0700272 (void *)(uintptr_t)bl32_start,
273 bl32_img_info.image_size);
274
275 /* clean up non-secure intermediate buffer */
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100276 zeromem((void *)(uintptr_t)bl32_start,
Varun Wadekarb41a4142016-05-23 15:56:14 -0700277 bl32_img_info.image_size);
278 }
279 }
280
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700281 /*
282 * Add timestamp for platform early setup exit.
283 */
284 boot_profiler_add_record("[TF] early setup exit");
285
Sandrine Bailleuxfff61b62018-06-21 11:41:43 +0200286 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
287 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
288 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530289}
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800290
291#ifdef SPD_trusty
292void plat_trusty_set_boot_args(aapcs64_params_t *args)
293{
294 args->arg0 = bl32_mem_size;
295 args->arg1 = bl32_boot_params;
296 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
Varun Wadekarc2099802018-12-28 13:50:20 -0800297
298 /* update EKS size */
299 if (args->arg4 != 0U) {
300 args->arg2 = args->arg4;
301 }
Varun Wadekar7a1ba292019-01-02 16:30:01 -0800302
303 /* Profiler Carveout Base */
304 args->arg3 = args->arg5;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800305}
306#endif
Varun Wadekarb316e242015-05-19 16:48:04 +0530307
308/*******************************************************************************
309 * Initialize the gic, configure the SCR.
310 ******************************************************************************/
311void bl31_platform_setup(void)
312{
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700313 /*
314 * Add timestamp for platform setup entry.
315 */
316 boot_profiler_add_record("[TF] plat setup entry");
317
Varun Wadekarb7b45752015-12-28 14:55:41 -0800318 /* Initialize the gic cpu and distributor interfaces */
319 plat_gic_setup();
320
Varun Wadekarb316e242015-05-19 16:48:04 +0530321 /*
322 * Setup secondary CPU POR infrastructure.
323 */
324 plat_secondary_setup();
325
326 /*
327 * Initial Memory Controller configuration.
328 */
329 tegra_memctrl_setup();
330
331 /*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800332 * Set up the TZRAM memory aperture to allow only secure world
333 * access
334 */
335 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
336
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700337 /*
Dilan Lee1f66f3d2017-10-27 09:51:09 +0800338 * Late setup handler to allow platforms to performs additional
339 * functionality.
340 * This handler gets called with MMU enabled.
341 */
342 plat_late_platform_setup();
343
344 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700345 * Add timestamp for platform setup exit.
346 */
347 boot_profiler_add_record("[TF] plat setup exit");
348
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530349 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530350}
351
352/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800353 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
354 ******************************************************************************/
355void bl31_plat_runtime_setup(void)
356{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700357 /*
Harvey Hsieh359be952017-08-21 15:01:53 +0800358 * During cold boot, it is observed that the arbitration
359 * bit is set in the Memory controller leading to false
360 * error interrupts in the non-secure world. To avoid
361 * this, clean the interrupt status register before
362 * booting into the non-secure world
363 */
364 tegra_memctrl_clear_pending_interrupts();
365
366 /*
Varun Wadekarc92050b2017-03-29 14:57:29 -0700367 * During boot, USB3 and flash media (SDMMC/SATA) devices need
368 * access to IRAM. Because these clients connect to the MC and
369 * do not have a direct path to the IRAM, the MC implements AHB
370 * redirection during boot to allow path to IRAM. In this mode
371 * accesses to a programmed memory address aperture are directed
372 * to the AHB bus, allowing access to the IRAM. This mode must be
373 * disabled before we jump to the non-secure world.
374 */
375 tegra_memctrl_disable_ahb_redirection();
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700376
377 /*
378 * Add final timestamp before exiting BL31.
379 */
380 boot_profiler_add_record("[TF] bl31 exit");
381 boot_profiler_deinit();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800382}
383
384/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530385 * Perform the very early platform specific architectural setup here. At the
386 * moment this only intializes the mmu in a quick and dirty way.
387 ******************************************************************************/
388void bl31_plat_arch_setup(void)
389{
Varun Wadekarfda095f2019-01-02 10:48:18 -0800390 uint64_t rw_start = BL31_RW_START;
391 uint64_t rw_size = BL31_RW_END - BL31_RW_START;
392 uint64_t rodata_start = BL31_RODATA_BASE;
393 uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
394 uint64_t code_base = TEXT_START;
395 uint64_t code_size = TEXT_END - TEXT_START;
Varun Wadekarb316e242015-05-19 16:48:04 +0530396 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530397#if USE_COHERENT_MEM
Varun Wadekarfda095f2019-01-02 10:48:18 -0800398 uint32_t coh_start, coh_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530399#endif
Varun Wadekarfda095f2019-01-02 10:48:18 -0800400 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530401
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700402 /*
403 * Add timestamp for arch setup entry.
404 */
405 boot_profiler_add_record("[TF] arch setup entry");
406
Varun Wadekarb316e242015-05-19 16:48:04 +0530407 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800408 mmap_add_region(rw_start, rw_start,
409 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530410 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800411 mmap_add_region(rodata_start, rodata_start,
412 rodata_size,
413 MT_RO_DATA | MT_SECURE);
414 mmap_add_region(code_base, code_base,
415 code_size,
416 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530417
Varun Wadekard1513632016-03-18 13:01:12 -0700418 /* map TZDRAM used by BL31 as coherent memory */
419 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
420 mmap_add_region(params_from_bl2->tzdram_base,
421 params_from_bl2->tzdram_base,
422 BL31_SIZE,
423 MT_DEVICE | MT_RW | MT_SECURE);
424 }
425
Varun Wadekarb316e242015-05-19 16:48:04 +0530426#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900427 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
428 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
Varun Wadekar207cc732015-07-08 12:57:50 +0530429
Varun Wadekarb316e242015-05-19 16:48:04 +0530430 mmap_add_region(coh_start, coh_start,
431 coh_size,
Varun Wadekarfda095f2019-01-02 10:48:18 -0800432 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
Varun Wadekarb316e242015-05-19 16:48:04 +0530433#endif
434
Steven Kao4d160ac2016-12-23 16:05:13 +0800435 /* map on-chip free running uS timer */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800436 mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0),
437 page_align(TEGRA_TMRUS_BASE, 0),
438 TEGRA_TMRUS_SIZE,
439 (uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE);
Steven Kao4d160ac2016-12-23 16:05:13 +0800440
Varun Wadekarb316e242015-05-19 16:48:04 +0530441 /* add MMIO space */
442 plat_mmio_map = plat_get_mmio_map();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800443 if (plat_mmio_map != NULL) {
Varun Wadekarb316e242015-05-19 16:48:04 +0530444 mmap_add(plat_mmio_map);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800445 } else {
Varun Wadekarb316e242015-05-19 16:48:04 +0530446 WARN("MMIO map not available\n");
Varun Wadekarfda095f2019-01-02 10:48:18 -0800447 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530448
449 /* set up translation tables */
450 init_xlat_tables();
451
452 /* enable the MMU */
453 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530454
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700455 /*
456 * Add timestamp for arch setup exit.
457 */
458 boot_profiler_add_record("[TF] arch setup exit");
459
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530460 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530461}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530462
463/*******************************************************************************
464 * Check if the given NS DRAM range is valid
465 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -0800466int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
Varun Wadekar7a269e22015-06-10 14:04:32 +0530467{
Varun Wadekarc74343c2017-07-20 09:43:28 -0700468 uint64_t end = base + size_in_bytes - U(1);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800469 int32_t ret = 0;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530470
471 /*
472 * Check if the NS DRAM address is valid
473 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700474 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
475 (end > TEGRA_DRAM_END)) {
476
Varun Wadekar7a269e22015-06-10 14:04:32 +0530477 ERROR("NS address is out-of-bounds!\n");
Varun Wadekarfda095f2019-01-02 10:48:18 -0800478 ret = -EFAULT;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530479 }
480
481 /*
482 * TZDRAM aperture contains the BL31 and BL32 images, so we need
483 * to check if the NS DRAM range overlaps the TZDRAM aperture.
484 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700485 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
Varun Wadekar7a269e22015-06-10 14:04:32 +0530486 ERROR("NS address overlaps TZDRAM!\n");
Varun Wadekarfda095f2019-01-02 10:48:18 -0800487 ret = -ENOTSUP;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530488 }
489
490 /* valid NS address */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800491 return ret;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530492}