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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <bl31.h>
11#include <bl_common.h>
12#include <console.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053013#include <cortex_a53.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010014#include <cortex_a57.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053015#include <debug.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053016#include <denver.h>
Varun Wadekar7a269e22015-06-10 14:04:32 +053017#include <errno.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053018#include <memctrl.h>
19#include <mmio.h>
20#include <platform.h>
21#include <platform_def.h>
22#include <stddef.h>
Varun Wadekarb41a4142016-05-23 15:56:14 -070023#include <string.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080024#include <tegra_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053025#include <tegra_private.h>
Joel Hutton5cc3bc82018-03-21 11:40:57 +000026#include <utils_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053027
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080028/* length of Trusty's input parameters (in bytes) */
29#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
30
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010031extern void memcpy16(void *dest, const void *src, unsigned int length);
Varun Wadekarb41a4142016-05-23 15:56:14 -070032extern void zeromem16(void *mem, unsigned int length);
33
Varun Wadekarb316e242015-05-19 16:48:04 +053034/*******************************************************************************
35 * Declarations of linker defined symbols which will help us find the layout
36 * of trusted SRAM
37 ******************************************************************************/
Joel Hutton5cc3bc82018-03-21 11:40:57 +000038
39IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
40IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
41IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE);
42IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END);
43IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START);
44IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END);
Varun Wadekarb316e242015-05-19 16:48:04 +053045
Varun Wadekarb316e242015-05-19 16:48:04 +053046extern uint64_t tegra_bl31_phys_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053047extern uint64_t tegra_console_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053048
Varun Wadekarb316e242015-05-19 16:48:04 +053049
Varun Wadekar52a15982015-06-05 12:57:27 +053050static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053051static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarc8bfe2e2015-07-31 10:03:01 +053052 .tzdram_size = (uint64_t)TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053053};
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080054static unsigned long bl32_mem_size;
55static unsigned long bl32_boot_params;
Varun Wadekarb316e242015-05-19 16:48:04 +053056
57/*******************************************************************************
58 * This variable holds the non-secure image entry address
59 ******************************************************************************/
60extern uint64_t ns_image_entrypoint;
61
62/*******************************************************************************
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070063 * The following platform setup functions are weakly defined. They
64 * provide typical implementations that will be overridden by a SoC.
65 ******************************************************************************/
66#pragma weak plat_early_platform_setup
Varun Wadekard22d4ad2016-05-23 11:41:07 -070067#pragma weak plat_get_bl31_params
68#pragma weak plat_get_bl31_plat_params
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070069
70void plat_early_platform_setup(void)
71{
72 ; /* do nothing */
73}
74
Varun Wadekard22d4ad2016-05-23 11:41:07 -070075bl31_params_t *plat_get_bl31_params(void)
76{
77 return NULL;
78}
79
80plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
81{
82 return NULL;
83}
84
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070085/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +053086 * Return a pointer to the 'entry_point_info' structure of the next image for
87 * security state specified. BL33 corresponds to the non-secure image type
88 * while BL32 corresponds to the secure image type.
89 ******************************************************************************/
90entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
91{
92 if (type == NON_SECURE)
93 return &bl33_image_ep_info;
94
Varun Wadekar197a75f2016-06-06 10:46:28 -070095 /* return BL32 entry point info if it is valid */
96 if (type == SECURE && bl32_image_ep_info.pc)
Varun Wadekar52a15982015-06-05 12:57:27 +053097 return &bl32_image_ep_info;
98
Varun Wadekarb316e242015-05-19 16:48:04 +053099 return NULL;
100}
101
102/*******************************************************************************
103 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
104 * passes this platform specific information.
105 ******************************************************************************/
106plat_params_from_bl2_t *bl31_get_plat_params(void)
107{
108 return &plat_bl31_params_from_bl2;
109}
110
111/*******************************************************************************
112 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
113 * info.
114 ******************************************************************************/
115void bl31_early_platform_setup(bl31_params_t *from_bl2,
116 void *plat_params_from_bl2)
117{
118 plat_params_from_bl2_t *plat_params =
119 (plat_params_from_bl2_t *)plat_params_from_bl2;
Varun Wadekarb41a4142016-05-23 15:56:14 -0700120 image_info_t bl32_img_info = { {0} };
121 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530122
Varun Wadekarb316e242015-05-19 16:48:04 +0530123 /*
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700124 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
125 * there's no argument to relay from a previous bootloader. Platforms
126 * might use custom ways to get arguments, so provide handlers which
127 * they can override.
128 */
129 if (from_bl2 == NULL)
130 from_bl2 = plat_get_bl31_params();
131 if (plat_params == NULL)
132 plat_params = plat_get_bl31_plat_params();
133
134 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530135 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530136 * They are stored in Secure RAM, in BL2's address space.
137 */
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700138 assert(from_bl2);
Varun Wadekar6bb62462015-10-06 12:49:31 +0530139 assert(from_bl2->bl33_ep_info);
140 bl33_image_ep_info = *from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530141
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800142 if (from_bl2->bl32_ep_info) {
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530143 bl32_image_ep_info = *from_bl2->bl32_ep_info;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800144 bl32_mem_size = from_bl2->bl32_ep_info->args.arg0;
145 bl32_boot_params = from_bl2->bl32_ep_info->args.arg2;
146 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530147
148 /*
Varun Wadekar6bb62462015-10-06 12:49:31 +0530149 * Parse platform specific parameters - TZDRAM aperture base and size
Varun Wadekarb316e242015-05-19 16:48:04 +0530150 */
Varun Wadekar6bb62462015-10-06 12:49:31 +0530151 assert(plat_params);
152 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
153 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530154 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
155
156 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700157 * It is very important that we run either from TZDRAM or TZSRAM base.
158 * Add an explicit check here.
159 */
160 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
161 (TEGRA_TZRAM_BASE != BL31_BASE))
162 panic();
163
164 /*
Varun Wadekard2014c62015-10-29 10:37:28 +0530165 * Get the base address of the UART controller to be used for the
166 * console
167 */
Varun Wadekard2014c62015-10-29 10:37:28 +0530168 tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
169
Damon Duan777baa52016-11-07 19:37:50 +0800170 if (tegra_console_base != (uint64_t)0) {
171 /*
172 * Configure the UART port to be used as the console
173 */
174 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
175 TEGRA_CONSOLE_BAUDRATE);
Damon Duan777baa52016-11-07 19:37:50 +0800176 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530177
Varun Wadekar5118b532016-06-04 22:08:50 -0700178 /*
Steven Kao27e64312016-10-21 14:16:59 +0800179 * Initialize delay timer
180 */
181 tegra_delay_timer_init();
182
183 /*
Varun Wadekar5118b532016-06-04 22:08:50 -0700184 * Do initial security configuration to allow DRAM/device access.
185 */
186 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
187 plat_bl31_params_from_bl2.tzdram_size);
188
Varun Wadekarb41a4142016-05-23 15:56:14 -0700189 /*
190 * The previous bootloader might not have placed the BL32 image
191 * inside the TZDRAM. We check the BL32 image info to find out
192 * the base/PC values and relocate the image if necessary.
193 */
194 if (from_bl2->bl32_image_info) {
195
196 bl32_img_info = *from_bl2->bl32_image_info;
197
198 /* Relocate BL32 if it resides outside of the TZDRAM */
199 tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
200 tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
201 plat_bl31_params_from_bl2.tzdram_size;
202 bl32_start = bl32_img_info.image_base;
203 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
204
205 assert(tzdram_end > tzdram_start);
206 assert(bl32_end > bl32_start);
207 assert(bl32_image_ep_info.pc > tzdram_start);
208 assert(bl32_image_ep_info.pc < tzdram_end);
209
210 /* relocate BL32 */
211 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
212
213 INFO("Relocate BL32 to TZDRAM\n");
214
215 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
216 (void *)(uintptr_t)bl32_start,
217 bl32_img_info.image_size);
218
219 /* clean up non-secure intermediate buffer */
220 zeromem16((void *)(uintptr_t)bl32_start,
221 bl32_img_info.image_size);
222 }
223 }
224
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -0700225 /* Early platform setup for Tegra SoCs */
226 plat_early_platform_setup();
227
Sandrine Bailleuxfff61b62018-06-21 11:41:43 +0200228 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
229 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
230 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530231}
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800232
233#ifdef SPD_trusty
234void plat_trusty_set_boot_args(aapcs64_params_t *args)
235{
236 args->arg0 = bl32_mem_size;
237 args->arg1 = bl32_boot_params;
238 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
239}
240#endif
Varun Wadekarb316e242015-05-19 16:48:04 +0530241
242/*******************************************************************************
243 * Initialize the gic, configure the SCR.
244 ******************************************************************************/
245void bl31_platform_setup(void)
246{
247 uint32_t tmp_reg;
248
Varun Wadekarb7b45752015-12-28 14:55:41 -0800249 /* Initialize the gic cpu and distributor interfaces */
250 plat_gic_setup();
251
Varun Wadekarb316e242015-05-19 16:48:04 +0530252 /*
253 * Setup secondary CPU POR infrastructure.
254 */
255 plat_secondary_setup();
256
257 /*
258 * Initial Memory Controller configuration.
259 */
260 tegra_memctrl_setup();
261
262 /*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800263 * Set up the TZRAM memory aperture to allow only secure world
264 * access
265 */
266 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
267
Varun Wadekarb316e242015-05-19 16:48:04 +0530268 /* Set the next EL to be AArch64 */
269 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
270 write_scr(tmp_reg);
271
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530272 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530273}
274
275/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800276 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
277 ******************************************************************************/
278void bl31_plat_runtime_setup(void)
279{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700280 /*
281 * During boot, USB3 and flash media (SDMMC/SATA) devices need
282 * access to IRAM. Because these clients connect to the MC and
283 * do not have a direct path to the IRAM, the MC implements AHB
284 * redirection during boot to allow path to IRAM. In this mode
285 * accesses to a programmed memory address aperture are directed
286 * to the AHB bus, allowing access to the IRAM. This mode must be
287 * disabled before we jump to the non-secure world.
288 */
289 tegra_memctrl_disable_ahb_redirection();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800290}
291
292/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530293 * Perform the very early platform specific architectural setup here. At the
294 * moment this only intializes the mmu in a quick and dirty way.
295 ******************************************************************************/
296void bl31_plat_arch_setup(void)
297{
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800298 unsigned long rw_start = BL31_RW_START;
299 unsigned long rw_size = BL31_RW_END - BL31_RW_START;
300 unsigned long rodata_start = BL31_RODATA_BASE;
301 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
Joel Hutton5cc3bc82018-03-21 11:40:57 +0000302 unsigned long code_base = TEXT_START;
303 unsigned long code_size = TEXT_END - TEXT_START;
Varun Wadekarb316e242015-05-19 16:48:04 +0530304 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530305#if USE_COHERENT_MEM
Varun Wadekar207cc732015-07-08 12:57:50 +0530306 unsigned long coh_start, coh_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530307#endif
Varun Wadekard1513632016-03-18 13:01:12 -0700308 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530309
310 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800311 mmap_add_region(rw_start, rw_start,
312 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530313 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800314 mmap_add_region(rodata_start, rodata_start,
315 rodata_size,
316 MT_RO_DATA | MT_SECURE);
317 mmap_add_region(code_base, code_base,
318 code_size,
319 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530320
Varun Wadekard1513632016-03-18 13:01:12 -0700321 /* map TZDRAM used by BL31 as coherent memory */
322 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
323 mmap_add_region(params_from_bl2->tzdram_base,
324 params_from_bl2->tzdram_base,
325 BL31_SIZE,
326 MT_DEVICE | MT_RW | MT_SECURE);
327 }
328
Varun Wadekarb316e242015-05-19 16:48:04 +0530329#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900330 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
331 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
Varun Wadekar207cc732015-07-08 12:57:50 +0530332
Varun Wadekarb316e242015-05-19 16:48:04 +0530333 mmap_add_region(coh_start, coh_start,
334 coh_size,
335 MT_DEVICE | MT_RW | MT_SECURE);
336#endif
337
Steven Kao4d160ac2016-12-23 16:05:13 +0800338 /* map on-chip free running uS timer */
339 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
340 page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
341 (uint64_t)TEGRA_TMRUS_SIZE,
342 MT_DEVICE | MT_RO | MT_SECURE);
343
Varun Wadekarb316e242015-05-19 16:48:04 +0530344 /* add MMIO space */
345 plat_mmio_map = plat_get_mmio_map();
346 if (plat_mmio_map)
347 mmap_add(plat_mmio_map);
348 else
349 WARN("MMIO map not available\n");
350
351 /* set up translation tables */
352 init_xlat_tables();
353
354 /* enable the MMU */
355 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530356
357 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530358}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530359
360/*******************************************************************************
361 * Check if the given NS DRAM range is valid
362 ******************************************************************************/
363int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
364{
Varun Wadekar55902982017-01-25 13:35:27 -0800365 uint64_t end = base + size_in_bytes;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530366
367 /*
368 * Check if the NS DRAM address is valid
369 */
Varun Wadekar55902982017-01-25 13:35:27 -0800370 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) {
Varun Wadekar7a269e22015-06-10 14:04:32 +0530371 ERROR("NS address is out-of-bounds!\n");
372 return -EFAULT;
373 }
374
375 /*
376 * TZDRAM aperture contains the BL31 and BL32 images, so we need
377 * to check if the NS DRAM range overlaps the TZDRAM aperture.
378 */
379 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
380 ERROR("NS address overlaps TZDRAM!\n");
381 return -ENOTSUP;
382 }
383
384 /* valid NS address */
385 return 0;
386}