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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar3fb854f2017-02-28 08:23:59 -08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl31.h>
35#include <bl_common.h>
36#include <console.h>
37#include <cortex_a57.h>
38#include <cortex_a53.h>
39#include <debug.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053040#include <denver.h>
Varun Wadekar7a269e22015-06-10 14:04:32 +053041#include <errno.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053042#include <memctrl.h>
43#include <mmio.h>
44#include <platform.h>
45#include <platform_def.h>
46#include <stddef.h>
Varun Wadekarb41a4142016-05-23 15:56:14 -070047#include <string.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080048#include <tegra_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053049#include <tegra_private.h>
50
Varun Wadekarb41a4142016-05-23 15:56:14 -070051extern void zeromem16(void *mem, unsigned int length);
52
Varun Wadekarb316e242015-05-19 16:48:04 +053053/*******************************************************************************
54 * Declarations of linker defined symbols which will help us find the layout
55 * of trusted SRAM
56 ******************************************************************************/
Varun Wadekar3fb854f2017-02-28 08:23:59 -080057extern unsigned long __TEXT_START__;
58extern unsigned long __TEXT_END__;
59extern unsigned long __RW_START__;
60extern unsigned long __RW_END__;
61extern unsigned long __RODATA_START__;
62extern unsigned long __RODATA_END__;
Varun Wadekarb316e242015-05-19 16:48:04 +053063extern unsigned long __BL31_END__;
64
Varun Wadekarb316e242015-05-19 16:48:04 +053065extern uint64_t tegra_bl31_phys_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053066extern uint64_t tegra_console_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053067
68/*
69 * The next 3 constants identify the extents of the code, RO data region and the
70 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
71 * therefore they must be page-aligned. It is the responsibility of the linker
72 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
73 * refer to page-aligned addresses.
74 */
Varun Wadekar3fb854f2017-02-28 08:23:59 -080075#define BL31_RW_START (unsigned long)(&__RW_START__)
76#define BL31_RW_END (unsigned long)(&__RW_END__)
77#define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__)
78#define BL31_RODATA_END (unsigned long)(&__RODATA_END__)
Varun Wadekarb316e242015-05-19 16:48:04 +053079#define BL31_END (unsigned long)(&__BL31_END__)
80
Varun Wadekar52a15982015-06-05 12:57:27 +053081static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053082static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarc8bfe2e2015-07-31 10:03:01 +053083 .tzdram_size = (uint64_t)TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053084};
85
86/*******************************************************************************
87 * This variable holds the non-secure image entry address
88 ******************************************************************************/
89extern uint64_t ns_image_entrypoint;
90
91/*******************************************************************************
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070092 * The following platform setup functions are weakly defined. They
93 * provide typical implementations that will be overridden by a SoC.
94 ******************************************************************************/
95#pragma weak plat_early_platform_setup
Varun Wadekard22d4ad2016-05-23 11:41:07 -070096#pragma weak plat_get_bl31_params
97#pragma weak plat_get_bl31_plat_params
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070098
99void plat_early_platform_setup(void)
100{
101 ; /* do nothing */
102}
103
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700104bl31_params_t *plat_get_bl31_params(void)
105{
106 return NULL;
107}
108
109plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
110{
111 return NULL;
112}
113
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -0700114/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530115 * Return a pointer to the 'entry_point_info' structure of the next image for
116 * security state specified. BL33 corresponds to the non-secure image type
117 * while BL32 corresponds to the secure image type.
118 ******************************************************************************/
119entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
120{
121 if (type == NON_SECURE)
122 return &bl33_image_ep_info;
123
Varun Wadekar197a75f2016-06-06 10:46:28 -0700124 /* return BL32 entry point info if it is valid */
125 if (type == SECURE && bl32_image_ep_info.pc)
Varun Wadekar52a15982015-06-05 12:57:27 +0530126 return &bl32_image_ep_info;
127
Varun Wadekarb316e242015-05-19 16:48:04 +0530128 return NULL;
129}
130
131/*******************************************************************************
132 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
133 * passes this platform specific information.
134 ******************************************************************************/
135plat_params_from_bl2_t *bl31_get_plat_params(void)
136{
137 return &plat_bl31_params_from_bl2;
138}
139
140/*******************************************************************************
141 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
142 * info.
143 ******************************************************************************/
144void bl31_early_platform_setup(bl31_params_t *from_bl2,
145 void *plat_params_from_bl2)
146{
147 plat_params_from_bl2_t *plat_params =
148 (plat_params_from_bl2_t *)plat_params_from_bl2;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530149#if DEBUG
150 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
151#endif
Varun Wadekarb41a4142016-05-23 15:56:14 -0700152 image_info_t bl32_img_info = { {0} };
153 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530154
Varun Wadekarb316e242015-05-19 16:48:04 +0530155 /*
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700156 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
157 * there's no argument to relay from a previous bootloader. Platforms
158 * might use custom ways to get arguments, so provide handlers which
159 * they can override.
160 */
161 if (from_bl2 == NULL)
162 from_bl2 = plat_get_bl31_params();
163 if (plat_params == NULL)
164 plat_params = plat_get_bl31_plat_params();
165
166 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530167 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530168 * They are stored in Secure RAM, in BL2's address space.
169 */
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700170 assert(from_bl2);
Varun Wadekar6bb62462015-10-06 12:49:31 +0530171 assert(from_bl2->bl33_ep_info);
172 bl33_image_ep_info = *from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530173
174 if (from_bl2->bl32_ep_info)
175 bl32_image_ep_info = *from_bl2->bl32_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +0530176
177 /*
Varun Wadekar6bb62462015-10-06 12:49:31 +0530178 * Parse platform specific parameters - TZDRAM aperture base and size
Varun Wadekarb316e242015-05-19 16:48:04 +0530179 */
Varun Wadekar6bb62462015-10-06 12:49:31 +0530180 assert(plat_params);
181 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
182 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530183 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
184
185 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700186 * It is very important that we run either from TZDRAM or TZSRAM base.
187 * Add an explicit check here.
188 */
189 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
190 (TEGRA_TZRAM_BASE != BL31_BASE))
191 panic();
192
193 /*
Varun Wadekard2014c62015-10-29 10:37:28 +0530194 * Get the base address of the UART controller to be used for the
195 * console
196 */
Varun Wadekard2014c62015-10-29 10:37:28 +0530197 tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
198
Damon Duan777baa52016-11-07 19:37:50 +0800199 if (tegra_console_base != (uint64_t)0) {
200 /*
201 * Configure the UART port to be used as the console
202 */
203 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
204 TEGRA_CONSOLE_BAUDRATE);
Damon Duan777baa52016-11-07 19:37:50 +0800205 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530206
Varun Wadekar5118b532016-06-04 22:08:50 -0700207 /*
Steven Kao27e64312016-10-21 14:16:59 +0800208 * Initialize delay timer
209 */
210 tegra_delay_timer_init();
211
212 /*
Varun Wadekar5118b532016-06-04 22:08:50 -0700213 * Do initial security configuration to allow DRAM/device access.
214 */
215 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
216 plat_bl31_params_from_bl2.tzdram_size);
217
Varun Wadekarb41a4142016-05-23 15:56:14 -0700218 /*
219 * The previous bootloader might not have placed the BL32 image
220 * inside the TZDRAM. We check the BL32 image info to find out
221 * the base/PC values and relocate the image if necessary.
222 */
223 if (from_bl2->bl32_image_info) {
224
225 bl32_img_info = *from_bl2->bl32_image_info;
226
227 /* Relocate BL32 if it resides outside of the TZDRAM */
228 tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
229 tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
230 plat_bl31_params_from_bl2.tzdram_size;
231 bl32_start = bl32_img_info.image_base;
232 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
233
234 assert(tzdram_end > tzdram_start);
235 assert(bl32_end > bl32_start);
236 assert(bl32_image_ep_info.pc > tzdram_start);
237 assert(bl32_image_ep_info.pc < tzdram_end);
238
239 /* relocate BL32 */
240 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
241
242 INFO("Relocate BL32 to TZDRAM\n");
243
244 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
245 (void *)(uintptr_t)bl32_start,
246 bl32_img_info.image_size);
247
248 /* clean up non-secure intermediate buffer */
249 zeromem16((void *)(uintptr_t)bl32_start,
250 bl32_img_info.image_size);
251 }
252 }
253
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -0700254 /* Early platform setup for Tegra SoCs */
255 plat_early_platform_setup();
256
Varun Wadekard2014c62015-10-29 10:37:28 +0530257 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
258 "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530259}
260
261/*******************************************************************************
262 * Initialize the gic, configure the SCR.
263 ******************************************************************************/
264void bl31_platform_setup(void)
265{
266 uint32_t tmp_reg;
267
Varun Wadekarb7b45752015-12-28 14:55:41 -0800268 /* Initialize the gic cpu and distributor interfaces */
269 plat_gic_setup();
270
Varun Wadekarb316e242015-05-19 16:48:04 +0530271 /*
272 * Setup secondary CPU POR infrastructure.
273 */
274 plat_secondary_setup();
275
276 /*
277 * Initial Memory Controller configuration.
278 */
279 tegra_memctrl_setup();
280
281 /*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800282 * Set up the TZRAM memory aperture to allow only secure world
283 * access
284 */
285 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
286
Varun Wadekarb316e242015-05-19 16:48:04 +0530287 /* Set the next EL to be AArch64 */
288 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
289 write_scr(tmp_reg);
290
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530291 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530292}
293
294/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800295 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
296 ******************************************************************************/
297void bl31_plat_runtime_setup(void)
298{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700299 /*
300 * During boot, USB3 and flash media (SDMMC/SATA) devices need
301 * access to IRAM. Because these clients connect to the MC and
302 * do not have a direct path to the IRAM, the MC implements AHB
303 * redirection during boot to allow path to IRAM. In this mode
304 * accesses to a programmed memory address aperture are directed
305 * to the AHB bus, allowing access to the IRAM. This mode must be
306 * disabled before we jump to the non-secure world.
307 */
308 tegra_memctrl_disable_ahb_redirection();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800309}
310
311/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530312 * Perform the very early platform specific architectural setup here. At the
313 * moment this only intializes the mmu in a quick and dirty way.
314 ******************************************************************************/
315void bl31_plat_arch_setup(void)
316{
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800317 unsigned long rw_start = BL31_RW_START;
318 unsigned long rw_size = BL31_RW_END - BL31_RW_START;
319 unsigned long rodata_start = BL31_RODATA_BASE;
320 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
321 unsigned long code_base = (unsigned long)(&__TEXT_START__);
322 unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base;
Varun Wadekarb316e242015-05-19 16:48:04 +0530323 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530324#if USE_COHERENT_MEM
Varun Wadekar207cc732015-07-08 12:57:50 +0530325 unsigned long coh_start, coh_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530326#endif
Varun Wadekard1513632016-03-18 13:01:12 -0700327 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530328
329 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800330 mmap_add_region(rw_start, rw_start,
331 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530332 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800333 mmap_add_region(rodata_start, rodata_start,
334 rodata_size,
335 MT_RO_DATA | MT_SECURE);
336 mmap_add_region(code_base, code_base,
337 code_size,
338 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530339
Varun Wadekard1513632016-03-18 13:01:12 -0700340 /* map TZDRAM used by BL31 as coherent memory */
341 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
342 mmap_add_region(params_from_bl2->tzdram_base,
343 params_from_bl2->tzdram_base,
344 BL31_SIZE,
345 MT_DEVICE | MT_RW | MT_SECURE);
346 }
347
Varun Wadekarb316e242015-05-19 16:48:04 +0530348#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900349 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
350 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
Varun Wadekar207cc732015-07-08 12:57:50 +0530351
Varun Wadekarb316e242015-05-19 16:48:04 +0530352 mmap_add_region(coh_start, coh_start,
353 coh_size,
354 MT_DEVICE | MT_RW | MT_SECURE);
355#endif
356
Steven Kao4d160ac2016-12-23 16:05:13 +0800357 /* map on-chip free running uS timer */
358 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
359 page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
360 (uint64_t)TEGRA_TMRUS_SIZE,
361 MT_DEVICE | MT_RO | MT_SECURE);
362
Varun Wadekarb316e242015-05-19 16:48:04 +0530363 /* add MMIO space */
364 plat_mmio_map = plat_get_mmio_map();
365 if (plat_mmio_map)
366 mmap_add(plat_mmio_map);
367 else
368 WARN("MMIO map not available\n");
369
370 /* set up translation tables */
371 init_xlat_tables();
372
373 /* enable the MMU */
374 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530375
376 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530377}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530378
379/*******************************************************************************
380 * Check if the given NS DRAM range is valid
381 ******************************************************************************/
382int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
383{
Varun Wadekar55902982017-01-25 13:35:27 -0800384 uint64_t end = base + size_in_bytes;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530385
386 /*
387 * Check if the NS DRAM address is valid
388 */
Varun Wadekar55902982017-01-25 13:35:27 -0800389 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) {
Varun Wadekar7a269e22015-06-10 14:04:32 +0530390 ERROR("NS address is out-of-bounds!\n");
391 return -EFAULT;
392 }
393
394 /*
395 * TZDRAM aperture contains the BL31 and BL32 images, so we need
396 * to check if the NS DRAM range overlaps the TZDRAM aperture.
397 */
398 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
399 ERROR("NS address overlaps TZDRAM!\n");
400 return -ENOTSUP;
401 }
402
403 /* valid NS address */
404 return 0;
405}