blob: 9ec4bcdf0efe4a48dc2fd1abed584ae8359673d3 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
Toshiyuki Ogasahara58ff4b22021-07-12 19:05:06 +09002 * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Scott Brandene5dcf982020-08-25 13:49:32 -07007#include <inttypes.h>
8#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <string.h>
10
Marek Vasut93c85fc2018-10-02 20:45:18 +020011#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020013#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014
15#include <arch_helpers.h>
16#include <bl1/bl1.h>
17#include <common/bl_common.h>
18#include <common/debug.h>
19#include <common/desc_image_load.h>
Marek Vasutb25ee352021-02-13 19:09:29 +010020#include <common/image_decompress.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <drivers/console.h>
Toshiyuki Ogasahara04f16282019-12-13 14:43:52 +090022#include <drivers/io/io_driver.h>
23#include <drivers/io/io_storage.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <lib/mmio.h>
25#include <lib/xlat_tables/xlat_tables_defs.h>
26#include <plat/common/platform.h>
Marek Vasutb25ee352021-02-13 19:09:29 +010027#if RCAR_GEN3_BL33_GZIP == 1
28#include <tf_gunzip.h>
29#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020030
31#include "avs_driver.h"
32#include "boot_init_dram.h"
33#include "cpg_registers.h"
34#include "board.h"
35#include "emmc_def.h"
36#include "emmc_hal.h"
37#include "emmc_std.h"
38
39#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
40#include "iic_dvfs.h"
41#endif
42
43#include "io_common.h"
Toshiyuki Ogasahara04f16282019-12-13 14:43:52 +090044#include "io_rcar.h"
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020045#include "qos_init.h"
46#include "rcar_def.h"
47#include "rcar_private.h"
48#include "rcar_version.h"
49#include "rom_api.h"
50
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -060051#if RCAR_BL2_DCACHE == 1
52/*
53 * Following symbols are only used during plat_arch_setup() only
54 * when RCAR_BL2_DCACHE is enabled.
55 */
56static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
57static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020058
59#if USE_COHERENT_MEM
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -060060static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
61static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
62#endif
63
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020064#endif
65
66extern void plat_rcar_gic_driver_init(void);
67extern void plat_rcar_gic_init(void);
68extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
69extern void bl2_system_cpg_init(void);
70extern void bl2_secure_setting(void);
71extern void bl2_cpg_init(void);
72extern void rcar_io_emmc_setup(void);
73extern void rcar_io_setup(void);
74extern void rcar_swdt_release(void);
75extern void rcar_swdt_init(void);
76extern void rcar_rpc_init(void);
77extern void rcar_pfc_init(void);
78extern void rcar_dma_init(void);
79
Marek Vasut1eca7782018-12-28 20:12:13 +010080static void bl2_init_generic_timer(void);
81
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020082/* R-Car Gen3 product check */
83#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
Marek Vasut9cadc782019-08-06 19:13:22 +020084#define TARGET_PRODUCT PRR_PRODUCT_H3
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020085#define TARGET_NAME "R-Car H3"
86#elif RCAR_LSI == RCAR_M3
Marek Vasut9cadc782019-08-06 19:13:22 +020087#define TARGET_PRODUCT PRR_PRODUCT_M3
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020088#define TARGET_NAME "R-Car M3"
89#elif RCAR_LSI == RCAR_M3N
Marek Vasut9cadc782019-08-06 19:13:22 +020090#define TARGET_PRODUCT PRR_PRODUCT_M3N
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020091#define TARGET_NAME "R-Car M3N"
Valentine Barshakf2184142018-10-30 02:06:17 +030092#elif RCAR_LSI == RCAR_V3M
Marek Vasut9cadc782019-08-06 19:13:22 +020093#define TARGET_PRODUCT PRR_PRODUCT_V3M
Valentine Barshakf2184142018-10-30 02:06:17 +030094#define TARGET_NAME "R-Car V3M"
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020095#elif RCAR_LSI == RCAR_E3
Marek Vasut9cadc782019-08-06 19:13:22 +020096#define TARGET_PRODUCT PRR_PRODUCT_E3
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020097#define TARGET_NAME "R-Car E3"
Marek Vasut4ae342c2019-01-05 13:56:03 +010098#elif RCAR_LSI == RCAR_D3
Marek Vasut9cadc782019-08-06 19:13:22 +020099#define TARGET_PRODUCT PRR_PRODUCT_D3
Marek Vasut4ae342c2019-01-05 13:56:03 +0100100#define TARGET_NAME "R-Car D3"
Marek Vasut94cc0f82018-12-28 20:11:26 +0100101#elif RCAR_LSI == RCAR_AUTO
Valentine Barshakf2184142018-10-30 02:06:17 +0300102#define TARGET_NAME "R-Car H3/M3/M3N/V3M"
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200103#endif
104
105#if (RCAR_LSI == RCAR_E3)
106#define GPIO_INDT (GPIO_INDT6)
107#define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U)
108#else
109#define GPIO_INDT (GPIO_INDT1)
110#define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U)
111#endif
112
113CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
114 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
115 assert_bl31_params_do_not_fit_in_shared_memory);
116
117static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
118
Marek Vasut93c85fc2018-10-02 20:45:18 +0200119/* FDT with DRAM configuration */
120uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
121static void *fdt = (void *)fdt_blob;
122
123static void unsigned_num_print(unsigned long long int unum, unsigned int radix,
124 char *string)
125{
126 /* Just need enough space to store 64 bit decimal integer */
127 char num_buf[20];
128 int i = 0;
129 unsigned int rem;
130
131 do {
132 rem = unum % radix;
133 if (rem < 0xa)
134 num_buf[i] = '0' + rem;
135 else
136 num_buf[i] = 'a' + (rem - 0xa);
137 i++;
138 unum /= radix;
139 } while (unum > 0U);
140
141 while (--i >= 0)
142 *string++ = num_buf[i];
Marek Vasut64299332020-04-11 19:02:29 +0200143 *string = 0;
Marek Vasut93c85fc2018-10-02 20:45:18 +0200144}
145
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200146#if (RCAR_LOSSY_ENABLE == 1)
147typedef struct bl2_lossy_info {
148 uint32_t magic;
149 uint32_t a0;
150 uint32_t b0;
151} bl2_lossy_info_t;
152
Marek Vasut4d693c22018-10-11 16:53:58 +0200153static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
154 uint64_t end_addr, uint32_t format,
155 uint32_t enable, int fcnlnode)
156{
157 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
158 char nodename[40] = { 0 };
159 int ret, node;
160
161 /* Ignore undefined addresses */
162 if (start_addr == 0 && end_addr == 0)
163 return;
164
165 snprintf(nodename, sizeof(nodename), "lossy-decompression@");
166 unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
167
168 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
169 if (ret < 0) {
170 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
171 panic();
172 }
173
174 ret = fdt_setprop_string(fdt, node, "compatible",
175 "renesas,lossy-decompression");
176 if (ret < 0) {
177 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret);
178 panic();
179 }
180
181 ret = fdt_appendprop_string(fdt, node, "compatible",
182 "shared-dma-pool");
183 if (ret < 0) {
184 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret);
185 panic();
186 }
187
188 ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
189 if (ret < 0) {
190 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
191 panic();
192 }
193
194 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
195 if (ret < 0) {
196 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
197 panic();
198 }
199
200 ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
201 if (ret < 0) {
202 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
203 panic();
204 }
205
206 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
207 if (ret < 0) {
208 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
209 panic();
210 }
211}
212
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200213static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
214 uint64_t end_addr, uint32_t format,
Marek Vasut4d693c22018-10-11 16:53:58 +0200215 uint32_t enable, int fcnlnode)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200216{
217 bl2_lossy_info_t info;
218 uint32_t reg;
219
Marek Vasut4d693c22018-10-11 16:53:58 +0200220 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
221
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200222 reg = format | (start_addr >> 20);
223 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
224 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
225 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
226
227 info.magic = 0x12345678U;
228 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
229 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
230
231 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
232 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
233 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
234
235 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
236 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
237 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
238}
239#endif
240
241void bl2_plat_flush_bl31_params(void)
242{
243 uint32_t product_cut, product, cut;
244 uint32_t boot_dev, boot_cpu;
245 uint32_t lcs, reg, val;
246
247 reg = mmio_read_32(RCAR_MODEMR);
248 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
249
250 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
251 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
252 emmc_terminate();
253
254 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
255 bl2_secure_setting();
256
257 reg = mmio_read_32(RCAR_PRR);
Marek Vasut9cadc782019-08-06 19:13:22 +0200258 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
259 product = reg & PRR_PRODUCT_MASK;
260 cut = reg & PRR_CUT_MASK;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200261
Marek Vasut9cadc782019-08-06 19:13:22 +0200262 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200263 goto tlb;
264
Marek Vasut9cadc782019-08-06 19:13:22 +0200265 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200266 goto tlb;
267
268 /* Disable MFIS write protection */
269 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
270
271tlb:
272 reg = mmio_read_32(RCAR_MODEMR);
273 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
274 if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
275 boot_cpu != MODEMR_BOOT_CPU_CA53)
276 goto mmu;
277
Marek Vasut9cadc782019-08-06 19:13:22 +0200278 if (product_cut == PRR_PRODUCT_H3_CUT20) {
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200279 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
280 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
281 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
282 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
283 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
284 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
Marek Vasut9cadc782019-08-06 19:13:22 +0200285 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
286 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200287 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
288 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
Marek Vasut9cadc782019-08-06 19:13:22 +0200289 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
290 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200291 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
Marek Vasute6208012018-12-31 16:48:04 +0100292 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200293 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
294 }
295
Marek Vasut9cadc782019-08-06 19:13:22 +0200296 if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
297 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
298 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
299 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200300 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
301 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
302 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
303
304 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
305 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
306 }
307
308mmu:
309 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
310 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
311
312 val = rcar_rom_get_lcs(&lcs);
313 if (val) {
314 ERROR("BL2: Failed to get the LCS. (%d)\n", val);
315 panic();
316 }
317
318 if (lcs == LCS_SE)
319 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
320
321 rcar_swdt_release();
322 bl2_system_cpg_init();
323
324#if RCAR_BL2_DCACHE == 1
325 /* Disable data cache (clean and invalidate) */
326 disable_mmu_el3();
327#endif
328}
329
330static uint32_t is_ddr_backup_mode(void)
331{
332#if RCAR_SYSTEM_SUSPEND
333 static uint32_t reason = RCAR_COLD_BOOT;
334 static uint32_t once;
335
336#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
337 uint8_t data;
338#endif
339 if (once)
340 return reason;
341
342 once = 1;
343 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
344 return reason;
345
346#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
347 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
348 ERROR("BL2: REG Keep10 READ ERROR.\n");
349 panic();
350 }
351
352 if (KEEP10_MAGIC != data)
353 reason = RCAR_WARM_BOOT;
354#else
355 reason = RCAR_WARM_BOOT;
356#endif
357 return reason;
358#else
359 return RCAR_COLD_BOOT;
360#endif
361}
362
Marek Vasutb25ee352021-02-13 19:09:29 +0100363#if RCAR_GEN3_BL33_GZIP == 1
364void bl2_plat_preload_setup(void)
365{
366 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip);
367}
368#endif
369
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200370int bl2_plat_handle_pre_image_load(unsigned int image_id)
371{
372 u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
373 bl_mem_params_node_t *bl_mem_params;
374
Marek Vasutb25ee352021-02-13 19:09:29 +0100375 bl_mem_params = get_bl_mem_params_node(image_id);
376
377#if RCAR_GEN3_BL33_GZIP == 1
378 if (image_id == BL33_IMAGE_ID) {
379 image_decompress_prepare(&bl_mem_params->image_info);
380 }
381#endif
382
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200383 if (image_id != BL31_IMAGE_ID)
384 return 0;
385
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200386 if (is_ddr_backup_mode() == RCAR_COLD_BOOT)
387 goto cold_boot;
388
389 *boot_kind = RCAR_WARM_BOOT;
390 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
391
392 console_flush();
393 bl2_plat_flush_bl31_params();
394
395 /* will not return */
396 bl2_enter_bl31(&bl_mem_params->ep_info);
397
398cold_boot:
399 *boot_kind = RCAR_COLD_BOOT;
400 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
401
402 return 0;
403}
404
Toshiyuki Ogasahara04f16282019-12-13 14:43:52 +0900405static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest)
406{
407 uint32_t cert, len;
408 int ret;
409
410 ret = rcar_get_certificate(certid, &cert);
411 if (ret) {
412 ERROR("%s : cert file load error", __func__);
413 return 1;
414 }
415
416 rcar_read_certificate((uint64_t) cert, &len, dest);
417
418 return 0;
419}
420
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200421int bl2_plat_handle_post_image_load(unsigned int image_id)
422{
423 static bl2_to_bl31_params_mem_t *params;
424 bl_mem_params_node_t *bl_mem_params;
Toshiyuki Ogasahara04f16282019-12-13 14:43:52 +0900425 uintptr_t dest;
426 int ret;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200427
428 if (!params) {
429 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
430 memset((void *)PARAMS_BASE, 0, sizeof(*params));
431 }
432
433 bl_mem_params = get_bl_mem_params_node(image_id);
434
435 switch (image_id) {
436 case BL31_IMAGE_ID:
Toshiyuki Ogasahara04f16282019-12-13 14:43:52 +0900437 ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID,
438 &dest);
439 if (!ret)
440 bl_mem_params->image_info.image_base = dest;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200441 break;
442 case BL32_IMAGE_ID:
Toshiyuki Ogasahara04f16282019-12-13 14:43:52 +0900443 ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID,
444 &dest);
445 if (!ret)
446 bl_mem_params->image_info.image_base = dest;
447
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200448 memcpy(&params->bl32_ep_info, &bl_mem_params->ep_info,
449 sizeof(entry_point_info_t));
450 break;
451 case BL33_IMAGE_ID:
Marek Vasutb25ee352021-02-13 19:09:29 +0100452#if RCAR_GEN3_BL33_GZIP == 1
453 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) {
454 /* decompress gzip-compressed image */
455 ret = image_decompress(&bl_mem_params->image_info);
456 if (ret != 0) {
457 return ret;
458 }
459 } else {
460 /* plain image, copy it in place */
461 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE,
462 bl_mem_params->image_info.image_size);
463 }
464#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200465 memcpy(&params->bl33_ep_info, &bl_mem_params->ep_info,
466 sizeof(entry_point_info_t));
467 break;
468 }
469
470 return 0;
471}
472
Marek Vasutc7077c62018-12-26 15:57:08 +0100473struct meminfo *bl2_plat_sec_mem_layout(void)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200474{
475 return &bl2_tzram_layout;
476}
477
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100478static void bl2_populate_compatible_string(void *dt)
Marek Vasuta987b002018-10-11 16:15:41 +0200479{
480 uint32_t board_type;
481 uint32_t board_rev;
482 uint32_t reg;
483 int ret;
484
Marek Vasut688251a2020-01-06 03:26:43 +0100485 fdt_setprop_u32(dt, 0, "#address-cells", 2);
486 fdt_setprop_u32(dt, 0, "#size-cells", 2);
487
Marek Vasuta987b002018-10-11 16:15:41 +0200488 /* Populate compatible string */
489 rcar_get_board_type(&board_type, &board_rev);
490 switch (board_type) {
491 case BOARD_SALVATOR_X:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100492 ret = fdt_setprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200493 "renesas,salvator-x");
494 break;
495 case BOARD_SALVATOR_XS:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100496 ret = fdt_setprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200497 "renesas,salvator-xs");
498 break;
499 case BOARD_STARTER_KIT:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100500 ret = fdt_setprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200501 "renesas,m3ulcb");
502 break;
503 case BOARD_STARTER_KIT_PRE:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100504 ret = fdt_setprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200505 "renesas,h3ulcb");
506 break;
Valentine Barshakf2184142018-10-30 02:06:17 +0300507 case BOARD_EAGLE:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100508 ret = fdt_setprop_string(dt, 0, "compatible",
Valentine Barshakf2184142018-10-30 02:06:17 +0300509 "renesas,eagle");
510 break;
Marek Vasuta987b002018-10-11 16:15:41 +0200511 case BOARD_EBISU:
512 case BOARD_EBISU_4D:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100513 ret = fdt_setprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200514 "renesas,ebisu");
515 break;
Marek Vasut4ae342c2019-01-05 13:56:03 +0100516 case BOARD_DRAAK:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100517 ret = fdt_setprop_string(dt, 0, "compatible",
Marek Vasut4ae342c2019-01-05 13:56:03 +0100518 "renesas,draak");
519 break;
Marek Vasuta987b002018-10-11 16:15:41 +0200520 default:
521 NOTICE("BL2: Cannot set compatible string, board unsupported\n");
522 panic();
523 }
524
525 if (ret < 0) {
526 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
527 panic();
528 }
529
530 reg = mmio_read_32(RCAR_PRR);
Marek Vasut9cadc782019-08-06 19:13:22 +0200531 switch (reg & PRR_PRODUCT_MASK) {
532 case PRR_PRODUCT_H3:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100533 ret = fdt_appendprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200534 "renesas,r8a7795");
535 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200536 case PRR_PRODUCT_M3:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100537 ret = fdt_appendprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200538 "renesas,r8a7796");
539 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200540 case PRR_PRODUCT_M3N:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100541 ret = fdt_appendprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200542 "renesas,r8a77965");
543 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200544 case PRR_PRODUCT_V3M:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100545 ret = fdt_appendprop_string(dt, 0, "compatible",
Valentine Barshakf2184142018-10-30 02:06:17 +0300546 "renesas,r8a77970");
547 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200548 case PRR_PRODUCT_E3:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100549 ret = fdt_appendprop_string(dt, 0, "compatible",
Marek Vasuta987b002018-10-11 16:15:41 +0200550 "renesas,r8a77990");
551 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200552 case PRR_PRODUCT_D3:
Justin Chadwell7d0e3ba2019-09-17 15:21:50 +0100553 ret = fdt_appendprop_string(dt, 0, "compatible",
Marek Vasut4ae342c2019-01-05 13:56:03 +0100554 "renesas,r8a77995");
555 break;
Marek Vasuta987b002018-10-11 16:15:41 +0200556 default:
557 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
558 panic();
559 }
560
561 if (ret < 0) {
562 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
563 panic();
564 }
565}
566
Marek Vasute7618e72021-07-10 17:59:05 +0200567static void bl2_add_rpc_node(void)
568{
569#if (RCAR_RPC_HYPERFLASH_LOCKED == 0)
570 int ret, node;
571
572 node = ret = fdt_add_subnode(fdt, 0, "soc");
573 if (ret < 0) {
574 goto err;
575 }
576
Geert Uytterhoeven5480bd12022-03-23 14:21:31 +0100577 node = ret = fdt_add_subnode(fdt, node, "spi@ee200000");
Marek Vasute7618e72021-07-10 17:59:05 +0200578 if (ret < 0) {
579 goto err;
580 }
581
582 ret = fdt_setprop_string(fdt, node, "status", "okay");
583 if (ret < 0) {
584 goto err;
585 }
586
587 return;
588err:
589 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret);
590 panic();
591#endif
592}
593
Marek Vasut5ca408a2021-04-16 21:25:27 +0200594static void bl2_add_dram_entry(uint64_t start, uint64_t size)
Marek Vasut6a6881a2018-10-02 20:43:09 +0200595{
Marek Vasut93c85fc2018-10-02 20:45:18 +0200596 char nodename[32] = { 0 };
Marek Vasut93c85fc2018-10-02 20:45:18 +0200597 uint64_t fdtsize;
Marek Vasut5ca408a2021-04-16 21:25:27 +0200598 int ret, node;
599
600 fdtsize = cpu_to_fdt64(size);
601
602 snprintf(nodename, sizeof(nodename), "memory@");
603 unsigned_num_print(start, 16, nodename + strlen(nodename));
604 node = ret = fdt_add_subnode(fdt, 0, nodename);
605 if (ret < 0) {
606 goto err;
607 }
608
609 ret = fdt_setprop_string(fdt, node, "device_type", "memory");
610 if (ret < 0) {
611 goto err;
612 }
613
614 ret = fdt_setprop_u64(fdt, node, "reg", start);
615 if (ret < 0) {
616 goto err;
617 }
618
619 ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
620 sizeof(fdtsize));
621 if (ret < 0) {
622 goto err;
623 }
624
625 return;
626err:
Scott Brandene5dcf982020-08-25 13:49:32 -0700627 NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n",
Marek Vasut5ca408a2021-04-16 21:25:27 +0200628 start, start + size - 1, ret);
629 panic();
630}
631
632static void bl2_advertise_dram_entries(uint64_t dram_config[8])
633{
Marek Vasut9601d5a2021-04-16 21:39:36 +0200634 uint64_t start, size, size32;
Marek Vasut5ca408a2021-04-16 21:25:27 +0200635 int chan;
Marek Vasut6a6881a2018-10-02 20:43:09 +0200636
637 for (chan = 0; chan < 4; chan++) {
638 start = dram_config[2 * chan];
639 size = dram_config[2 * chan + 1];
640 if (!size)
641 continue;
642
Scott Brandene5dcf982020-08-25 13:49:32 -0700643 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
Marek Vasut89c17512019-03-30 04:01:41 +0100644 chan, start, start + size - 1,
645 (size >> 30) ? : size >> 20,
646 (size >> 30) ? "G" : "M");
Marek Vasut6a6881a2018-10-02 20:43:09 +0200647 }
Marek Vasut93c85fc2018-10-02 20:45:18 +0200648
649 /*
650 * We add the DT nodes in reverse order here. The fdt_add_subnode()
651 * adds the DT node before the first existing DT node, so we have
652 * to add them in reverse order to get nodes sorted by address in
653 * the resulting DT.
654 */
655 for (chan = 3; chan >= 0; chan--) {
656 start = dram_config[2 * chan];
657 size = dram_config[2 * chan + 1];
658 if (!size)
659 continue;
660
661 /*
662 * Channel 0 is mapped in 32bit space and the first
Marek Vasut9601d5a2021-04-16 21:39:36 +0200663 * 128 MiB are reserved and the maximum size is 2GiB.
Marek Vasut93c85fc2018-10-02 20:45:18 +0200664 */
665 if (chan == 0) {
Marek Vasut9601d5a2021-04-16 21:39:36 +0200666 /* Limit the 32bit entry to 2 GiB - 128 MiB */
667 size32 = size - 0x8000000U;
668 if (size32 >= 0x78000000U) {
669 size32 = 0x78000000U;
670 }
671
672 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */
673 bl2_add_dram_entry(0x48000000, size32);
674
675 /*
676 * If channel 0 is less than 2 GiB long, the
677 * entire memory fits into the 32bit space entry,
678 * so move on to the next channel.
679 */
680 if (size <= 0x80000000U) {
681 continue;
682 }
683
684 /*
685 * If channel 0 is more than 2 GiB long, emit
686 * another entry which covers the rest of the
687 * memory in channel 0, in the 64bit space.
688 *
689 * Start of this new entry is at 2 GiB offset
690 * from the beginning of the 64bit channel 0
691 * address, size is 2 GiB shorter than total
692 * size of the channel.
693 */
694 start += 0x80000000U;
695 size -= 0x80000000U;
Marek Vasut93c85fc2018-10-02 20:45:18 +0200696 }
697
Marek Vasut5ca408a2021-04-16 21:25:27 +0200698 bl2_add_dram_entry(start, size);
Marek Vasut93c85fc2018-10-02 20:45:18 +0200699 }
Marek Vasut6a6881a2018-10-02 20:43:09 +0200700}
701
Marek Vasutb0e13592018-10-02 14:53:27 +0200702static void bl2_advertise_dram_size(uint32_t product)
Marek Vasut673bc322018-10-02 13:33:32 +0200703{
Marek Vasut6a6881a2018-10-02 20:43:09 +0200704 uint64_t dram_config[8] = {
705 [0] = 0x400000000ULL,
706 [2] = 0x500000000ULL,
707 [4] = 0x600000000ULL,
708 [6] = 0x700000000ULL,
709 };
Toshiyuki Ogasahara58ff4b22021-07-12 19:05:06 +0900710 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
Marek Vasut6a6881a2018-10-02 20:43:09 +0200711
Marek Vasut9963f702018-10-02 15:09:04 +0200712 switch (product) {
Marek Vasut9cadc782019-08-06 19:13:22 +0200713 case PRR_PRODUCT_H3:
Marek Vasut673bc322018-10-02 13:33:32 +0200714#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
715 /* 4GB(1GBx4) */
Marek Vasut6a6881a2018-10-02 20:43:09 +0200716 dram_config[1] = 0x40000000ULL;
717 dram_config[3] = 0x40000000ULL;
718 dram_config[5] = 0x40000000ULL;
719 dram_config[7] = 0x40000000ULL;
Marek Vasut673bc322018-10-02 13:33:32 +0200720#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
721 (RCAR_DRAM_CHANNEL == 5) && \
722 (RCAR_DRAM_SPLIT == 2)
723 /* 4GB(2GBx2 2ch split) */
Marek Vasut6a6881a2018-10-02 20:43:09 +0200724 dram_config[1] = 0x80000000ULL;
725 dram_config[3] = 0x80000000ULL;
Marek Vasut673bc322018-10-02 13:33:32 +0200726#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
727 /* 8GB(2GBx4: default) */
Marek Vasut6a6881a2018-10-02 20:43:09 +0200728 dram_config[1] = 0x80000000ULL;
729 dram_config[3] = 0x80000000ULL;
730 dram_config[5] = 0x80000000ULL;
731 dram_config[7] = 0x80000000ULL;
Marek Vasut673bc322018-10-02 13:33:32 +0200732#endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
Marek Vasut9963f702018-10-02 15:09:04 +0200733 break;
Marek Vasut673bc322018-10-02 13:33:32 +0200734
Marek Vasut9cadc782019-08-06 19:13:22 +0200735 case PRR_PRODUCT_M3:
Toshiyuki Ogasahara58ff4b22021-07-12 19:05:06 +0900736 if (cut < PRR_PRODUCT_30) {
Marek Vasut0208c942019-03-09 16:10:59 +0100737#if (RCAR_GEN3_ULCB == 1)
Toshiyuki Ogasahara58ff4b22021-07-12 19:05:06 +0900738 /* 2GB(1GBx2 2ch split) */
739 dram_config[1] = 0x40000000ULL;
740 dram_config[5] = 0x40000000ULL;
Marek Vasut0208c942019-03-09 16:10:59 +0100741#else
Toshiyuki Ogasahara58ff4b22021-07-12 19:05:06 +0900742 /* 4GB(2GBx2 2ch split) */
743 dram_config[1] = 0x80000000ULL;
744 dram_config[5] = 0x80000000ULL;
Marek Vasut0208c942019-03-09 16:10:59 +0100745#endif
Toshiyuki Ogasahara58ff4b22021-07-12 19:05:06 +0900746 } else {
747 /* 8GB(2GBx4 2ch split) */
748 dram_config[1] = 0x100000000ULL;
749 dram_config[5] = 0x100000000ULL;
750 }
Marek Vasut9963f702018-10-02 15:09:04 +0200751 break;
752
Marek Vasut9cadc782019-08-06 19:13:22 +0200753 case PRR_PRODUCT_M3N:
Toshiyuki Ogasahara67e19522020-12-15 18:22:16 +0900754#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
755 /* 4GB(4GBx1) */
756 dram_config[1] = 0x100000000ULL;
757#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1)
Marek Vasut9963f702018-10-02 15:09:04 +0200758 /* 2GB(1GBx2) */
Marek Vasut6a6881a2018-10-02 20:43:09 +0200759 dram_config[1] = 0x80000000ULL;
Toshiyuki Ogasahara67e19522020-12-15 18:22:16 +0900760#endif
Marek Vasut9963f702018-10-02 15:09:04 +0200761 break;
762
Marek Vasut9cadc782019-08-06 19:13:22 +0200763 case PRR_PRODUCT_V3M:
Valentine Barshakf2184142018-10-30 02:06:17 +0300764 /* 1GB(512MBx2) */
765 dram_config[1] = 0x40000000ULL;
766 break;
767
Marek Vasut9cadc782019-08-06 19:13:22 +0200768 case PRR_PRODUCT_E3:
Marek Vasut673bc322018-10-02 13:33:32 +0200769#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
770 /* 1GB(512MBx2) */
Marek Vasut6a6881a2018-10-02 20:43:09 +0200771 dram_config[1] = 0x40000000ULL;
Marek Vasut673bc322018-10-02 13:33:32 +0200772#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
773 /* 2GB(512MBx4) */
Marek Vasut6a6881a2018-10-02 20:43:09 +0200774 dram_config[1] = 0x80000000ULL;
Marek Vasut8cb12ec2018-10-02 13:51:19 +0200775#elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
776 /* 4GB(1GBx4) */
Marek Vasut6a6881a2018-10-02 20:43:09 +0200777 dram_config[1] = 0x100000000ULL;
Marek Vasut673bc322018-10-02 13:33:32 +0200778#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
Marek Vasut9963f702018-10-02 15:09:04 +0200779 break;
Marek Vasut4ae342c2019-01-05 13:56:03 +0100780
Marek Vasut9cadc782019-08-06 19:13:22 +0200781 case PRR_PRODUCT_D3:
Marek Vasut4ae342c2019-01-05 13:56:03 +0100782 /* 512MB */
783 dram_config[1] = 0x20000000ULL;
784 break;
Marek Vasut673bc322018-10-02 13:33:32 +0200785 }
Marek Vasut6a6881a2018-10-02 20:43:09 +0200786
787 bl2_advertise_dram_entries(dram_config);
Marek Vasut673bc322018-10-02 13:33:32 +0200788}
789
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200790void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
791 u_register_t arg3, u_register_t arg4)
792{
793 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
Marek Vasutb0e13592018-10-02 14:53:27 +0200794 uint32_t product, product_cut, major, minor;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200795 int32_t ret;
796 const char *str;
797 const char *unknown = "unknown";
798 const char *cpu_ca57 = "CA57";
799 const char *cpu_ca53 = "CA53";
800 const char *product_m3n = "M3N";
801 const char *product_h3 = "H3";
802 const char *product_m3 = "M3";
803 const char *product_e3 = "E3";
Marek Vasut4ae342c2019-01-05 13:56:03 +0100804 const char *product_d3 = "D3";
Valentine Barshakf2184142018-10-30 02:06:17 +0300805 const char *product_v3m = "V3M";
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200806 const char *lcs_secure = "SE";
807 const char *lcs_cm = "CM";
808 const char *lcs_dm = "DM";
809 const char *lcs_sd = "SD";
810 const char *lcs_fa = "FA";
811 const char *sscg_off = "PLL1 nonSSCG Clock select";
812 const char *sscg_on = "PLL1 SSCG Clock select";
813 const char *boot_hyper80 = "HyperFlash(80MHz)";
814 const char *boot_qspi40 = "QSPI Flash(40MHz)";
815 const char *boot_qspi80 = "QSPI Flash(80MHz)";
816 const char *boot_emmc25x1 = "eMMC(25MHz x1)";
817 const char *boot_emmc50x8 = "eMMC(50MHz x8)";
Marek Vasut4ae342c2019-01-05 13:56:03 +0100818#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200819 const char *boot_hyper160 = "HyperFlash(150MHz)";
820#else
821 const char *boot_hyper160 = "HyperFlash(160MHz)";
822#endif
Marek Vasut4d693c22018-10-11 16:53:58 +0200823#if (RCAR_LOSSY_ENABLE == 1)
824 int fcnlnode;
825#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200826
Marek Vasut1eca7782018-12-28 20:12:13 +0100827 bl2_init_generic_timer();
828
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200829 reg = mmio_read_32(RCAR_MODEMR);
830 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
831 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
832
833 bl2_cpg_init();
834
835 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
836 boot_cpu == MODEMR_BOOT_CPU_CA53) {
837 rcar_pfc_init();
Marek Vasut0aa268e2019-05-18 19:29:16 +0200838 rcar_console_boot_init();
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200839 }
840
841 plat_rcar_gic_driver_init();
842 plat_rcar_gic_init();
843 rcar_swdt_init();
844
845 /* FIQ interrupts are taken to EL3 */
846 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
847
848 write_daifclr(DAIF_FIQ_BIT);
849
850 reg = read_midr();
851 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
852 switch (midr) {
853 case MIDR_CA57:
854 str = cpu_ca57;
855 break;
856 case MIDR_CA53:
857 str = cpu_ca53;
858 break;
859 default:
860 str = unknown;
861 break;
862 }
863
864 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
865 version_of_renesas);
866
867 reg = mmio_read_32(RCAR_PRR);
Marek Vasut9cadc782019-08-06 19:13:22 +0200868 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
869 product = reg & PRR_PRODUCT_MASK;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200870
871 switch (product) {
Marek Vasut9cadc782019-08-06 19:13:22 +0200872 case PRR_PRODUCT_H3:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200873 str = product_h3;
874 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200875 case PRR_PRODUCT_M3:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200876 str = product_m3;
877 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200878 case PRR_PRODUCT_M3N:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200879 str = product_m3n;
880 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200881 case PRR_PRODUCT_V3M:
Valentine Barshakf2184142018-10-30 02:06:17 +0300882 str = product_v3m;
883 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200884 case PRR_PRODUCT_E3:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200885 str = product_e3;
886 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200887 case PRR_PRODUCT_D3:
Marek Vasut4ae342c2019-01-05 13:56:03 +0100888 str = product_d3;
889 break;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200890 default:
891 str = unknown;
892 break;
893 }
894
Marek Vasut9cadc782019-08-06 19:13:22 +0200895 if ((PRR_PRODUCT_M3 == product) &&
896 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
897 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
Marek Vasut3af20052019-02-25 14:57:08 +0100898 /* M3 Ver.1.1 or Ver.1.2 */
899 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
900 str);
901 } else {
902 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n",
903 str,
904 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
905 }
Toshiyuki Ogasaharac3c52272021-07-12 19:18:57 +0900906 } else if (product == PRR_PRODUCT_D3) {
907 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) {
908 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str);
909 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
910 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str);
911 } else {
912 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str);
913 }
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200914 } else {
915 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
916 major = major + RCAR_MAJOR_OFFSET;
917 minor = reg & RCAR_MINOR_MASK;
918 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
919 }
920
Toshiyuki Ogasahara9be13a92021-07-12 19:19:39 +0900921 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) {
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200922 reg = mmio_read_32(RCAR_MODEMR);
923 sscg = reg & RCAR_SSCG_MASK;
924 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
925 NOTICE("BL2: %s\n", str);
926 }
927
928 rcar_get_board_type(&type, &rev);
929
930 switch (type) {
931 case BOARD_SALVATOR_X:
932 case BOARD_KRIEK:
933 case BOARD_STARTER_KIT:
934 case BOARD_SALVATOR_XS:
935 case BOARD_EBISU:
936 case BOARD_STARTER_KIT_PRE:
937 case BOARD_EBISU_4D:
Marek Vasut4ae342c2019-01-05 13:56:03 +0100938 case BOARD_DRAAK:
Valentine Barshakf2184142018-10-30 02:06:17 +0300939 case BOARD_EAGLE:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200940 break;
941 default:
942 type = BOARD_UNKNOWN;
943 break;
944 }
945
946 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
947 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
948 else {
949 NOTICE("BL2: Board is %s Rev.%d.%d\n",
950 GET_BOARD_NAME(type),
951 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
952 }
953
954#if RCAR_LSI != RCAR_AUTO
955 if (product != TARGET_PRODUCT) {
956 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
957 ERROR("BL2: Please write the correct IPL to flash memory.\n");
958 panic();
959 }
960#endif
961 rcar_avs_init();
962 rcar_avs_setting();
963
964 switch (boot_dev) {
965 case MODEMR_BOOT_DEV_HYPERFLASH160:
966 str = boot_hyper160;
967 break;
968 case MODEMR_BOOT_DEV_HYPERFLASH80:
969 str = boot_hyper80;
970 break;
971 case MODEMR_BOOT_DEV_QSPI_FLASH40:
972 str = boot_qspi40;
973 break;
974 case MODEMR_BOOT_DEV_QSPI_FLASH80:
975 str = boot_qspi80;
976 break;
977 case MODEMR_BOOT_DEV_EMMC_25X1:
Marek Vasut4ae342c2019-01-05 13:56:03 +0100978#if RCAR_LSI == RCAR_D3
979 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
980 panic();
981#endif
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200982 str = boot_emmc25x1;
983 break;
984 case MODEMR_BOOT_DEV_EMMC_50X8:
985 str = boot_emmc50x8;
986 break;
987 default:
988 str = unknown;
989 break;
990 }
991 NOTICE("BL2: Boot device is %s\n", str);
992
993 rcar_avs_setting();
994 reg = rcar_rom_get_lcs(&lcs);
995 if (reg) {
996 str = unknown;
997 goto lcm_state;
998 }
999
1000 switch (lcs) {
1001 case LCS_CM:
1002 str = lcs_cm;
1003 break;
1004 case LCS_DM:
1005 str = lcs_dm;
1006 break;
1007 case LCS_SD:
1008 str = lcs_sd;
1009 break;
1010 case LCS_SE:
1011 str = lcs_secure;
1012 break;
1013 case LCS_FA:
1014 str = lcs_fa;
1015 break;
1016 default:
1017 str = unknown;
1018 break;
1019 }
1020
1021lcm_state:
1022 NOTICE("BL2: LCM state is %s\n", str);
1023
1024 rcar_avs_end();
1025 is_ddr_backup_mode();
1026
1027 bl2_tzram_layout.total_base = BL31_BASE;
1028 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
1029
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001030 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
1031 boot_cpu == MODEMR_BOOT_CPU_CA53) {
1032 ret = rcar_dram_init();
1033 if (ret) {
1034 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
1035 panic();
1036 }
1037 rcar_qos_init();
1038 }
1039
Marek Vasut93c85fc2018-10-02 20:45:18 +02001040 /* Set up FDT */
1041 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
1042 if (ret) {
1043 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
1044 panic();
1045 }
1046
Marek Vasuta987b002018-10-11 16:15:41 +02001047 /* Add platform compatible string */
1048 bl2_populate_compatible_string(fdt);
1049
Marek Vasute7618e72021-07-10 17:59:05 +02001050 /* Enable RPC if unlocked */
1051 bl2_add_rpc_node();
1052
Marek Vasut63659fd2018-10-02 15:12:15 +02001053 /* Print DRAM layout */
1054 bl2_advertise_dram_size(product);
1055
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001056 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1057 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
1058 if (rcar_emmc_init() != EMMC_SUCCESS) {
1059 NOTICE("BL2: Failed to eMMC driver initialize.\n");
1060 panic();
1061 }
1062 rcar_emmc_memcard_power(EMMC_POWER_ON);
1063 if (rcar_emmc_mount() != EMMC_SUCCESS) {
1064 NOTICE("BL2: Failed to eMMC mount operation.\n");
1065 panic();
1066 }
1067 } else {
1068 rcar_rpc_init();
1069 rcar_dma_init();
1070 }
1071
1072 reg = mmio_read_32(RST_WDTRSTCR);
1073 reg &= ~WDTRSTCR_RWDT_RSTMSK;
1074 reg |= WDTRSTCR_PASSWORD;
1075 mmio_write_32(RST_WDTRSTCR, reg);
1076
1077 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
1078 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
1079
1080 reg = mmio_read_32(RCAR_PRR);
1081 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
1082 mmio_write_32(CPG_CA57DBGRCR,
1083 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
1084
1085 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
1086 mmio_write_32(CPG_CA53DBGRCR,
1087 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
1088
Marek Vasut9cadc782019-08-06 19:13:22 +02001089 if (product_cut == PRR_PRODUCT_H3_CUT10) {
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001090 reg = mmio_read_32(CPG_PLL2CR);
1091 reg &= ~((uint32_t) 1 << 5);
1092 mmio_write_32(CPG_PLL2CR, reg);
1093
1094 reg = mmio_read_32(CPG_PLL4CR);
1095 reg &= ~((uint32_t) 1 << 5);
1096 mmio_write_32(CPG_PLL4CR, reg);
1097
1098 reg = mmio_read_32(CPG_PLL0CR);
1099 reg &= ~((uint32_t) 1 << 12);
1100 mmio_write_32(CPG_PLL0CR, reg);
1101 }
1102#if (RCAR_LOSSY_ENABLE == 1)
1103 NOTICE("BL2: Lossy Decomp areas\n");
Marek Vasut4d693c22018-10-11 16:53:58 +02001104
1105 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
1106 if (fcnlnode < 0) {
1107 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
1108 fcnlnode);
1109 panic();
1110 }
1111
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001112 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
Marek Vasut4d693c22018-10-11 16:53:58 +02001113 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001114 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
Marek Vasut4d693c22018-10-11 16:53:58 +02001115 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001116 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
Marek Vasut4d693c22018-10-11 16:53:58 +02001117 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001118#endif
1119
Marek Vasut93c85fc2018-10-02 20:45:18 +02001120 fdt_pack(fdt);
1121 NOTICE("BL2: FDT at %p\n", fdt);
1122
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001123 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1124 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
1125 rcar_io_emmc_setup();
1126 else
1127 rcar_io_setup();
1128}
1129
1130void bl2_el3_plat_arch_setup(void)
1131{
1132#if RCAR_BL2_DCACHE == 1
1133 NOTICE("BL2: D-Cache enable\n");
1134 rcar_configure_mmu_el3(BL2_BASE,
Marek Vasut2e032c02018-12-26 15:57:08 +01001135 BL2_END - BL2_BASE,
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001136 BL2_RO_BASE, BL2_RO_LIMIT
1137#if USE_COHERENT_MEM
1138 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
1139#endif
1140 );
1141#endif
1142}
1143
1144void bl2_platform_setup(void)
1145{
1146
1147}
Marek Vasut1eca7782018-12-28 20:12:13 +01001148
1149static void bl2_init_generic_timer(void)
1150{
Valentine Barshakf2184142018-10-30 02:06:17 +03001151/* FIXME: V3M 16.666 MHz ? */
Marek Vasut4ae342c2019-01-05 13:56:03 +01001152#if RCAR_LSI == RCAR_D3
1153 uint32_t reg_cntfid = EXTAL_DRAAK;
1154#elif RCAR_LSI == RCAR_E3
Marek Vasut1eca7782018-12-28 20:12:13 +01001155 uint32_t reg_cntfid = EXTAL_EBISU;
1156#else /* RCAR_LSI == RCAR_E3 */
1157 uint32_t reg;
1158 uint32_t reg_cntfid;
1159 uint32_t modemr;
1160 uint32_t modemr_pll;
1161 uint32_t board_type;
1162 uint32_t board_rev;
1163 uint32_t pll_table[] = {
1164 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
1165 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
1166 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
1167 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
1168 };
1169
1170 modemr = mmio_read_32(RCAR_MODEMR);
1171 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
1172
1173 /* Set frequency data in CNTFID0 */
1174 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
Marek Vasut9cadc782019-08-06 19:13:22 +02001175 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
Marek Vasut1eca7782018-12-28 20:12:13 +01001176 switch (modemr_pll) {
1177 case MD14_MD13_TYPE_0:
1178 rcar_get_board_type(&board_type, &board_rev);
1179 if (BOARD_SALVATOR_XS == board_type) {
1180 reg_cntfid = EXTAL_SALVATOR_XS;
1181 }
1182 break;
1183 case MD14_MD13_TYPE_3:
Marek Vasut9cadc782019-08-06 19:13:22 +02001184 if (PRR_PRODUCT_H3_CUT10 == reg) {
Marek Vasut1eca7782018-12-28 20:12:13 +01001185 reg_cntfid = reg_cntfid >> 1U;
1186 }
1187 break;
1188 default:
1189 /* none */
1190 break;
1191 }
1192#endif /* RCAR_LSI == RCAR_E3 */
Elyes Haouas2be03c02023-02-13 09:14:48 +01001193 /* Update memory mapped and register based frequency */
Marek Vasut1eca7782018-12-28 20:12:13 +01001194 write_cntfrq_el0((u_register_t )reg_cntfid);
1195 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
1196 /* Enable counter */
1197 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
1198 (uint32_t)CNTCR_EN);
1199}