| commit | 2be03c06e08df475673ace8137ea2a630f52d7a3 | [log] [tgz] |
|---|---|---|
| author | Elyes Haouas <ehaouas@noos.fr> | Mon Feb 13 09:14:48 2023 +0100 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Tue May 09 15:57:12 2023 +0100 |
| tree | 5085dd0af7deed3a5a52dbcd82a78aa5cd96e888 | |
| parent | 64b7cdcb4c2689a0907c7a063ca2d1369399290d [diff] [blame] |
fix(tree): correct some typos found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index f85db8d..9ec4bcd 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -1190,7 +1190,7 @@ break; } #endif /* RCAR_LSI == RCAR_E3 */ - /* Update memory mapped and register based freqency */ + /* Update memory mapped and register based frequency */ write_cntfrq_el0((u_register_t )reg_cntfid); mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); /* Enable counter */