rcar_gen3: plat: Fix BL2 size check
Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable
BL2 area.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index b0ce069..115190d 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -899,7 +899,7 @@
#if RCAR_BL2_DCACHE == 1
NOTICE("BL2: D-Cache enable\n");
rcar_configure_mmu_el3(BL2_BASE,
- RCAR_SYSRAM_LIMIT - BL2_BASE,
+ BL2_END - BL2_BASE,
BL2_RO_BASE, BL2_RO_LIMIT
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT