diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index b0ce069..115190d 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -899,7 +899,7 @@
 #if RCAR_BL2_DCACHE == 1
 	NOTICE("BL2: D-Cache enable\n");
 	rcar_configure_mmu_el3(BL2_BASE,
-			       RCAR_SYSRAM_LIMIT - BL2_BASE,
+			       BL2_END - BL2_BASE,
 			       BL2_RO_BASE, BL2_RO_LIMIT
 #if USE_COHERENT_MEM
 			       , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT