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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -06002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Varun Wadekar6e6ce612018-06-20 13:43:43 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9#include <errno.h>
10#include <stddef.h>
11#include <string.h>
12
13#include <platform_def.h>
14
Varun Wadekarb316e242015-05-19 16:48:04 +053015#include <arch.h>
16#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <bl31/bl31.h>
18#include <common/bl_common.h>
19#include <common/debug.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053020#include <cortex_a53.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010021#include <cortex_a57.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053022#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/console.h>
24#include <lib/mmio.h>
25#include <lib/utils.h>
26#include <lib/utils_def.h>
27#include <plat/common/platform.h>
28
Varun Wadekarb316e242015-05-19 16:48:04 +053029#include <memctrl.h>
Varun Wadekar4967c3d2017-07-21 13:34:16 -070030#include <profiler.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080031#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080032#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053033#include <tegra_private.h>
34
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080035/* length of Trusty's input parameters (in bytes) */
36#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
37
Varun Wadekarb316e242015-05-19 16:48:04 +053038/*******************************************************************************
39 * Declarations of linker defined symbols which will help us find the layout
40 * of trusted SRAM
41 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -080042IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -060043
Varun Wadekarb316e242015-05-19 16:48:04 +053044extern uint64_t tegra_bl31_phys_base;
45
Varun Wadekar52a15982015-06-05 12:57:27 +053046static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053047static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarfda095f2019-01-02 10:48:18 -080048 .tzdram_size = TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053049};
Varun Wadekar1c4d5e42019-12-17 21:23:24 -080050#ifdef SPD_trusty
51static aapcs64_params_t bl32_args;
52#endif
Varun Wadekarb316e242015-05-19 16:48:04 +053053
54/*******************************************************************************
55 * This variable holds the non-secure image entry address
56 ******************************************************************************/
57extern uint64_t ns_image_entrypoint;
58
59/*******************************************************************************
60 * Return a pointer to the 'entry_point_info' structure of the next image for
61 * security state specified. BL33 corresponds to the non-secure image type
62 * while BL32 corresponds to the secure image type.
63 ******************************************************************************/
64entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
65{
Varun Wadekarfda095f2019-01-02 10:48:18 -080066 entry_point_info_t *ep = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +053067
Varun Wadekar197a75f2016-06-06 10:46:28 -070068 /* return BL32 entry point info if it is valid */
Varun Wadekarfda095f2019-01-02 10:48:18 -080069 if (type == NON_SECURE) {
70 ep = &bl33_image_ep_info;
71 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
72 ep = &bl32_image_ep_info;
73 }
Varun Wadekar52a15982015-06-05 12:57:27 +053074
Varun Wadekarfda095f2019-01-02 10:48:18 -080075 return ep;
Varun Wadekarb316e242015-05-19 16:48:04 +053076}
77
78/*******************************************************************************
79 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
80 * passes this platform specific information.
81 ******************************************************************************/
82plat_params_from_bl2_t *bl31_get_plat_params(void)
83{
84 return &plat_bl31_params_from_bl2;
85}
86
87/*******************************************************************************
88 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
89 * info.
90 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010091void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
92 u_register_t arg2, u_register_t arg3)
Varun Wadekarb316e242015-05-19 16:48:04 +053093{
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010094 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
95 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
Varun Wadekar4967c3d2017-07-21 13:34:16 -070096 int32_t ret;
Varun Wadekarbaf903e2015-09-22 15:00:06 +053097
Varun Wadekarb316e242015-05-19 16:48:04 +053098 /*
Varun Wadekard22d4ad2016-05-23 11:41:07 -070099 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
100 * there's no argument to relay from a previous bootloader. Platforms
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700101 * might use custom ways to get arguments.
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700102 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800103 if (arg_from_bl2 == NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100104 arg_from_bl2 = plat_get_bl31_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800105 }
106 if (plat_params == NULL) {
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700107 plat_params = plat_get_bl31_plat_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800108 }
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700109
110 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530111 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530112 * They are stored in Secure RAM, in BL2's address space.
113 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800114 assert(arg_from_bl2 != NULL);
115 assert(arg_from_bl2->bl33_ep_info != NULL);
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100116 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530117
Varun Wadekarfda095f2019-01-02 10:48:18 -0800118 if (arg_from_bl2->bl32_ep_info != NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100119 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800120#ifdef SPD_trusty
121 /* save BL32 boot parameters */
122 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args));
123#endif
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800124 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530125
126 /*
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800127 * Parse platform specific parameters
Varun Wadekarb316e242015-05-19 16:48:04 +0530128 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800129 assert(plat_params != NULL);
Varun Wadekar6bb62462015-10-06 12:49:31 +0530130 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
131 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530132 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800133 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800134 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
135 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
Varun Wadekard2014c62015-10-29 10:37:28 +0530136
137 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700138 * It is very important that we run either from TZDRAM or TZSRAM base.
139 * Add an explicit check here.
140 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800141 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
142 (TEGRA_TZRAM_BASE != BL31_BASE)) {
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700143 panic();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800144 }
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700145
146 /*
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700147 * Enable console for the platform
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800148 */
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700149 plat_enable_console(plat_params->uart_id);
Varun Wadekard2014c62015-10-29 10:37:28 +0530150
Varun Wadekar5118b532016-06-04 22:08:50 -0700151 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700152 * The previous bootloader passes the base address of the shared memory
153 * location to store the boot profiler logs. Sanity check the
Andreas Färberd829cd42019-06-17 00:06:43 +0200154 * address and initialise the profiler library, if it looks ok.
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700155 */
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700156 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
157 PROFILER_SIZE_BYTES);
158 if (ret == (int32_t)0) {
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700159
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700160 /* store the membase for the profiler lib */
161 plat_bl31_params_from_bl2.boot_profiler_shmem_base =
162 plat_params->boot_profiler_shmem_base;
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700163
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700164 /* initialise the profiler library */
165 boot_profiler_init(plat_params->boot_profiler_shmem_base,
166 TEGRA_TMRUS_BASE);
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700167 }
168
169 /*
170 * Add timestamp for platform early setup entry.
171 */
172 boot_profiler_add_record("[TF] early setup entry");
173
174 /*
Steven Kao27e64312016-10-21 14:16:59 +0800175 * Initialize delay timer
176 */
177 tegra_delay_timer_init();
178
Varun Wadekardbe67c72017-09-20 15:09:38 -0700179 /* Early platform setup for Tegra SoCs */
180 plat_early_platform_setup();
181
Steven Kao27e64312016-10-21 14:16:59 +0800182 /*
Varun Wadekar5118b532016-06-04 22:08:50 -0700183 * Do initial security configuration to allow DRAM/device access.
184 */
185 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
Varun Wadekarfda095f2019-01-02 10:48:18 -0800186 (uint32_t)plat_bl31_params_from_bl2.tzdram_size);
Varun Wadekar5118b532016-06-04 22:08:50 -0700187
Varun Wadekar0ed62702018-06-20 14:30:59 -0700188#if RELOCATE_BL32_IMAGE
Varun Wadekarb41a4142016-05-23 15:56:14 -0700189 /*
190 * The previous bootloader might not have placed the BL32 image
Varun Wadekar0ed62702018-06-20 14:30:59 -0700191 * inside the TZDRAM. Platform handler to allow relocation of BL32
192 * image to TZDRAM memory. This behavior might change per platform.
Varun Wadekarb41a4142016-05-23 15:56:14 -0700193 */
Varun Wadekar0ed62702018-06-20 14:30:59 -0700194 plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
195#endif
Varun Wadekarb41a4142016-05-23 15:56:14 -0700196
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700197 /*
198 * Add timestamp for platform early setup exit.
199 */
200 boot_profiler_add_record("[TF] early setup exit");
201
Sandrine Bailleuxfff61b62018-06-21 11:41:43 +0200202 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
203 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
204 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530205}
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800206
207#ifdef SPD_trusty
208void plat_trusty_set_boot_args(aapcs64_params_t *args)
209{
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800210 /*
211 * arg0 = TZDRAM aperture available for BL32
212 * arg1 = BL32 boot params
213 * arg2 = EKS Blob Length
214 * arg3 = Boot Profiler Carveout Base
215 */
216 args->arg0 = bl32_args.arg0;
217 args->arg1 = bl32_args.arg2;
Varun Wadekarc2099802018-12-28 13:50:20 -0800218
219 /* update EKS size */
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800220 args->arg2 = bl32_args.arg4;
Varun Wadekar7a1ba292019-01-02 16:30:01 -0800221
222 /* Profiler Carveout Base */
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800223 args->arg3 = bl32_args.arg5;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800224}
225#endif
Varun Wadekarb316e242015-05-19 16:48:04 +0530226
227/*******************************************************************************
228 * Initialize the gic, configure the SCR.
229 ******************************************************************************/
230void bl31_platform_setup(void)
231{
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700232 /*
233 * Add timestamp for platform setup entry.
234 */
235 boot_profiler_add_record("[TF] plat setup entry");
236
Varun Wadekarb7b45752015-12-28 14:55:41 -0800237 /* Initialize the gic cpu and distributor interfaces */
238 plat_gic_setup();
239
Varun Wadekarb316e242015-05-19 16:48:04 +0530240 /*
241 * Setup secondary CPU POR infrastructure.
242 */
243 plat_secondary_setup();
244
245 /*
246 * Initial Memory Controller configuration.
247 */
248 tegra_memctrl_setup();
249
250 /*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800251 * Set up the TZRAM memory aperture to allow only secure world
252 * access
253 */
254 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
255
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700256 /*
Dilan Lee1f66f3d2017-10-27 09:51:09 +0800257 * Late setup handler to allow platforms to performs additional
258 * functionality.
259 * This handler gets called with MMU enabled.
260 */
261 plat_late_platform_setup();
262
263 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700264 * Add timestamp for platform setup exit.
265 */
266 boot_profiler_add_record("[TF] plat setup exit");
267
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530268 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530269}
270
271/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800272 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
273 ******************************************************************************/
274void bl31_plat_runtime_setup(void)
275{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700276 /*
Harvey Hsieh359be952017-08-21 15:01:53 +0800277 * During cold boot, it is observed that the arbitration
278 * bit is set in the Memory controller leading to false
279 * error interrupts in the non-secure world. To avoid
280 * this, clean the interrupt status register before
281 * booting into the non-secure world
282 */
283 tegra_memctrl_clear_pending_interrupts();
284
285 /*
Varun Wadekarc92050b2017-03-29 14:57:29 -0700286 * During boot, USB3 and flash media (SDMMC/SATA) devices need
287 * access to IRAM. Because these clients connect to the MC and
288 * do not have a direct path to the IRAM, the MC implements AHB
289 * redirection during boot to allow path to IRAM. In this mode
290 * accesses to a programmed memory address aperture are directed
291 * to the AHB bus, allowing access to the IRAM. This mode must be
292 * disabled before we jump to the non-secure world.
293 */
294 tegra_memctrl_disable_ahb_redirection();
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700295
296 /*
297 * Add final timestamp before exiting BL31.
298 */
299 boot_profiler_add_record("[TF] bl31 exit");
300 boot_profiler_deinit();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800301}
302
303/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530304 * Perform the very early platform specific architectural setup here. At the
305 * moment this only intializes the mmu in a quick and dirty way.
306 ******************************************************************************/
307void bl31_plat_arch_setup(void)
308{
Varun Wadekarfda095f2019-01-02 10:48:18 -0800309 uint64_t rw_start = BL31_RW_START;
Kalyani Chidambaram425155a2018-12-19 11:06:14 -0800310 uint64_t rw_size = BL_END - BL31_RW_START;
311 uint64_t rodata_start = BL_RO_DATA_BASE;
312 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
313 uint64_t code_base = BL_CODE_BASE;
314 uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
Varun Wadekarb316e242015-05-19 16:48:04 +0530315 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarfda095f2019-01-02 10:48:18 -0800316 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530317
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700318 /*
319 * Add timestamp for arch setup entry.
320 */
321 boot_profiler_add_record("[TF] arch setup entry");
322
Varun Wadekar922550a2018-01-23 14:38:51 -0800323 /* add MMIO space */
324 plat_mmio_map = plat_get_mmio_map();
325 if (plat_mmio_map != NULL) {
326 mmap_add(plat_mmio_map);
327 } else {
328 WARN("MMIO map not available\n");
329 }
330
Varun Wadekarb316e242015-05-19 16:48:04 +0530331 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800332 mmap_add_region(rw_start, rw_start,
333 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530334 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800335 mmap_add_region(rodata_start, rodata_start,
336 rodata_size,
337 MT_RO_DATA | MT_SECURE);
338 mmap_add_region(code_base, code_base,
339 code_size,
340 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530341
Varun Wadekar922550a2018-01-23 14:38:51 -0800342 /* map TZDRAM used by BL31 as coherent memory */
343 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
344 mmap_add_region(params_from_bl2->tzdram_base,
345 params_from_bl2->tzdram_base,
346 BL31_SIZE,
347 MT_DEVICE | MT_RW | MT_SECURE);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800348 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530349
350 /* set up translation tables */
351 init_xlat_tables();
352
353 /* enable the MMU */
354 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530355
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700356 /*
357 * Add timestamp for arch setup exit.
358 */
359 boot_profiler_add_record("[TF] arch setup exit");
360
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530361 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530362}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530363
364/*******************************************************************************
365 * Check if the given NS DRAM range is valid
366 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -0800367int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
Varun Wadekar7a269e22015-06-10 14:04:32 +0530368{
Varun Wadekarc74343c2017-07-20 09:43:28 -0700369 uint64_t end = base + size_in_bytes - U(1);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800370 int32_t ret = 0;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530371
372 /*
373 * Check if the NS DRAM address is valid
374 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700375 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
376 (end > TEGRA_DRAM_END)) {
377
Andreas Färber90bbade2019-06-16 23:32:20 +0200378 ERROR("NS address 0x%llx is out-of-bounds!\n", base);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800379 ret = -EFAULT;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530380 }
381
382 /*
383 * TZDRAM aperture contains the BL31 and BL32 images, so we need
384 * to check if the NS DRAM range overlaps the TZDRAM aperture.
385 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700386 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
Andreas Färber90bbade2019-06-16 23:32:20 +0200387 ERROR("NS address 0x%llx overlaps TZDRAM!\n", base);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800388 ret = -ENOTSUP;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530389 }
390
391 /* valid NS address */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800392 return ret;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530393}