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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Masahiro Yamada0b67e562020-03-09 17:39:48 +09002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Masahiro Yamadac5864d82020-04-22 10:50:12 +09007/*
8 * The .data section gets copied from ROM to RAM at runtime.
9 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
10 * aligned regions in it.
11 * Its VMA must be page-aligned as it marks the first read/write page.
12 */
13#define DATA_ALIGN 16
14
Masahiro Yamada0b67e562020-03-09 17:39:48 +090015#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010017
18OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
19OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000020ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010021
22MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010023 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
24 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010025}
26
27SECTIONS
28{
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010029 . = BL1_RO_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000030 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010031 "BL1_RO_BASE address is not aligned on a page boundary.")
32
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010033#if SEPARATE_CODE_AND_RODATA
34 .text . : {
35 __TEXT_START__ = .;
36 *bl1_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050037 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010038 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010039 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010040 __TEXT_END__ = .;
Jorge Troncosoda284d52022-10-20 21:42:06 -070041 } >ROM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010042
Jorge Troncosoda284d52022-10-20 21:42:06 -070043 /* .ARM.extab and .ARM.exidx are only added because Clang need them */
44 .ARM.extab . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010045 *(.ARM.extab* .gnu.linkonce.armextab.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070046 } >ROM
Roberto Vargas1d04c632018-05-10 11:01:16 +010047
Jorge Troncosoda284d52022-10-20 21:42:06 -070048 .ARM.exidx . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010049 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070050 } >ROM
Roberto Vargas1d04c632018-05-10 11:01:16 +010051
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010052 .rodata . : {
53 __RODATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050054 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010055
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090056 RODATA_COMMON
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010057
58 /*
59 * No need to pad out the .rodata section to a page boundary. Next is
60 * the .data section, which can mapped in ROM with the same memory
61 * attributes as the .rodata section.
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080062 *
63 * Pad out to 16 bytes though as .data section needs to be 16 byte
64 * aligned and lld does not align the LMA to the aligment specified
65 * on the .data section.
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010066 */
67 __RODATA_END__ = .;
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080068 . = ALIGN(16);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010069 } >ROM
70#else
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010071 ro . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000072 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000073 *bl1_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050074 *(SORT_BY_ALIGNMENT(.text*))
75 *(SORT_BY_ALIGNMENT(.rodata*))
Soby Mathewc704cbc2014-08-14 11:33:56 +010076
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090077 RODATA_COMMON
Soby Mathewc704cbc2014-08-14 11:33:56 +010078
Achin Guptab739f222014-01-18 16:50:09 +000079 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000080 __RO_END__ = .;
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080081
82 /*
83 * Pad out to 16 bytes as .data section needs to be 16 byte aligned and
84 * lld does not align the LMA to the aligment specified on the .data
85 * section.
86 */
87 . = ALIGN(16);
Achin Gupta4f6ad662013-10-25 09:08:21 +010088 } >ROM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010089#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010090
Soby Mathewc704cbc2014-08-14 11:33:56 +010091 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
92 "cpu_ops not defined for this platform.")
93
Douglas Raillard306593d2017-02-24 18:14:15 +000094 . = BL1_RW_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000095 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
Douglas Raillard306593d2017-02-24 18:14:15 +000096 "BL1_RW_BASE address is not aligned on a page boundary.")
97
Masahiro Yamadac5864d82020-04-22 10:50:12 +090098 DATA_SECTION >RAM AT>ROM
99 __DATA_RAM_START__ = __DATA_START__;
100 __DATA_RAM_END__ = __DATA_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101
Masahiro Yamada403990e2020-04-07 13:04:24 +0900102 STACK_SECTION >RAM
Masahiro Yamadadd053b62020-03-26 13:16:33 +0900103 BSS_SECTION >RAM
Masahiro Yamada0b67e562020-03-09 17:39:48 +0900104 XLAT_TABLE_SECTION >RAM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000105
Soby Mathew2ae20432015-01-08 18:02:44 +0000106#if USE_COHERENT_MEM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000107 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000108 * The base address of the coherent memory section must be page-aligned (4K)
109 * to guarantee that the coherent data are stored on their own pages and
110 * are not mixed with normal data. This is required to set up the correct
111 * memory attributes for the coherent data page tables.
112 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000113 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000114 __COHERENT_RAM_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 *(tzfw_coherent_mem)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000116 __COHERENT_RAM_END_UNALIGNED__ = .;
117 /*
118 * Memory page(s) mapped to this section will be marked
119 * as device memory. No other unexpected data must creep in.
120 * Ensure the rest of the current memory page is unused.
121 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100122 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000123 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100124 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000125#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000127 __BL1_RAM_START__ = ADDR(.data);
128 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000130 __DATA_ROM_START__ = LOADADDR(.data);
131 __DATA_SIZE__ = SIZEOF(.data);
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100132
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100133 /*
134 * The .data section is the last PROGBITS section so its end marks the end
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100135 * of BL1's actual content in Trusted ROM.
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100136 */
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100137 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
138 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
139 "BL1's ROM content has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000141 __BSS_SIZE__ = SIZEOF(.bss);
142
Soby Mathew2ae20432015-01-08 18:02:44 +0000143#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000144 __COHERENT_RAM_UNALIGNED_SIZE__ =
145 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000146#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100148 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149}