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git01.mediatek.com / filogic / uboot / 05b3b5c8f62884d5353f128dc2c5ad996c3256fa / drivers / ddr / fsl / ctrl_regs.c
  1. 1b07ef1 driver/ddr/fsl: Fix MRC_CYC calculation for DDR3 by York Sun · 10 years ago
  2. fbce88c driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots by York Sun · 10 years ago
  3. db20464 linux/kernel.h: sync min, max, min3, max3 macros with Linux by Masahiro Yamada · 10 years ago
  4. a8b3d52 driver/ddr/fsl: Fix DDR4 driver by York Sun · 10 years ago
  5. c1bf24f driver/ddr/fsl: Fix tXP and tCKE by York Sun · 10 years ago
  6. e0f6046 driver/ddr/fsl: Add support of overriding chip select write leveling by York Sun · 10 years ago
  7. 5d6c626 driver/ddr/freescale: Add support of accumulate ECC by York Sun · 10 years ago
  8. f0e4f6d driver/ddr: Fix DDR register timing_cfg_8 by York Sun · 10 years ago
  9. 9982579 powerpc/mpc85xx: Add workaround for DDR erratum A004508 by York Sun · 11 years ago
  10. edbeee1 drivers/ddr: Fix possible out of bounds error by York Sun · 11 years ago
  11. 2896cb7 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver by York Sun · 11 years ago
  12. c459ae6 driver/ddr: Add 256 byte interleaving support by York Sun · 11 years ago
  13. 29647ab driver/ddr: Change Freescale ARM DDR driver to support both big and little endian by York Sun · 11 years ago
  14. 63c91cd powerpc/mpc8xxx: Extend DDR registers' fields by York Sun · 11 years ago
  15. a21803d Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx by York Sun · 11 years ago
  16. f062659 Driver/DDR: Moving Freescale DDR driver to a common driver by York Sun · 11 years ago[Renamed (97%) from arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  17. 0b81093 mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it by Valentin Longchamp · 11 years ago
  18. 4a71741 powerpc: Fix CamelCase warnings in DDR related code by Priyanka Jain · 11 years ago
  19. 26681f5 powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE] by James Yang · 11 years ago
  20. 4889c98 powerpc/mpc8xxx: Add x4 DDR device support by York Sun · 11 years ago
  21. c21a739 powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff by York Sun · 11 years ago
  22. 972cc40 mpc85xx: Base emulator support by York Sun · 11 years ago
  23. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · 11 years ago
  24. 021b7ae mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE by Anatolij Gustschin · 12 years ago
  25. 992562c 8xxx: Change all 8*xx_DDR addresses to 8xxx by Andy Fleming · 12 years ago
  26. 82f576f arch/powerpc/cpu/mpc8xxx/: sparse fixes by Kim Phillips · 12 years ago
  27. 98df4d1 powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation by York Sun · 12 years ago
  28. 7d69ea3 powerpc/mpc8xxx: Update DDR registers by York Sun · 12 years ago
  29. cd077cf powerpc/mpc8xxx: Fix bug for extended DDR timing by York Sun · 12 years ago
  30. e8dc17b powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving by York Sun · 12 years ago
  31. bad8209 powerpc/mpc8xxx: Add support for cas latency 12 and above by York Sun · 12 years ago
  32. d5bbe66 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning by Kumar Gala · 13 years ago
  33. e12ce98 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver by York Sun · 13 years ago
  34. 15f874a powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en by York Sun · 13 years ago
  35. 7a16d64 powerpc/mpc8xxx: Extend CWL table by York Sun · 13 years ago
  36. f8691fc powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time by York Sun · 14 years ago
  37. 4513d76 powerpc/8xxx: Fix typo for address hashing message by Kumar Gala · 14 years ago
  38. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · 14 years ago
  39. 501b70d powerpc/mpc8xxx: disable rcw_en bit for non-DDR3 by York Sun · 14 years ago
  40. 3673f2c powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers by York Sun · 14 years ago
  41. 27f83be powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 by York Sun · 14 years ago
  42. 65b5be2 powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 board by Kumar Gala · 14 years ago
  43. ba0c2eb mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 by York Sun · 14 years ago
  44. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · 14 years ago
  45. 2927c5e Disable unused chip-select for DDR controller interleaving by York Sun · 14 years ago
  46. 5207e77 Fix parameters to support RDIMM for P2020DS by York Sun · 14 years ago
  47. 1714e49 powerpc/8xxx: Improvement to DDR parameters by york · 14 years ago
  48. de87932 powerpc/8xxx: Enable DDR3 RDIMM support by york · 14 years ago
  49. 4260372 powerpc/8xxx: Enabled address hashing for 85xx by york · 14 years ago
  50. f4f93c6 powerpc/8xxx: Enable quad-rank DIMMs. by york · 14 years ago
  51. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · 14 years ago
  52. 8107926 fsl-ddr: Add extra cycle to turnaround times by Dave Liu · 15 years ago
  53. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · 15 years ago[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  54. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · 15 years ago[Renamed from cpu/mpc8xxx/ddr/ctrl_regs.c]
  55. 3525e1a fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 by Dave Liu · 15 years ago
  56. 625b268 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · 15 years ago
  57. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · 15 years ago
  58. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  59. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · 15 years ago
  60. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  61. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  62. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  63. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  64. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  65. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  66. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  67. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  68. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  69. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  70. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  71. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago