blob: 9dc7b63db5d10026577572ff8f98d6a373a89bc7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
wdenk4a9cbbe2002-08-27 09:48:53 +000010#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -060011#include <env.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
Simon Glass1a974af2019-08-01 09:46:36 -060014#include <gzip.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060015#include <image.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
wdenk525d7b62005-01-22 18:13:04 +000017#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000018
Michal Simek02d95c02018-06-04 14:57:34 +020019static long do_fpga_get_device(char *arg)
20{
21 long dev = FPGA_INVALID_DEVICE;
22 char *devstr = env_get("fpga");
23
24 if (devstr)
25 /* Should be strtol to handle -1 cases */
26 dev = simple_strtol(devstr, NULL, 16);
27
Michal Simek19942472018-07-26 15:33:51 +020028 if (dev == FPGA_INVALID_DEVICE && arg)
Michal Simek02d95c02018-06-04 14:57:34 +020029 dev = simple_strtol(arg, NULL, 16);
30
31 debug("%s: device = %ld\n", __func__, dev);
32
33 return dev;
34}
35
Michal Simek6f6be6f2018-06-04 15:51:23 +020036static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
Simon Glassed38aef2020-05-10 11:40:03 -060037 struct cmd_tbl *cmdtp, int argc,
38 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +020039{
40 size_t local_data_size;
41 long local_fpga_data;
42
43 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
44
45 if (argc != cmdtp->maxargs) {
46 debug("fpga: incorrect parameters passed\n");
47 return CMD_RET_USAGE;
48 }
49
50 *dev = do_fpga_get_device(argv[0]);
51
52 local_fpga_data = simple_strtol(argv[1], NULL, 16);
53 if (!local_fpga_data) {
54 debug("fpga: zero fpga_data address\n");
55 return CMD_RET_USAGE;
56 }
57 *fpga_data = local_fpga_data;
58
Simon Glass3ff49ec2021-07-24 09:03:29 -060059 local_data_size = hextoul(argv[2], NULL);
Michal Simek6f6be6f2018-06-04 15:51:23 +020060 if (!local_data_size) {
61 debug("fpga: zero size\n");
62 return CMD_RET_USAGE;
63 }
64 *data_size = local_data_size;
65
66 return 0;
67}
68
Michal Simeka2555972018-05-30 10:00:40 +020069#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek0341c062025-02-03 10:28:15 +010070static int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc,
71 char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000072{
wdenk1ebf41e2004-01-02 14:00:00 +000073 size_t data_size = 0;
Michal Simekc1fd3122018-06-05 15:14:39 +020074 long fpga_data, dev;
75 int ret;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053076 struct fpga_secure_info fpga_sec_info;
77
78 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
wdenk4a9cbbe2002-08-27 09:48:53 +000079
Michal Simekc1fd3122018-06-05 15:14:39 +020080 if (argc < 5) {
81 debug("fpga: incorrect parameters passed\n");
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053082 return CMD_RET_USAGE;
83 }
84
Michal Simekc1fd3122018-06-05 15:14:39 +020085 if (argc == 6)
86 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
87 simple_strtoull(argv[5],
88 NULL, 16);
89 else
90 /*
91 * If 6th parameter is not passed then do_fpga_check_params
92 * will get 5 instead of expected 6 which means that function
93 * return CMD_RET_USAGE. Increase number of params +1 to pass
94 * this.
95 */
96 argc++;
Michal Simek2af67462018-05-30 11:18:38 +020097
Simon Glass3ff49ec2021-07-24 09:03:29 -060098 fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL);
99 fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL);
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530100
Michal Simekc1fd3122018-06-05 15:14:39 +0200101 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
102 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
103 debug("fpga: Use <fpga load> for NonSecure bitstream\n");
104 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000105 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000106
Michal Simekc1fd3122018-06-05 15:14:39 +0200107 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
108 !fpga_sec_info.userkey_addr) {
109 debug("fpga: User key not provided\n");
Michal Simekf4337f32018-05-30 10:04:34 +0200110 return CMD_RET_USAGE;
Stefano Babic67d7f562010-10-19 09:22:52 +0200111 }
112
Michal Simekc1fd3122018-06-05 15:14:39 +0200113 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
114 cmdtp, argc, argv);
115 if (ret)
116 return ret;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200117
Michal Simekc1fd3122018-06-05 15:14:39 +0200118 return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info);
wdenk4a9cbbe2002-08-27 09:48:53 +0000119}
Michal Simekc1fd3122018-06-05 15:14:39 +0200120#endif
Michal Simeke2846782018-06-04 15:51:16 +0200121
122#if defined(CONFIG_CMD_FPGA_LOADFS)
Simon Glassed38aef2020-05-10 11:40:03 -0600123static int do_fpga_loadfs(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simeke2846782018-06-04 15:51:16 +0200124 char *const argv[])
125{
126 size_t data_size = 0;
127 long fpga_data, dev;
128 int ret;
129 fpga_fs_info fpga_fsinfo;
130
131 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
132 cmdtp, argc, argv);
133 if (ret)
134 return ret;
135
136 fpga_fsinfo.fstype = FS_TYPE_ANY;
Simon Glass3ff49ec2021-07-24 09:03:29 -0600137 fpga_fsinfo.blocksize = (unsigned int)hextoul(argv[3], NULL);
Michal Simeke2846782018-06-04 15:51:16 +0200138 fpga_fsinfo.interface = argv[4];
139 fpga_fsinfo.dev_part = argv[5];
140 fpga_fsinfo.filename = argv[6];
141
142 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
143}
144#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000145
Simon Glassed38aef2020-05-10 11:40:03 -0600146static int do_fpga_info(struct cmd_tbl *cmdtp, int flag, int argc,
147 char *const argv[])
Michal Simek02d95c02018-06-04 14:57:34 +0200148{
149 long dev = do_fpga_get_device(argv[0]);
150
151 return fpga_info(dev);
152}
153
Simon Glassed38aef2020-05-10 11:40:03 -0600154static int do_fpga_dump(struct cmd_tbl *cmdtp, int flag, int argc,
155 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200156{
157 size_t data_size = 0;
158 long fpga_data, dev;
159 int ret;
160
161 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
162 cmdtp, argc, argv);
163 if (ret)
164 return ret;
165
166 return fpga_dump(dev, (void *)fpga_data, data_size);
167}
168
Simon Glassed38aef2020-05-10 11:40:03 -0600169static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc,
170 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200171{
172 size_t data_size = 0;
173 long fpga_data, dev;
174 int ret;
175
176 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
177 cmdtp, argc, argv);
178 if (ret)
179 return ret;
180
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300181 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL, 0);
Michal Simek6f6be6f2018-06-04 15:51:23 +0200182}
183
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000184#if defined(CONFIG_CMD_FPGA_LOADB)
Simon Glassed38aef2020-05-10 11:40:03 -0600185static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc,
186 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200187{
188 size_t data_size = 0;
189 long fpga_data, dev;
190 int ret;
191
192 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
193 cmdtp, argc, argv);
194 if (ret)
195 return ret;
196
197 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
198}
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000199#endif
Michal Simek6f6be6f2018-06-04 15:51:23 +0200200#if defined(CONFIG_CMD_FPGA_LOADP)
Simon Glassed38aef2020-05-10 11:40:03 -0600201static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc,
202 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200203{
204 size_t data_size = 0;
205 long fpga_data, dev;
206 int ret;
207
208 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
209 cmdtp, argc, argv);
210 if (ret)
211 return ret;
212
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300213 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL, 0);
Michal Simek6f6be6f2018-06-04 15:51:23 +0200214}
215#endif
216
217#if defined(CONFIG_CMD_FPGA_LOADBP)
Simon Glassed38aef2020-05-10 11:40:03 -0600218static int do_fpga_loadbp(struct cmd_tbl *cmdtp, int flag, int argc,
219 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200220{
221 size_t data_size = 0;
222 long fpga_data, dev;
223 int ret;
224
225 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
226 cmdtp, argc, argv);
227 if (ret)
228 return ret;
229
230 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
231 BIT_PARTIAL);
232}
233#endif
234
Michal Simek4aeae102018-06-04 16:15:58 +0200235#if defined(CONFIG_CMD_FPGA_LOADMK)
Simon Glassed38aef2020-05-10 11:40:03 -0600236static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
237 char *const argv[])
Michal Simek4aeae102018-06-04 16:15:58 +0200238{
239 size_t data_size = 0;
240 void *fpga_data = NULL;
241#if defined(CONFIG_FIT)
242 const char *fit_uname = NULL;
243 ulong fit_addr;
244#endif
245 ulong dev = do_fpga_get_device(argv[0]);
246 char *datastr = env_get("fpgadata");
247
Michal Simek19942472018-07-26 15:33:51 +0200248 debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
249
250 if (dev == FPGA_INVALID_DEVICE) {
251 debug("fpga: Invalid fpga device\n");
252 return CMD_RET_USAGE;
253 }
254
255 if (argc == 0 && !datastr) {
256 debug("fpga: No datastr passed\n");
257 return CMD_RET_USAGE;
258 }
Michal Simek4aeae102018-06-04 16:15:58 +0200259
260 if (argc == 2) {
Michal Simek19942472018-07-26 15:33:51 +0200261 datastr = argv[1];
262 debug("fpga: Full command with two args\n");
263 } else if (argc == 1 && !datastr) {
264 debug("fpga: Dev is setup - fpgadata passed\n");
265 datastr = argv[0];
266 }
267
Michal Simek4aeae102018-06-04 16:15:58 +0200268#if defined(CONFIG_FIT)
Michal Simek19942472018-07-26 15:33:51 +0200269 if (fit_parse_subimage(datastr, (ulong)fpga_data,
270 &fit_addr, &fit_uname)) {
271 fpga_data = (void *)fit_addr;
272 debug("* fpga: subimage '%s' from FIT image ",
273 fit_uname);
274 debug("at 0x%08lx\n", fit_addr);
275 } else
Michal Simek4aeae102018-06-04 16:15:58 +0200276#endif
Michal Simek19942472018-07-26 15:33:51 +0200277 {
Simon Glass3ff49ec2021-07-24 09:03:29 -0600278 fpga_data = (void *)hextoul(datastr, NULL);
Michal Simek19942472018-07-26 15:33:51 +0200279 debug("* fpga: cmdline image address = 0x%08lx\n",
280 (ulong)fpga_data);
281 }
282 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
283 if (!fpga_data) {
284 puts("Zero fpga_data address\n");
285 return CMD_RET_USAGE;
Michal Simek4aeae102018-06-04 16:15:58 +0200286 }
287
288 switch (genimg_get_format(fpga_data)) {
Tom Rinic220bd92019-05-23 07:14:07 -0400289#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
Michal Simek4aeae102018-06-04 16:15:58 +0200290 case IMAGE_FORMAT_LEGACY:
291 {
Simon Glassbb7d3bb2022-09-06 20:26:52 -0600292 struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)fpga_data;
Michal Simek4aeae102018-06-04 16:15:58 +0200293 ulong data;
294 u8 comp;
295
296 comp = image_get_comp(hdr);
297 if (comp == IH_COMP_GZIP) {
298#if defined(CONFIG_GZIP)
299 ulong image_buf = image_get_data(hdr);
300 ulong image_size = ~0UL;
301
302 data = image_get_load(hdr);
303
304 if (gunzip((void *)data, ~0UL, (void *)image_buf,
305 &image_size) != 0) {
306 puts("GUNZIP: error\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200307 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200308 }
309 data_size = image_size;
310#else
311 puts("Gunzip image is not supported\n");
312 return 1;
313#endif
314 } else {
315 data = (ulong)image_get_data(hdr);
316 data_size = image_get_data_size(hdr);
317 }
318 return fpga_load(dev, (void *)data, data_size,
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300319 BIT_FULL, 0);
Michal Simek4aeae102018-06-04 16:15:58 +0200320 }
321#endif
322#if defined(CONFIG_FIT)
323 case IMAGE_FORMAT_FIT:
324 {
325 const void *fit_hdr = (const void *)fpga_data;
Sean Andersonb89d61a2022-08-16 11:16:05 -0400326 int err;
Michal Simek4aeae102018-06-04 16:15:58 +0200327 const void *fit_data;
328
329 if (!fit_uname) {
330 puts("No FIT subimage unit name\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200331 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200332 }
333
Simon Glassd563c252021-02-15 17:08:09 -0700334 if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
Michal Simek4aeae102018-06-04 16:15:58 +0200335 puts("Bad FIT image format\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200336 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200337 }
338
Sean Andersonb89d61a2022-08-16 11:16:05 -0400339 err = fit_get_data_node(fit_hdr, fit_uname, &fit_data,
340 &data_size);
341 if (err) {
342 printf("Could not load '%s' subimage (err %d)\n",
343 fit_uname, err);
Michal Simekec2e3dc2018-06-05 16:43:38 +0200344 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200345 }
346
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300347 return fpga_load(dev, fit_data, data_size, BIT_FULL, 0);
Michal Simek4aeae102018-06-04 16:15:58 +0200348 }
349#endif
350 default:
351 puts("** Unknown image type\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200352 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200353 }
354}
355#endif
356
Simon Glassed38aef2020-05-10 11:40:03 -0600357static struct cmd_tbl fpga_commands[] = {
Michal Simek02d95c02018-06-04 14:57:34 +0200358 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek6f6be6f2018-06-04 15:51:23 +0200359 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
360 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000361#if defined(CONFIG_CMD_FPGA_LOADB)
Michal Simek6f6be6f2018-06-04 15:51:23 +0200362 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000363#endif
Michal Simek6f6be6f2018-06-04 15:51:23 +0200364#if defined(CONFIG_CMD_FPGA_LOADP)
365 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
366#endif
367#if defined(CONFIG_CMD_FPGA_LOADBP)
368 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
369#endif
Michal Simeke2846782018-06-04 15:51:16 +0200370#if defined(CONFIG_CMD_FPGA_LOADFS)
371 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
372#endif
Michal Simek4aeae102018-06-04 16:15:58 +0200373#if defined(CONFIG_CMD_FPGA_LOADMK)
374 U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""),
375#endif
Michal Simekc1fd3122018-06-05 15:14:39 +0200376#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
377 U_BOOT_CMD_MKENT(loads, 6, 1, do_fpga_loads, "", ""),
378#endif
Michal Simek9933c362018-06-04 14:55:20 +0200379};
380
Simon Glassed38aef2020-05-10 11:40:03 -0600381static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simek9933c362018-06-04 14:55:20 +0200382 char *const argv[])
383{
Simon Glassed38aef2020-05-10 11:40:03 -0600384 struct cmd_tbl *fpga_cmd;
Michal Simek9933c362018-06-04 14:55:20 +0200385 int ret;
386
387 if (argc < 2)
388 return CMD_RET_USAGE;
389
390 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
391 ARRAY_SIZE(fpga_commands));
Michal Simek9933c362018-06-04 14:55:20 +0200392 if (!fpga_cmd) {
393 debug("fpga: non existing command\n");
394 return CMD_RET_USAGE;
395 }
396
397 argc -= 2;
398 argv += 2;
399
400 if (argc > fpga_cmd->maxargs) {
401 debug("fpga: more parameters passed\n");
402 return CMD_RET_USAGE;
403 }
404
405 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
406
407 return cmd_process_error(fpga_cmd, ret);
408}
409
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530410#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9933c362018-06-04 14:55:20 +0200411U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530412#else
Michal Simek9933c362018-06-04 14:55:20 +0200413U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530414#endif
Ibai Erkiagaae279752025-01-21 13:01:30 +0000415 "loadable FPGA image support",
416 "info [dev] List known device information\n"
417 "fpga dump <dev> <address> <size> Load device to memory buffer\n"
418 "fpga load <dev> <address> <size> Load device from memory buffer\n"
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000419#if defined(CONFIG_CMD_FPGA_LOADP)
Ibai Erkiaga9b5b7392025-01-21 13:01:32 +0000420 "fpga loadb <dev> <address> <size> Load device from bitstream buffer\n"
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000421#endif
Michal Simek64c70982014-05-02 13:43:39 +0200422#if defined(CONFIG_CMD_FPGA_LOADP)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000423 "fpga loadp <dev> <address> <size> Load device from memory buffer\n"
424 " with partial bitstream\n"
Michal Simek64c70982014-05-02 13:43:39 +0200425#endif
Michal Simek64c70982014-05-02 13:43:39 +0200426#if defined(CONFIG_CMD_FPGA_LOADBP)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000427 "fpga loadbp <dev> <address> <size> Load device from bitstream buffer\n"
Ibai Erkiaga0e2bc7f2025-01-21 13:01:33 +0000428 " with partial bitstream\n"
Michal Simek64c70982014-05-02 13:43:39 +0200429#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530430#if defined(CONFIG_CMD_FPGA_LOADFS)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000431 "fpga loadfs <dev> <address> <size> <blocksize> <interface> [<dev[:part]>] <filename>\n"
Ibai Erkiaga0e2bc7f2025-01-21 13:01:33 +0000432 " Load device from filesystem (FAT by default)\n"
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530433#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530434#if defined(CONFIG_CMD_FPGA_LOADMK)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000435 "fpga loadmk <dev> <address> Load device generated with mkimage\n"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100436#if defined(CONFIG_FIT)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000437 " NOTE: loadmk operating on FIT must include subimage unit\n"
438 " name in the form of addr:<subimg_uname>\n"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100439#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530440#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530441#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Ibai Erkiagad4c0a452025-01-21 13:01:31 +0000442 "fpga loads <dev> <address> <size> <authflag> <encflag> [Userkey address]\n"
443 " Load device from memory buffer with secure bistream\n"
Ibai Erkiaga0e2bc7f2025-01-21 13:01:33 +0000444 " (authenticated/encrypted/both)\n"
Ibai Erkiagad4c0a452025-01-21 13:01:31 +0000445 " -authflag: 0 for OCM, 1 for DDR, 2 for no authentication\n"
446 " (specifies where to perform authentication)\n"
447 " -encflag: 0 for device key, 1 for user key, 2 for no encryption\n"
448 " -Userkey address: address where user key is stored\n"
449 " NOTE: secure bitstream has to be created using Xilinx bootgen tool\n"
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530450#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100451);