blob: 9fc2df699d7b659023e5196270a6f490a5eba774 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
Simon Glass1a974af2019-08-01 09:46:36 -060014#include <gzip.h>
wdenk525d7b62005-01-22 18:13:04 +000015#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000016
Michal Simek02d95c02018-06-04 14:57:34 +020017static long do_fpga_get_device(char *arg)
18{
19 long dev = FPGA_INVALID_DEVICE;
20 char *devstr = env_get("fpga");
21
22 if (devstr)
23 /* Should be strtol to handle -1 cases */
24 dev = simple_strtol(devstr, NULL, 16);
25
Michal Simek19942472018-07-26 15:33:51 +020026 if (dev == FPGA_INVALID_DEVICE && arg)
Michal Simek02d95c02018-06-04 14:57:34 +020027 dev = simple_strtol(arg, NULL, 16);
28
29 debug("%s: device = %ld\n", __func__, dev);
30
31 return dev;
32}
33
Michal Simek6f6be6f2018-06-04 15:51:23 +020034static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
35 cmd_tbl_t *cmdtp, int argc, char *const argv[])
36{
37 size_t local_data_size;
38 long local_fpga_data;
39
40 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
41
42 if (argc != cmdtp->maxargs) {
43 debug("fpga: incorrect parameters passed\n");
44 return CMD_RET_USAGE;
45 }
46
47 *dev = do_fpga_get_device(argv[0]);
48
49 local_fpga_data = simple_strtol(argv[1], NULL, 16);
50 if (!local_fpga_data) {
51 debug("fpga: zero fpga_data address\n");
52 return CMD_RET_USAGE;
53 }
54 *fpga_data = local_fpga_data;
55
56 local_data_size = simple_strtoul(argv[2], NULL, 16);
57 if (!local_data_size) {
58 debug("fpga: zero size\n");
59 return CMD_RET_USAGE;
60 }
61 *data_size = local_data_size;
62
63 return 0;
64}
65
Michal Simeka2555972018-05-30 10:00:40 +020066#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simekc1fd3122018-06-05 15:14:39 +020067int do_fpga_loads(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000068{
wdenk1ebf41e2004-01-02 14:00:00 +000069 size_t data_size = 0;
Michal Simekc1fd3122018-06-05 15:14:39 +020070 long fpga_data, dev;
71 int ret;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053072 struct fpga_secure_info fpga_sec_info;
73
74 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
wdenk4a9cbbe2002-08-27 09:48:53 +000075
Michal Simekc1fd3122018-06-05 15:14:39 +020076 if (argc < 5) {
77 debug("fpga: incorrect parameters passed\n");
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053078 return CMD_RET_USAGE;
79 }
80
Michal Simekc1fd3122018-06-05 15:14:39 +020081 if (argc == 6)
82 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
83 simple_strtoull(argv[5],
84 NULL, 16);
85 else
86 /*
87 * If 6th parameter is not passed then do_fpga_check_params
88 * will get 5 instead of expected 6 which means that function
89 * return CMD_RET_USAGE. Increase number of params +1 to pass
90 * this.
91 */
92 argc++;
Michal Simek2af67462018-05-30 11:18:38 +020093
Michal Simekc1fd3122018-06-05 15:14:39 +020094 fpga_sec_info.encflag = (u8)simple_strtoul(argv[4], NULL, 16);
95 fpga_sec_info.authflag = (u8)simple_strtoul(argv[3], NULL, 16);
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053096
Michal Simekc1fd3122018-06-05 15:14:39 +020097 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
98 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
99 debug("fpga: Use <fpga load> for NonSecure bitstream\n");
100 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000101 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000102
Michal Simekc1fd3122018-06-05 15:14:39 +0200103 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
104 !fpga_sec_info.userkey_addr) {
105 debug("fpga: User key not provided\n");
Michal Simekf4337f32018-05-30 10:04:34 +0200106 return CMD_RET_USAGE;
Stefano Babic67d7f562010-10-19 09:22:52 +0200107 }
108
Michal Simekc1fd3122018-06-05 15:14:39 +0200109 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
110 cmdtp, argc, argv);
111 if (ret)
112 return ret;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200113
Michal Simekc1fd3122018-06-05 15:14:39 +0200114 return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info);
wdenk4a9cbbe2002-08-27 09:48:53 +0000115}
Michal Simekc1fd3122018-06-05 15:14:39 +0200116#endif
Michal Simeke2846782018-06-04 15:51:16 +0200117
118#if defined(CONFIG_CMD_FPGA_LOADFS)
119static int do_fpga_loadfs(cmd_tbl_t *cmdtp, int flag, int argc,
120 char *const argv[])
121{
122 size_t data_size = 0;
123 long fpga_data, dev;
124 int ret;
125 fpga_fs_info fpga_fsinfo;
126
127 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
128 cmdtp, argc, argv);
129 if (ret)
130 return ret;
131
132 fpga_fsinfo.fstype = FS_TYPE_ANY;
133 fpga_fsinfo.blocksize = (unsigned int)simple_strtoul(argv[3], NULL, 16);
134 fpga_fsinfo.interface = argv[4];
135 fpga_fsinfo.dev_part = argv[5];
136 fpga_fsinfo.filename = argv[6];
137
138 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
139}
140#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000141
Michal Simek02d95c02018-06-04 14:57:34 +0200142static int do_fpga_info(cmd_tbl_t *cmdtp, int flag, int argc,
143 char * const argv[])
144{
145 long dev = do_fpga_get_device(argv[0]);
146
147 return fpga_info(dev);
148}
149
Michal Simek6f6be6f2018-06-04 15:51:23 +0200150static int do_fpga_dump(cmd_tbl_t *cmdtp, int flag, int argc,
151 char * const argv[])
152{
153 size_t data_size = 0;
154 long fpga_data, dev;
155 int ret;
156
157 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
158 cmdtp, argc, argv);
159 if (ret)
160 return ret;
161
162 return fpga_dump(dev, (void *)fpga_data, data_size);
163}
164
165static int do_fpga_load(cmd_tbl_t *cmdtp, int flag, int argc,
166 char * const argv[])
167{
168 size_t data_size = 0;
169 long fpga_data, dev;
170 int ret;
171
172 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
173 cmdtp, argc, argv);
174 if (ret)
175 return ret;
176
177 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL);
178}
179
180static int do_fpga_loadb(cmd_tbl_t *cmdtp, int flag, int argc,
181 char * const argv[])
182{
183 size_t data_size = 0;
184 long fpga_data, dev;
185 int ret;
186
187 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
188 cmdtp, argc, argv);
189 if (ret)
190 return ret;
191
192 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
193}
194
195#if defined(CONFIG_CMD_FPGA_LOADP)
196static int do_fpga_loadp(cmd_tbl_t *cmdtp, int flag, int argc,
197 char * const argv[])
198{
199 size_t data_size = 0;
200 long fpga_data, dev;
201 int ret;
202
203 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
204 cmdtp, argc, argv);
205 if (ret)
206 return ret;
207
208 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL);
209}
210#endif
211
212#if defined(CONFIG_CMD_FPGA_LOADBP)
213static int do_fpga_loadbp(cmd_tbl_t *cmdtp, int flag, int argc,
214 char * const argv[])
215{
216 size_t data_size = 0;
217 long fpga_data, dev;
218 int ret;
219
220 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
221 cmdtp, argc, argv);
222 if (ret)
223 return ret;
224
225 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
226 BIT_PARTIAL);
227}
228#endif
229
Michal Simek4aeae102018-06-04 16:15:58 +0200230#if defined(CONFIG_CMD_FPGA_LOADMK)
231static int do_fpga_loadmk(cmd_tbl_t *cmdtp, int flag, int argc,
232 char * const argv[])
233{
234 size_t data_size = 0;
235 void *fpga_data = NULL;
236#if defined(CONFIG_FIT)
237 const char *fit_uname = NULL;
238 ulong fit_addr;
239#endif
240 ulong dev = do_fpga_get_device(argv[0]);
241 char *datastr = env_get("fpgadata");
242
Michal Simek19942472018-07-26 15:33:51 +0200243 debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
244
245 if (dev == FPGA_INVALID_DEVICE) {
246 debug("fpga: Invalid fpga device\n");
247 return CMD_RET_USAGE;
248 }
249
250 if (argc == 0 && !datastr) {
251 debug("fpga: No datastr passed\n");
252 return CMD_RET_USAGE;
253 }
Michal Simek4aeae102018-06-04 16:15:58 +0200254
255 if (argc == 2) {
Michal Simek19942472018-07-26 15:33:51 +0200256 datastr = argv[1];
257 debug("fpga: Full command with two args\n");
258 } else if (argc == 1 && !datastr) {
259 debug("fpga: Dev is setup - fpgadata passed\n");
260 datastr = argv[0];
261 }
262
Michal Simek4aeae102018-06-04 16:15:58 +0200263#if defined(CONFIG_FIT)
Michal Simek19942472018-07-26 15:33:51 +0200264 if (fit_parse_subimage(datastr, (ulong)fpga_data,
265 &fit_addr, &fit_uname)) {
266 fpga_data = (void *)fit_addr;
267 debug("* fpga: subimage '%s' from FIT image ",
268 fit_uname);
269 debug("at 0x%08lx\n", fit_addr);
270 } else
Michal Simek4aeae102018-06-04 16:15:58 +0200271#endif
Michal Simek19942472018-07-26 15:33:51 +0200272 {
273 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
274 debug("* fpga: cmdline image address = 0x%08lx\n",
275 (ulong)fpga_data);
276 }
277 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
278 if (!fpga_data) {
279 puts("Zero fpga_data address\n");
280 return CMD_RET_USAGE;
Michal Simek4aeae102018-06-04 16:15:58 +0200281 }
282
283 switch (genimg_get_format(fpga_data)) {
Tom Rinic220bd92019-05-23 07:14:07 -0400284#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
Michal Simek4aeae102018-06-04 16:15:58 +0200285 case IMAGE_FORMAT_LEGACY:
286 {
287 image_header_t *hdr = (image_header_t *)fpga_data;
288 ulong data;
289 u8 comp;
290
291 comp = image_get_comp(hdr);
292 if (comp == IH_COMP_GZIP) {
293#if defined(CONFIG_GZIP)
294 ulong image_buf = image_get_data(hdr);
295 ulong image_size = ~0UL;
296
297 data = image_get_load(hdr);
298
299 if (gunzip((void *)data, ~0UL, (void *)image_buf,
300 &image_size) != 0) {
301 puts("GUNZIP: error\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200302 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200303 }
304 data_size = image_size;
305#else
306 puts("Gunzip image is not supported\n");
307 return 1;
308#endif
309 } else {
310 data = (ulong)image_get_data(hdr);
311 data_size = image_get_data_size(hdr);
312 }
313 return fpga_load(dev, (void *)data, data_size,
314 BIT_FULL);
315 }
316#endif
317#if defined(CONFIG_FIT)
318 case IMAGE_FORMAT_FIT:
319 {
320 const void *fit_hdr = (const void *)fpga_data;
321 int noffset;
322 const void *fit_data;
323
324 if (!fit_uname) {
325 puts("No FIT subimage unit name\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200326 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200327 }
328
329 if (!fit_check_format(fit_hdr)) {
330 puts("Bad FIT image format\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200331 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200332 }
333
334 /* get fpga component image node offset */
335 noffset = fit_image_get_node(fit_hdr, fit_uname);
336 if (noffset < 0) {
337 printf("Can't find '%s' FIT subimage\n", fit_uname);
Michal Simekec2e3dc2018-06-05 16:43:38 +0200338 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200339 }
340
341 /* verify integrity */
342 if (!fit_image_verify(fit_hdr, noffset)) {
343 puts("Bad Data Hash\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200344 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200345 }
346
Tien Fong Chee3e8ebc22019-02-12 20:41:34 +0800347 /* get fpga subimage/external data address and length */
348 if (fit_image_get_data_and_size(fit_hdr, noffset,
349 &fit_data, &data_size)) {
Michal Simek4aeae102018-06-04 16:15:58 +0200350 puts("Fpga subimage data not found\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200351 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200352 }
353
354 return fpga_load(dev, fit_data, data_size, BIT_FULL);
355 }
356#endif
357 default:
358 puts("** Unknown image type\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200359 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200360 }
361}
362#endif
363
Michal Simek9933c362018-06-04 14:55:20 +0200364static cmd_tbl_t fpga_commands[] = {
Michal Simek02d95c02018-06-04 14:57:34 +0200365 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek6f6be6f2018-06-04 15:51:23 +0200366 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
367 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
368 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
369#if defined(CONFIG_CMD_FPGA_LOADP)
370 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
371#endif
372#if defined(CONFIG_CMD_FPGA_LOADBP)
373 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
374#endif
Michal Simeke2846782018-06-04 15:51:16 +0200375#if defined(CONFIG_CMD_FPGA_LOADFS)
376 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
377#endif
Michal Simek4aeae102018-06-04 16:15:58 +0200378#if defined(CONFIG_CMD_FPGA_LOADMK)
379 U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""),
380#endif
Michal Simekc1fd3122018-06-05 15:14:39 +0200381#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
382 U_BOOT_CMD_MKENT(loads, 6, 1, do_fpga_loads, "", ""),
383#endif
Michal Simek9933c362018-06-04 14:55:20 +0200384};
385
386static int do_fpga_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
387 char *const argv[])
388{
389 cmd_tbl_t *fpga_cmd;
390 int ret;
391
392 if (argc < 2)
393 return CMD_RET_USAGE;
394
395 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
396 ARRAY_SIZE(fpga_commands));
Michal Simek9933c362018-06-04 14:55:20 +0200397 if (!fpga_cmd) {
398 debug("fpga: non existing command\n");
399 return CMD_RET_USAGE;
400 }
401
402 argc -= 2;
403 argv += 2;
404
405 if (argc > fpga_cmd->maxargs) {
406 debug("fpga: more parameters passed\n");
407 return CMD_RET_USAGE;
408 }
409
410 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
411
412 return cmd_process_error(fpga_cmd, ret);
413}
414
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530415#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9933c362018-06-04 14:55:20 +0200416U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530417#else
Michal Simek9933c362018-06-04 14:55:20 +0200418U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530419#endif
Michal Simeka888af72013-04-26 13:10:07 +0200420 "loadable FPGA image support",
421 "[operation type] [device number] [image address] [image size]\n"
422 "fpga operations:\n"
Michal Simek70da5922015-01-26 08:52:27 +0100423 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simeka888af72013-04-26 13:10:07 +0200424 " info\t[dev]\t\t\tlist known device information\n"
425 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200426#if defined(CONFIG_CMD_FPGA_LOADP)
427 " loadp\t[dev] [address] [size]\t"
428 "Load device from memory buffer with partial bitstream\n"
429#endif
Michal Simeka888af72013-04-26 13:10:07 +0200430 " loadb\t[dev] [address] [size]\t"
431 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200432#if defined(CONFIG_CMD_FPGA_LOADBP)
433 " loadbp\t[dev] [address] [size]\t"
434 "Load device from bitstream buffer with partial bitstream"
435 "(Xilinx only)\n"
436#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530437#if defined(CONFIG_CMD_FPGA_LOADFS)
438 "Load device from filesystem (FAT by default) (Xilinx only)\n"
439 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
440 " [<dev[:part]>] <filename>\n"
441#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530442#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200443 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100444#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200445 "\n"
446 "\tFor loadmk operating on FIT format uImage address must include\n"
447 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100448#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530449#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530450#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
451 "Load encrypted bitstream (Xilinx only)\n"
452 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
453 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
454 "Loads the secure bistreams(authenticated/encrypted/both\n"
455 "authenticated and encrypted) of [size] from [address].\n"
456 "The auth-OCM/DDR flag specifies to perform authentication\n"
457 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
458 "The enc flag specifies which key to be used for decryption\n"
459 "0-device key, 1-user key, 2-no encryption.\n"
460 "The optional Userkey address specifies from which address key\n"
461 "has to be used for decryption if user key is selected.\n"
Robert P. J. Dayda625142019-05-28 11:33:27 -0400462 "NOTE: the secure bitstream has to be created using Xilinx\n"
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530463 "bootgen tool only.\n"
464#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100465);