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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
wdenk525d7b62005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local defines */
Michal Simek20d6b952017-01-06 11:20:54 +010017enum {
18 FPGA_NONE = -1,
19 FPGA_INFO,
20 FPGA_LOAD,
21 FPGA_LOADB,
22 FPGA_DUMP,
23 FPGA_LOADMK,
24 FPGA_LOADP,
25 FPGA_LOADBP,
26 FPGA_LOADFS,
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053027 FPGA_LOADS,
Michal Simek20d6b952017-01-06 11:20:54 +010028};
wdenk4a9cbbe2002-08-27 09:48:53 +000029
Michal Simeka2555972018-05-30 10:00:40 +020030/*
31 * Map op to supported operations. We don't use a table since we
32 * would just have to relocate it from flash anyway.
33 */
34static int fpga_get_op(char *opstr)
35{
36 int op = FPGA_NONE;
37
38 if (!strcmp("info", opstr))
39 op = FPGA_INFO;
40 else if (!strcmp("loadb", opstr))
41 op = FPGA_LOADB;
42 else if (!strcmp("load", opstr))
43 op = FPGA_LOAD;
44#if defined(CONFIG_CMD_FPGA_LOADP)
45 else if (!strcmp("loadp", opstr))
46 op = FPGA_LOADP;
47#endif
48#if defined(CONFIG_CMD_FPGA_LOADBP)
49 else if (!strcmp("loadbp", opstr))
50 op = FPGA_LOADBP;
51#endif
52#if defined(CONFIG_CMD_FPGA_LOADFS)
53 else if (!strcmp("loadfs", opstr))
54 op = FPGA_LOADFS;
55#endif
56#if defined(CONFIG_CMD_FPGA_LOADMK)
57 else if (!strcmp("loadmk", opstr))
58 op = FPGA_LOADMK;
59#endif
60 else if (!strcmp("dump", opstr))
61 op = FPGA_DUMP;
62#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
63 else if (!strcmp("loads", opstr))
64 op = FPGA_LOADS;
65#endif
66
67 return op;
68}
69
wdenk4a9cbbe2002-08-27 09:48:53 +000070/* ------------------------------------------------------------------------- */
71/* command form:
72 * fpga <op> <device number> <data addr> <datasize>
73 * where op is 'load', 'dump', or 'info'
74 * If there is no device number field, the fpga environment variable is used.
75 * If there is no data addr field, the fpgadata environment variable is used.
76 * The info command requires no data address field.
77 */
Michal Simeka888af72013-04-26 13:10:07 +020078int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000079{
wdenk1ebf41e2004-01-02 14:00:00 +000080 int op, dev = FPGA_INVALID_DEVICE;
81 size_t data_size = 0;
82 void *fpga_data = NULL;
Simon Glass64b723f2017-08-03 12:22:12 -060083 char *devstr = env_get("fpga");
84 char *datastr = env_get("fpgadata");
wdenk1ebf41e2004-01-02 14:00:00 +000085 int rc = FPGA_FAIL;
Stefano Babic67d7f562010-10-19 09:22:52 +020086 int wrong_parms = 0;
Michal Simeka888af72013-04-26 13:10:07 +020087#if defined(CONFIG_FIT)
Marian Balakowiczd79162d2008-03-12 10:33:01 +010088 const char *fit_uname = NULL;
89 ulong fit_addr;
90#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053091#if defined(CONFIG_CMD_FPGA_LOADFS)
92 fpga_fs_info fpga_fsinfo;
93 fpga_fsinfo.fstype = FS_TYPE_ANY;
94#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053095#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
96 struct fpga_secure_info fpga_sec_info;
97
98 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
99#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000100
wdenk1ebf41e2004-01-02 14:00:00 +0000101 if (devstr)
Michal Simeka888af72013-04-26 13:10:07 +0200102 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenk1ebf41e2004-01-02 14:00:00 +0000103 if (datastr)
Michal Simeka888af72013-04-26 13:10:07 +0200104 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000105
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530106 if (argc > 9 || argc < 2) {
107 debug("%s: Too many or too few args (%d)\n", __func__, argc);
108 return CMD_RET_USAGE;
109 }
110
Michal Simeka2555972018-05-30 10:00:40 +0200111 op = fpga_get_op(argv[1]);
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530112
113 switch (op) {
Michal Simek2c660192018-05-30 09:57:42 +0200114 case FPGA_NONE:
115 printf("Unknown fpga operation \"%s\"\n", argv[1]);
116 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530117#if defined(CONFIG_CMD_FPGA_LOADFS)
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530118 case FPGA_LOADFS:
119 if (argc < 9)
120 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530121 fpga_fsinfo.blocksize = (unsigned int)
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530122 simple_strtoul(argv[5], NULL, 16);
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530123 fpga_fsinfo.interface = argv[6];
124 fpga_fsinfo.dev_part = argv[7];
125 fpga_fsinfo.filename = argv[8];
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530126 argc = 5;
127 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530128#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530129#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
130 case FPGA_LOADS:
131 if (argc < 7)
132 return CMD_RET_USAGE;
133 if (argc == 8)
134 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
135 simple_strtoull(argv[7],
136 NULL, 16);
137 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
138 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
139 argc = 5;
140 break;
141#endif
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530142 default:
143 break;
144 }
145
146 switch (argc) {
wdenk1ebf41e2004-01-02 14:00:00 +0000147 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simeka888af72013-04-26 13:10:07 +0200148 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100149
wdenk1ebf41e2004-01-02 14:00:00 +0000150 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100151#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200152 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
153 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100154 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +0200155 debug("* fpga: subimage '%s' from FIT image ",
156 fit_uname);
157 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100158 } else
159#endif
160 {
Michal Simeka888af72013-04-26 13:10:07 +0200161 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +0000162 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simeka888af72013-04-26 13:10:07 +0200163 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100164 }
Michal Simek77bb86d2016-01-05 13:51:48 +0100165 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100166
wdenk1ebf41e2004-01-02 14:00:00 +0000167 case 3: /* fpga <op> <dev | data addr> */
Michal Simeka888af72013-04-26 13:10:07 +0200168 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +0000169 debug("%s: device = %d\n", __func__, dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000170 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000171
Stefano Babic67d7f562010-10-19 09:22:52 +0200172 if (dev == FPGA_INVALID_DEVICE) {
173 puts("FPGA device not specified\n");
174 op = FPGA_NONE;
175 }
176
177 switch (op) {
178 case FPGA_NONE:
179 case FPGA_INFO:
180 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530181#if defined(CONFIG_CMD_FPGA_LOADFS)
182 case FPGA_LOADFS:
183 /* Blocksize can be zero */
184 if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
185 !fpga_fsinfo.filename)
186 wrong_parms = 1;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530187 break;
188#endif
189#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
190 case FPGA_LOADS:
191 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
192 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
193 puts("ERR: use <fpga load> for NonSecure bitstream\n");
194 wrong_parms = 1;
195 }
196
197 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
198 !fpga_sec_info.userkey_addr) {
199 wrong_parms = 1;
200 puts("ERR:User key not provided\n");
201 }
202 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530203#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200204 case FPGA_LOAD:
Michal Simek64c70982014-05-02 13:43:39 +0200205 case FPGA_LOADP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200206 case FPGA_LOADB:
Michal Simek64c70982014-05-02 13:43:39 +0200207 case FPGA_LOADBP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200208 case FPGA_DUMP:
209 if (!fpga_data || !data_size)
210 wrong_parms = 1;
211 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530212#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babic67d7f562010-10-19 09:22:52 +0200213 case FPGA_LOADMK:
214 if (!fpga_data)
215 wrong_parms = 1;
216 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530217#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200218 }
219
220 if (wrong_parms) {
221 puts("Wrong parameters for FPGA request\n");
222 op = FPGA_NONE;
223 }
224
wdenk1ebf41e2004-01-02 14:00:00 +0000225 switch (op) {
226 case FPGA_NONE:
Simon Glassa06dfc72011-12-10 08:44:01 +0000227 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000228
wdenk1ebf41e2004-01-02 14:00:00 +0000229 case FPGA_INFO:
Michal Simeka888af72013-04-26 13:10:07 +0200230 rc = fpga_info(dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000231 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000232
wdenk1ebf41e2004-01-02 14:00:00 +0000233 case FPGA_LOAD:
Michal Simek14663652014-05-02 14:09:30 +0200234 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenk1ebf41e2004-01-02 14:00:00 +0000235 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000236
Michal Simek64c70982014-05-02 13:43:39 +0200237#if defined(CONFIG_CMD_FPGA_LOADP)
238 case FPGA_LOADP:
239 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
240 break;
241#endif
242
wdenk310b4fc2005-01-09 18:12:51 +0000243 case FPGA_LOADB:
Michal Simek14663652014-05-02 14:09:30 +0200244 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk310b4fc2005-01-09 18:12:51 +0000245 break;
Michal Simek64c70982014-05-02 13:43:39 +0200246
247#if defined(CONFIG_CMD_FPGA_LOADBP)
248 case FPGA_LOADBP:
249 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
250 break;
251#endif
wdenk310b4fc2005-01-09 18:12:51 +0000252
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530253#if defined(CONFIG_CMD_FPGA_LOADFS)
254 case FPGA_LOADFS:
255 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
256 break;
257#endif
258
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530259#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
260 case FPGA_LOADS:
261 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
262 break;
263#endif
264
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530265#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200266 case FPGA_LOADMK:
Michal Simeka888af72013-04-26 13:10:07 +0200267 switch (genimg_get_format(fpga_data)) {
Heiko Schocher515eb122014-05-28 11:33:33 +0200268#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100269 case IMAGE_FORMAT_LEGACY:
270 {
Michal Simeka888af72013-04-26 13:10:07 +0200271 image_header_t *hdr =
272 (image_header_t *)fpga_data;
273 ulong data;
Michal Simekead2d422013-10-04 10:51:01 +0200274 uint8_t comp;
275
276 comp = image_get_comp(hdr);
277 if (comp == IH_COMP_GZIP) {
Michal Simekbe09b942014-07-16 10:30:50 +0200278#if defined(CONFIG_GZIP)
Michal Simekead2d422013-10-04 10:51:01 +0200279 ulong image_buf = image_get_data(hdr);
280 data = image_get_load(hdr);
281 ulong image_size = ~0UL;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200282
Michal Simekead2d422013-10-04 10:51:01 +0200283 if (gunzip((void *)data, ~0UL,
284 (void *)image_buf,
285 &image_size) != 0) {
286 puts("GUNZIP: error\n");
287 return 1;
288 }
289 data_size = image_size;
Michal Simekbe09b942014-07-16 10:30:50 +0200290#else
291 puts("Gunzip image is not supported\n");
292 return 1;
293#endif
Michal Simekead2d422013-10-04 10:51:01 +0200294 } else {
295 data = (ulong)image_get_data(hdr);
296 data_size = image_get_data_size(hdr);
297 }
Michal Simek14663652014-05-02 14:09:30 +0200298 rc = fpga_load(dev, (void *)data, data_size,
299 BIT_FULL);
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200300 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100301 break;
Heiko Schocher515eb122014-05-28 11:33:33 +0200302#endif
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100303#if defined(CONFIG_FIT)
304 case IMAGE_FORMAT_FIT:
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100305 {
306 const void *fit_hdr = (const void *)fpga_data;
307 int noffset;
Wolfgang Denk74f9b382011-07-30 13:33:49 +0000308 const void *fit_data;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100309
310 if (fit_uname == NULL) {
Michal Simeka888af72013-04-26 13:10:07 +0200311 puts("No FIT subimage unit name\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100312 return 1;
313 }
314
Michal Simeka888af72013-04-26 13:10:07 +0200315 if (!fit_check_format(fit_hdr)) {
316 puts("Bad FIT image format\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100317 return 1;
318 }
319
320 /* get fpga component image node offset */
Michal Simeka888af72013-04-26 13:10:07 +0200321 noffset = fit_image_get_node(fit_hdr,
322 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100323 if (noffset < 0) {
Michal Simeka888af72013-04-26 13:10:07 +0200324 printf("Can't find '%s' FIT subimage\n",
325 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100326 return 1;
327 }
328
329 /* verify integrity */
Simon Glass7428ad12013-05-07 06:11:57 +0000330 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100331 puts ("Bad Data Hash\n");
332 return 1;
333 }
334
335 /* get fpga subimage data address and length */
Michal Simeka888af72013-04-26 13:10:07 +0200336 if (fit_image_get_data(fit_hdr, noffset,
337 &fit_data, &data_size)) {
338 puts("Fpga subimage data not found\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100339 return 1;
340 }
341
Michal Simek14663652014-05-02 14:09:30 +0200342 rc = fpga_load(dev, fit_data, data_size,
343 BIT_FULL);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100344 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100345 break;
346#endif
347 default:
Michal Simeka888af72013-04-26 13:10:07 +0200348 puts("** Unknown image type\n");
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100349 rc = FPGA_FAIL;
350 break;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200351 }
352 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530353#endif
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200354
wdenk1ebf41e2004-01-02 14:00:00 +0000355 case FPGA_DUMP:
Michal Simeka888af72013-04-26 13:10:07 +0200356 rc = fpga_dump(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000357 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000358
wdenk1ebf41e2004-01-02 14:00:00 +0000359 default:
Michal Simeka888af72013-04-26 13:10:07 +0200360 printf("Unknown operation\n");
Simon Glassa06dfc72011-12-10 08:44:01 +0000361 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000362 }
Michal Simeka888af72013-04-26 13:10:07 +0200363 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000364}
365
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530366#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530367U_BOOT_CMD(fpga, 9, 1, do_fpga,
368#else
Michal Simeka888af72013-04-26 13:10:07 +0200369U_BOOT_CMD(fpga, 6, 1, do_fpga,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530370#endif
Michal Simeka888af72013-04-26 13:10:07 +0200371 "loadable FPGA image support",
372 "[operation type] [device number] [image address] [image size]\n"
373 "fpga operations:\n"
Michal Simek70da5922015-01-26 08:52:27 +0100374 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simeka888af72013-04-26 13:10:07 +0200375 " info\t[dev]\t\t\tlist known device information\n"
376 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200377#if defined(CONFIG_CMD_FPGA_LOADP)
378 " loadp\t[dev] [address] [size]\t"
379 "Load device from memory buffer with partial bitstream\n"
380#endif
Michal Simeka888af72013-04-26 13:10:07 +0200381 " loadb\t[dev] [address] [size]\t"
382 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200383#if defined(CONFIG_CMD_FPGA_LOADBP)
384 " loadbp\t[dev] [address] [size]\t"
385 "Load device from bitstream buffer with partial bitstream"
386 "(Xilinx only)\n"
387#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530388#if defined(CONFIG_CMD_FPGA_LOADFS)
389 "Load device from filesystem (FAT by default) (Xilinx only)\n"
390 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
391 " [<dev[:part]>] <filename>\n"
392#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530393#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200394 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100395#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200396 "\n"
397 "\tFor loadmk operating on FIT format uImage address must include\n"
398 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100399#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530400#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530401#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
402 "Load encrypted bitstream (Xilinx only)\n"
403 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
404 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
405 "Loads the secure bistreams(authenticated/encrypted/both\n"
406 "authenticated and encrypted) of [size] from [address].\n"
407 "The auth-OCM/DDR flag specifies to perform authentication\n"
408 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
409 "The enc flag specifies which key to be used for decryption\n"
410 "0-device key, 1-user key, 2-no encryption.\n"
411 "The optional Userkey address specifies from which address key\n"
412 "has to be used for decryption if user key is selected.\n"
413 "NOTE: the sceure bitstream has to be created using xilinx\n"
414 "bootgen tool only.\n"
415#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100416);