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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00006 */
7
8/*
9 * FPGA support
10 */
11#include <common.h>
12#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000013#include <fpga.h>
wdenk525d7b62005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local functions */
Michal Simeka888af72013-04-26 13:10:07 +020017static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000018
19/* Local defines */
20#define FPGA_NONE -1
21#define FPGA_INFO 0
22#define FPGA_LOAD 1
wdenk310b4fc2005-01-09 18:12:51 +000023#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000024#define FPGA_DUMP 3
Stefan Roese5f1cf2d2006-08-15 14:15:51 +020025#define FPGA_LOADMK 4
wdenk4a9cbbe2002-08-27 09:48:53 +000026
27/* ------------------------------------------------------------------------- */
28/* command form:
29 * fpga <op> <device number> <data addr> <datasize>
30 * where op is 'load', 'dump', or 'info'
31 * If there is no device number field, the fpga environment variable is used.
32 * If there is no data addr field, the fpgadata environment variable is used.
33 * The info command requires no data address field.
34 */
Michal Simeka888af72013-04-26 13:10:07 +020035int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000036{
wdenk1ebf41e2004-01-02 14:00:00 +000037 int op, dev = FPGA_INVALID_DEVICE;
38 size_t data_size = 0;
39 void *fpga_data = NULL;
Michal Simeka888af72013-04-26 13:10:07 +020040 char *devstr = getenv("fpga");
41 char *datastr = getenv("fpgadata");
wdenk1ebf41e2004-01-02 14:00:00 +000042 int rc = FPGA_FAIL;
Stefano Babic67d7f562010-10-19 09:22:52 +020043 int wrong_parms = 0;
Michal Simeka888af72013-04-26 13:10:07 +020044#if defined(CONFIG_FIT)
Marian Balakowiczd79162d2008-03-12 10:33:01 +010045 const char *fit_uname = NULL;
46 ulong fit_addr;
47#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000048
wdenk1ebf41e2004-01-02 14:00:00 +000049 if (devstr)
Michal Simeka888af72013-04-26 13:10:07 +020050 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenk1ebf41e2004-01-02 14:00:00 +000051 if (datastr)
Michal Simeka888af72013-04-26 13:10:07 +020052 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000053
wdenk1ebf41e2004-01-02 14:00:00 +000054 switch (argc) {
55 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simeka888af72013-04-26 13:10:07 +020056 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010057
wdenk1ebf41e2004-01-02 14:00:00 +000058 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczd79162d2008-03-12 10:33:01 +010059#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +020060 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
61 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +010062 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +020063 debug("* fpga: subimage '%s' from FIT image ",
64 fit_uname);
65 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010066 } else
67#endif
68 {
Michal Simeka888af72013-04-26 13:10:07 +020069 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000070 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simeka888af72013-04-26 13:10:07 +020071 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010072 }
Michal Simeka888af72013-04-26 13:10:07 +020073 debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010074
wdenk1ebf41e2004-01-02 14:00:00 +000075 case 3: /* fpga <op> <dev | data addr> */
Michal Simeka888af72013-04-26 13:10:07 +020076 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000077 debug("%s: device = %d\n", __func__, dev);
wdenk1ebf41e2004-01-02 14:00:00 +000078 /* FIXME - this is a really weak test */
Michal Simeka888af72013-04-26 13:10:07 +020079 if ((argc == 3) && (dev > fpga_count())) {
80 /* must be buffer ptr */
Stefano Babicb69b9a52011-12-28 06:47:01 +000081 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simeka888af72013-04-26 13:10:07 +020082 __func__);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010083
84#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +020085 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
86 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +010087 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +020088 debug("* fpga: subimage '%s' from FIT image ",
89 fit_uname);
90 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010091 } else
92#endif
93 {
Michal Simeka888af72013-04-26 13:10:07 +020094 fpga_data = (void *)dev;
95 debug("* fpga: cmdline image addr = 0x%08lx\n",
96 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010097 }
98
Stefano Babicb69b9a52011-12-28 06:47:01 +000099 debug("%s: fpga_data = 0x%x\n",
Michal Simeka888af72013-04-26 13:10:07 +0200100 __func__, (uint)fpga_data);
wdenk1ebf41e2004-01-02 14:00:00 +0000101 dev = FPGA_INVALID_DEVICE; /* reset device num */
102 }
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100103
wdenk1ebf41e2004-01-02 14:00:00 +0000104 case 2: /* fpga <op> */
Michal Simeka888af72013-04-26 13:10:07 +0200105 op = (int)fpga_get_op(argv[1]);
wdenk1ebf41e2004-01-02 14:00:00 +0000106 break;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100107
wdenk1ebf41e2004-01-02 14:00:00 +0000108 default:
Michal Simeka888af72013-04-26 13:10:07 +0200109 debug("%s: Too many or too few args (%d)\n", __func__, argc);
wdenk1ebf41e2004-01-02 14:00:00 +0000110 op = FPGA_NONE; /* force usage display */
111 break;
112 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000113
Stefano Babic67d7f562010-10-19 09:22:52 +0200114 if (dev == FPGA_INVALID_DEVICE) {
115 puts("FPGA device not specified\n");
116 op = FPGA_NONE;
117 }
118
119 switch (op) {
120 case FPGA_NONE:
121 case FPGA_INFO:
122 break;
123 case FPGA_LOAD:
124 case FPGA_LOADB:
125 case FPGA_DUMP:
126 if (!fpga_data || !data_size)
127 wrong_parms = 1;
128 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530129#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babic67d7f562010-10-19 09:22:52 +0200130 case FPGA_LOADMK:
131 if (!fpga_data)
132 wrong_parms = 1;
133 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530134#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200135 }
136
137 if (wrong_parms) {
138 puts("Wrong parameters for FPGA request\n");
139 op = FPGA_NONE;
140 }
141
wdenk1ebf41e2004-01-02 14:00:00 +0000142 switch (op) {
143 case FPGA_NONE:
Simon Glassa06dfc72011-12-10 08:44:01 +0000144 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000145
wdenk1ebf41e2004-01-02 14:00:00 +0000146 case FPGA_INFO:
Michal Simeka888af72013-04-26 13:10:07 +0200147 rc = fpga_info(dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000148 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000149
wdenk1ebf41e2004-01-02 14:00:00 +0000150 case FPGA_LOAD:
Michal Simeka888af72013-04-26 13:10:07 +0200151 rc = fpga_load(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000152 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000153
wdenk310b4fc2005-01-09 18:12:51 +0000154 case FPGA_LOADB:
155 rc = fpga_loadbitstream(dev, fpga_data, data_size);
156 break;
157
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530158#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200159 case FPGA_LOADMK:
Michal Simeka888af72013-04-26 13:10:07 +0200160 switch (genimg_get_format(fpga_data)) {
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100161 case IMAGE_FORMAT_LEGACY:
162 {
Michal Simeka888af72013-04-26 13:10:07 +0200163 image_header_t *hdr =
164 (image_header_t *)fpga_data;
165 ulong data;
Michal Simekead2d422013-10-04 10:51:01 +0200166 uint8_t comp;
167
168 comp = image_get_comp(hdr);
169 if (comp == IH_COMP_GZIP) {
170 ulong image_buf = image_get_data(hdr);
171 data = image_get_load(hdr);
172 ulong image_size = ~0UL;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200173
Michal Simekead2d422013-10-04 10:51:01 +0200174 if (gunzip((void *)data, ~0UL,
175 (void *)image_buf,
176 &image_size) != 0) {
177 puts("GUNZIP: error\n");
178 return 1;
179 }
180 data_size = image_size;
181 } else {
182 data = (ulong)image_get_data(hdr);
183 data_size = image_get_data_size(hdr);
184 }
Michal Simeka888af72013-04-26 13:10:07 +0200185 rc = fpga_load(dev, (void *)data, data_size);
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200186 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100187 break;
188#if defined(CONFIG_FIT)
189 case IMAGE_FORMAT_FIT:
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100190 {
191 const void *fit_hdr = (const void *)fpga_data;
192 int noffset;
Wolfgang Denk74f9b382011-07-30 13:33:49 +0000193 const void *fit_data;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100194
195 if (fit_uname == NULL) {
Michal Simeka888af72013-04-26 13:10:07 +0200196 puts("No FIT subimage unit name\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100197 return 1;
198 }
199
Michal Simeka888af72013-04-26 13:10:07 +0200200 if (!fit_check_format(fit_hdr)) {
201 puts("Bad FIT image format\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100202 return 1;
203 }
204
205 /* get fpga component image node offset */
Michal Simeka888af72013-04-26 13:10:07 +0200206 noffset = fit_image_get_node(fit_hdr,
207 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100208 if (noffset < 0) {
Michal Simeka888af72013-04-26 13:10:07 +0200209 printf("Can't find '%s' FIT subimage\n",
210 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100211 return 1;
212 }
213
214 /* verify integrity */
Simon Glass7428ad12013-05-07 06:11:57 +0000215 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100216 puts ("Bad Data Hash\n");
217 return 1;
218 }
219
220 /* get fpga subimage data address and length */
Michal Simeka888af72013-04-26 13:10:07 +0200221 if (fit_image_get_data(fit_hdr, noffset,
222 &fit_data, &data_size)) {
223 puts("Fpga subimage data not found\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100224 return 1;
225 }
226
Michal Simeka888af72013-04-26 13:10:07 +0200227 rc = fpga_load(dev, fit_data, data_size);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100228 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100229 break;
230#endif
231 default:
Michal Simeka888af72013-04-26 13:10:07 +0200232 puts("** Unknown image type\n");
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100233 rc = FPGA_FAIL;
234 break;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200235 }
236 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530237#endif
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200238
wdenk1ebf41e2004-01-02 14:00:00 +0000239 case FPGA_DUMP:
Michal Simeka888af72013-04-26 13:10:07 +0200240 rc = fpga_dump(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000241 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000242
wdenk1ebf41e2004-01-02 14:00:00 +0000243 default:
Michal Simeka888af72013-04-26 13:10:07 +0200244 printf("Unknown operation\n");
Simon Glassa06dfc72011-12-10 08:44:01 +0000245 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000246 }
Michal Simeka888af72013-04-26 13:10:07 +0200247 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000248}
249
wdenk4a9cbbe2002-08-27 09:48:53 +0000250/*
251 * Map op to supported operations. We don't use a table since we
252 * would just have to relocate it from flash anyway.
253 */
Michal Simeka888af72013-04-26 13:10:07 +0200254static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000255{
256 int op = FPGA_NONE;
257
Michal Simeka888af72013-04-26 13:10:07 +0200258 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000259 op = FPGA_INFO;
Michal Simeka888af72013-04-26 13:10:07 +0200260 else if (!strcmp("loadb", opstr))
wdenk310b4fc2005-01-09 18:12:51 +0000261 op = FPGA_LOADB;
Michal Simeka888af72013-04-26 13:10:07 +0200262 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000263 op = FPGA_LOAD;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530264#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200265 else if (!strcmp("loadmk", opstr))
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200266 op = FPGA_LOADMK;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530267#endif
Michal Simeka888af72013-04-26 13:10:07 +0200268 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000269 op = FPGA_DUMP;
wdenk4a9cbbe2002-08-27 09:48:53 +0000270
Michal Simeka888af72013-04-26 13:10:07 +0200271 if (op == FPGA_NONE)
272 printf("Unknown fpga operation \"%s\"\n", opstr);
273
wdenk4a9cbbe2002-08-27 09:48:53 +0000274 return op;
275}
276
Michal Simeka888af72013-04-26 13:10:07 +0200277U_BOOT_CMD(fpga, 6, 1, do_fpga,
278 "loadable FPGA image support",
279 "[operation type] [device number] [image address] [image size]\n"
280 "fpga operations:\n"
281 " dump\t[dev]\t\t\tLoad device to memory buffer\n"
282 " info\t[dev]\t\t\tlist known device information\n"
283 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
284 " loadb\t[dev] [address] [size]\t"
285 "Load device from bitstream buffer (Xilinx only)\n"
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530286#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200287 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100288#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200289 "\n"
290 "\tFor loadmk operating on FIT format uImage address must include\n"
291 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100292#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530293#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100294);