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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
wdenk525d7b62005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local defines */
Michal Simek20d6b952017-01-06 11:20:54 +010017enum {
18 FPGA_NONE = -1,
19 FPGA_INFO,
20 FPGA_LOAD,
21 FPGA_LOADB,
22 FPGA_DUMP,
23 FPGA_LOADMK,
24 FPGA_LOADP,
25 FPGA_LOADBP,
26 FPGA_LOADFS,
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053027 FPGA_LOADS,
Michal Simek20d6b952017-01-06 11:20:54 +010028};
wdenk4a9cbbe2002-08-27 09:48:53 +000029
Michal Simeka2555972018-05-30 10:00:40 +020030/*
31 * Map op to supported operations. We don't use a table since we
32 * would just have to relocate it from flash anyway.
33 */
34static int fpga_get_op(char *opstr)
35{
36 int op = FPGA_NONE;
37
38 if (!strcmp("info", opstr))
39 op = FPGA_INFO;
40 else if (!strcmp("loadb", opstr))
41 op = FPGA_LOADB;
42 else if (!strcmp("load", opstr))
43 op = FPGA_LOAD;
44#if defined(CONFIG_CMD_FPGA_LOADP)
45 else if (!strcmp("loadp", opstr))
46 op = FPGA_LOADP;
47#endif
48#if defined(CONFIG_CMD_FPGA_LOADBP)
49 else if (!strcmp("loadbp", opstr))
50 op = FPGA_LOADBP;
51#endif
52#if defined(CONFIG_CMD_FPGA_LOADFS)
53 else if (!strcmp("loadfs", opstr))
54 op = FPGA_LOADFS;
55#endif
56#if defined(CONFIG_CMD_FPGA_LOADMK)
57 else if (!strcmp("loadmk", opstr))
58 op = FPGA_LOADMK;
59#endif
60 else if (!strcmp("dump", opstr))
61 op = FPGA_DUMP;
62#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
63 else if (!strcmp("loads", opstr))
64 op = FPGA_LOADS;
65#endif
66
67 return op;
68}
69
wdenk4a9cbbe2002-08-27 09:48:53 +000070/* ------------------------------------------------------------------------- */
71/* command form:
72 * fpga <op> <device number> <data addr> <datasize>
73 * where op is 'load', 'dump', or 'info'
74 * If there is no device number field, the fpga environment variable is used.
75 * If there is no data addr field, the fpgadata environment variable is used.
76 * The info command requires no data address field.
77 */
Michal Simeka888af72013-04-26 13:10:07 +020078int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000079{
wdenk1ebf41e2004-01-02 14:00:00 +000080 int op, dev = FPGA_INVALID_DEVICE;
81 size_t data_size = 0;
82 void *fpga_data = NULL;
Simon Glass64b723f2017-08-03 12:22:12 -060083 char *devstr = env_get("fpga");
84 char *datastr = env_get("fpgadata");
wdenk1ebf41e2004-01-02 14:00:00 +000085 int rc = FPGA_FAIL;
Michal Simeka888af72013-04-26 13:10:07 +020086#if defined(CONFIG_FIT)
Marian Balakowiczd79162d2008-03-12 10:33:01 +010087 const char *fit_uname = NULL;
88 ulong fit_addr;
89#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053090#if defined(CONFIG_CMD_FPGA_LOADFS)
91 fpga_fs_info fpga_fsinfo;
92 fpga_fsinfo.fstype = FS_TYPE_ANY;
93#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053094#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
95 struct fpga_secure_info fpga_sec_info;
96
97 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
98#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000099
wdenk1ebf41e2004-01-02 14:00:00 +0000100 if (devstr)
Michal Simeka888af72013-04-26 13:10:07 +0200101 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenk1ebf41e2004-01-02 14:00:00 +0000102 if (datastr)
Michal Simeka888af72013-04-26 13:10:07 +0200103 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000104
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530105 if (argc > 9 || argc < 2) {
106 debug("%s: Too many or too few args (%d)\n", __func__, argc);
107 return CMD_RET_USAGE;
108 }
109
Michal Simeka2555972018-05-30 10:00:40 +0200110 op = fpga_get_op(argv[1]);
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530111
112 switch (op) {
Michal Simek2c660192018-05-30 09:57:42 +0200113 case FPGA_NONE:
114 printf("Unknown fpga operation \"%s\"\n", argv[1]);
115 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530116#if defined(CONFIG_CMD_FPGA_LOADFS)
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530117 case FPGA_LOADFS:
118 if (argc < 9)
119 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530120 fpga_fsinfo.blocksize = (unsigned int)
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530121 simple_strtoul(argv[5], NULL, 16);
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530122 fpga_fsinfo.interface = argv[6];
123 fpga_fsinfo.dev_part = argv[7];
124 fpga_fsinfo.filename = argv[8];
Michal Simek2af67462018-05-30 11:18:38 +0200125
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530126 argc = 5;
127 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530128#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530129#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
130 case FPGA_LOADS:
131 if (argc < 7)
132 return CMD_RET_USAGE;
133 if (argc == 8)
134 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
135 simple_strtoull(argv[7],
136 NULL, 16);
137 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
138 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
Michal Simek2af67462018-05-30 11:18:38 +0200139
140 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
141 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
142 puts("ERR: Use <fpga load> for NonSecure bitstream\n");
143 return CMD_RET_USAGE;
144 }
145
146 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
147 !fpga_sec_info.userkey_addr) {
148 puts("ERR: User key not provided\n");
149 return CMD_RET_USAGE;
150 }
151
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530152 argc = 5;
153 break;
154#endif
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530155 default:
156 break;
157 }
158
159 switch (argc) {
wdenk1ebf41e2004-01-02 14:00:00 +0000160 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simeka888af72013-04-26 13:10:07 +0200161 data_size = simple_strtoul(argv[4], NULL, 16);
Michal Simek76956a82018-05-30 11:28:57 +0200162 if (!data_size) {
163 puts("Zero data_size\n");
164 return CMD_RET_USAGE;
165 }
wdenk1ebf41e2004-01-02 14:00:00 +0000166 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100167#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200168 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
169 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100170 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +0200171 debug("* fpga: subimage '%s' from FIT image ",
172 fit_uname);
173 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100174 } else
175#endif
176 {
Michal Simeka888af72013-04-26 13:10:07 +0200177 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +0000178 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simeka888af72013-04-26 13:10:07 +0200179 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100180 }
Michal Simek77bb86d2016-01-05 13:51:48 +0100181 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Michal Simek76956a82018-05-30 11:28:57 +0200182 if (!fpga_data) {
183 puts("Zero fpga_data address\n");
184 return CMD_RET_USAGE;
185 }
wdenk1ebf41e2004-01-02 14:00:00 +0000186 case 3: /* fpga <op> <dev | data addr> */
Michal Simeka888af72013-04-26 13:10:07 +0200187 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +0000188 debug("%s: device = %d\n", __func__, dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000189 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000190
Stefano Babic67d7f562010-10-19 09:22:52 +0200191 if (dev == FPGA_INVALID_DEVICE) {
192 puts("FPGA device not specified\n");
Michal Simekf4337f32018-05-30 10:04:34 +0200193 return CMD_RET_USAGE;
Stefano Babic67d7f562010-10-19 09:22:52 +0200194 }
195
196 switch (op) {
Stefano Babic67d7f562010-10-19 09:22:52 +0200197 case FPGA_INFO:
Michal Simeka888af72013-04-26 13:10:07 +0200198 rc = fpga_info(dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000199 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000200
wdenk1ebf41e2004-01-02 14:00:00 +0000201 case FPGA_LOAD:
Michal Simek14663652014-05-02 14:09:30 +0200202 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenk1ebf41e2004-01-02 14:00:00 +0000203 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000204
Michal Simek64c70982014-05-02 13:43:39 +0200205#if defined(CONFIG_CMD_FPGA_LOADP)
206 case FPGA_LOADP:
207 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
208 break;
209#endif
210
wdenk310b4fc2005-01-09 18:12:51 +0000211 case FPGA_LOADB:
Michal Simek14663652014-05-02 14:09:30 +0200212 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk310b4fc2005-01-09 18:12:51 +0000213 break;
Michal Simek64c70982014-05-02 13:43:39 +0200214
215#if defined(CONFIG_CMD_FPGA_LOADBP)
216 case FPGA_LOADBP:
217 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
218 break;
219#endif
wdenk310b4fc2005-01-09 18:12:51 +0000220
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530221#if defined(CONFIG_CMD_FPGA_LOADFS)
222 case FPGA_LOADFS:
223 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
224 break;
225#endif
226
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530227#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
228 case FPGA_LOADS:
229 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
230 break;
231#endif
232
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530233#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200234 case FPGA_LOADMK:
Michal Simeka888af72013-04-26 13:10:07 +0200235 switch (genimg_get_format(fpga_data)) {
Heiko Schocher515eb122014-05-28 11:33:33 +0200236#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100237 case IMAGE_FORMAT_LEGACY:
238 {
Michal Simeka888af72013-04-26 13:10:07 +0200239 image_header_t *hdr =
240 (image_header_t *)fpga_data;
241 ulong data;
Michal Simekead2d422013-10-04 10:51:01 +0200242 uint8_t comp;
243
244 comp = image_get_comp(hdr);
245 if (comp == IH_COMP_GZIP) {
Michal Simekbe09b942014-07-16 10:30:50 +0200246#if defined(CONFIG_GZIP)
Michal Simekead2d422013-10-04 10:51:01 +0200247 ulong image_buf = image_get_data(hdr);
248 data = image_get_load(hdr);
249 ulong image_size = ~0UL;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200250
Michal Simekead2d422013-10-04 10:51:01 +0200251 if (gunzip((void *)data, ~0UL,
252 (void *)image_buf,
253 &image_size) != 0) {
254 puts("GUNZIP: error\n");
255 return 1;
256 }
257 data_size = image_size;
Michal Simekbe09b942014-07-16 10:30:50 +0200258#else
259 puts("Gunzip image is not supported\n");
260 return 1;
261#endif
Michal Simekead2d422013-10-04 10:51:01 +0200262 } else {
263 data = (ulong)image_get_data(hdr);
264 data_size = image_get_data_size(hdr);
265 }
Michal Simek14663652014-05-02 14:09:30 +0200266 rc = fpga_load(dev, (void *)data, data_size,
267 BIT_FULL);
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200268 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100269 break;
Heiko Schocher515eb122014-05-28 11:33:33 +0200270#endif
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100271#if defined(CONFIG_FIT)
272 case IMAGE_FORMAT_FIT:
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100273 {
274 const void *fit_hdr = (const void *)fpga_data;
275 int noffset;
Wolfgang Denk74f9b382011-07-30 13:33:49 +0000276 const void *fit_data;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100277
278 if (fit_uname == NULL) {
Michal Simeka888af72013-04-26 13:10:07 +0200279 puts("No FIT subimage unit name\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100280 return 1;
281 }
282
Michal Simeka888af72013-04-26 13:10:07 +0200283 if (!fit_check_format(fit_hdr)) {
284 puts("Bad FIT image format\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100285 return 1;
286 }
287
288 /* get fpga component image node offset */
Michal Simeka888af72013-04-26 13:10:07 +0200289 noffset = fit_image_get_node(fit_hdr,
290 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100291 if (noffset < 0) {
Michal Simeka888af72013-04-26 13:10:07 +0200292 printf("Can't find '%s' FIT subimage\n",
293 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100294 return 1;
295 }
296
297 /* verify integrity */
Simon Glass7428ad12013-05-07 06:11:57 +0000298 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100299 puts ("Bad Data Hash\n");
300 return 1;
301 }
302
303 /* get fpga subimage data address and length */
Michal Simeka888af72013-04-26 13:10:07 +0200304 if (fit_image_get_data(fit_hdr, noffset,
305 &fit_data, &data_size)) {
306 puts("Fpga subimage data not found\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100307 return 1;
308 }
309
Michal Simek14663652014-05-02 14:09:30 +0200310 rc = fpga_load(dev, fit_data, data_size,
311 BIT_FULL);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100312 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100313 break;
314#endif
315 default:
Michal Simeka888af72013-04-26 13:10:07 +0200316 puts("** Unknown image type\n");
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100317 rc = FPGA_FAIL;
318 break;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200319 }
320 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530321#endif
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200322
wdenk1ebf41e2004-01-02 14:00:00 +0000323 case FPGA_DUMP:
Michal Simeka888af72013-04-26 13:10:07 +0200324 rc = fpga_dump(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000325 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000326
wdenk1ebf41e2004-01-02 14:00:00 +0000327 default:
Michal Simeka888af72013-04-26 13:10:07 +0200328 printf("Unknown operation\n");
Simon Glassa06dfc72011-12-10 08:44:01 +0000329 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000330 }
Michal Simeka888af72013-04-26 13:10:07 +0200331 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000332}
333
Michal Simek9933c362018-06-04 14:55:20 +0200334static cmd_tbl_t fpga_commands[] = {
335};
336
337static int do_fpga_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
338 char *const argv[])
339{
340 cmd_tbl_t *fpga_cmd;
341 int ret;
342
343 if (argc < 2)
344 return CMD_RET_USAGE;
345
346 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
347 ARRAY_SIZE(fpga_commands));
348
349 /* This should be removed when all functions are converted */
350 if (!fpga_cmd)
351 return do_fpga(cmdtp, flag, argc, argv);
352
353 /* FIXME This can't be reached till all functions are converted */
354 if (!fpga_cmd) {
355 debug("fpga: non existing command\n");
356 return CMD_RET_USAGE;
357 }
358
359 argc -= 2;
360 argv += 2;
361
362 if (argc > fpga_cmd->maxargs) {
363 debug("fpga: more parameters passed\n");
364 return CMD_RET_USAGE;
365 }
366
367 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
368
369 return cmd_process_error(fpga_cmd, ret);
370}
371
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530372#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9933c362018-06-04 14:55:20 +0200373U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530374#else
Michal Simek9933c362018-06-04 14:55:20 +0200375U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530376#endif
Michal Simeka888af72013-04-26 13:10:07 +0200377 "loadable FPGA image support",
378 "[operation type] [device number] [image address] [image size]\n"
379 "fpga operations:\n"
Michal Simek70da5922015-01-26 08:52:27 +0100380 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simeka888af72013-04-26 13:10:07 +0200381 " info\t[dev]\t\t\tlist known device information\n"
382 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200383#if defined(CONFIG_CMD_FPGA_LOADP)
384 " loadp\t[dev] [address] [size]\t"
385 "Load device from memory buffer with partial bitstream\n"
386#endif
Michal Simeka888af72013-04-26 13:10:07 +0200387 " loadb\t[dev] [address] [size]\t"
388 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200389#if defined(CONFIG_CMD_FPGA_LOADBP)
390 " loadbp\t[dev] [address] [size]\t"
391 "Load device from bitstream buffer with partial bitstream"
392 "(Xilinx only)\n"
393#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530394#if defined(CONFIG_CMD_FPGA_LOADFS)
395 "Load device from filesystem (FAT by default) (Xilinx only)\n"
396 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
397 " [<dev[:part]>] <filename>\n"
398#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530399#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200400 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100401#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200402 "\n"
403 "\tFor loadmk operating on FIT format uImage address must include\n"
404 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100405#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530406#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530407#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
408 "Load encrypted bitstream (Xilinx only)\n"
409 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
410 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
411 "Loads the secure bistreams(authenticated/encrypted/both\n"
412 "authenticated and encrypted) of [size] from [address].\n"
413 "The auth-OCM/DDR flag specifies to perform authentication\n"
414 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
415 "The enc flag specifies which key to be used for decryption\n"
416 "0-device key, 1-user key, 2-no encryption.\n"
417 "The optional Userkey address specifies from which address key\n"
418 "has to be used for decryption if user key is selected.\n"
419 "NOTE: the sceure bitstream has to be created using xilinx\n"
420 "bootgen tool only.\n"
421#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100422);