Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000, 2001 |
| 4 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * FPGA support |
| 9 | */ |
| 10 | #include <common.h> |
| 11 | #include <command.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 12 | #include <env.h> |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 13 | #include <fpga.h> |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 14 | #include <fs.h> |
Simon Glass | 1a974af | 2019-08-01 09:46:36 -0600 | [diff] [blame] | 15 | #include <gzip.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 16 | #include <image.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 17 | #include <log.h> |
wdenk | 525d7b6 | 2005-01-22 18:13:04 +0000 | [diff] [blame] | 18 | #include <malloc.h> |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 19 | |
Michal Simek | 02d95c0 | 2018-06-04 14:57:34 +0200 | [diff] [blame] | 20 | static long do_fpga_get_device(char *arg) |
| 21 | { |
| 22 | long dev = FPGA_INVALID_DEVICE; |
| 23 | char *devstr = env_get("fpga"); |
| 24 | |
| 25 | if (devstr) |
| 26 | /* Should be strtol to handle -1 cases */ |
| 27 | dev = simple_strtol(devstr, NULL, 16); |
| 28 | |
Michal Simek | 1994247 | 2018-07-26 15:33:51 +0200 | [diff] [blame] | 29 | if (dev == FPGA_INVALID_DEVICE && arg) |
Michal Simek | 02d95c0 | 2018-06-04 14:57:34 +0200 | [diff] [blame] | 30 | dev = simple_strtol(arg, NULL, 16); |
| 31 | |
| 32 | debug("%s: device = %ld\n", __func__, dev); |
| 33 | |
| 34 | return dev; |
| 35 | } |
| 36 | |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 37 | static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size, |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 38 | struct cmd_tbl *cmdtp, int argc, |
| 39 | char *const argv[]) |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 40 | { |
| 41 | size_t local_data_size; |
| 42 | long local_fpga_data; |
| 43 | |
| 44 | debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs); |
| 45 | |
| 46 | if (argc != cmdtp->maxargs) { |
| 47 | debug("fpga: incorrect parameters passed\n"); |
| 48 | return CMD_RET_USAGE; |
| 49 | } |
| 50 | |
| 51 | *dev = do_fpga_get_device(argv[0]); |
| 52 | |
| 53 | local_fpga_data = simple_strtol(argv[1], NULL, 16); |
| 54 | if (!local_fpga_data) { |
| 55 | debug("fpga: zero fpga_data address\n"); |
| 56 | return CMD_RET_USAGE; |
| 57 | } |
| 58 | *fpga_data = local_fpga_data; |
| 59 | |
Simon Glass | 3ff49ec | 2021-07-24 09:03:29 -0600 | [diff] [blame^] | 60 | local_data_size = hextoul(argv[2], NULL); |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 61 | if (!local_data_size) { |
| 62 | debug("fpga: zero size\n"); |
| 63 | return CMD_RET_USAGE; |
| 64 | } |
| 65 | *data_size = local_data_size; |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
Michal Simek | a255597 | 2018-05-30 10:00:40 +0200 | [diff] [blame] | 70 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 71 | int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 72 | { |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 73 | size_t data_size = 0; |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 74 | long fpga_data, dev; |
| 75 | int ret; |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 76 | struct fpga_secure_info fpga_sec_info; |
| 77 | |
| 78 | memset(&fpga_sec_info, 0, sizeof(fpga_sec_info)); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 79 | |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 80 | if (argc < 5) { |
| 81 | debug("fpga: incorrect parameters passed\n"); |
Siva Durga Prasad Paladugu | 8f039b1 | 2018-05-31 15:10:21 +0530 | [diff] [blame] | 82 | return CMD_RET_USAGE; |
| 83 | } |
| 84 | |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 85 | if (argc == 6) |
| 86 | fpga_sec_info.userkey_addr = (u8 *)(uintptr_t) |
| 87 | simple_strtoull(argv[5], |
| 88 | NULL, 16); |
| 89 | else |
| 90 | /* |
| 91 | * If 6th parameter is not passed then do_fpga_check_params |
| 92 | * will get 5 instead of expected 6 which means that function |
| 93 | * return CMD_RET_USAGE. Increase number of params +1 to pass |
| 94 | * this. |
| 95 | */ |
| 96 | argc++; |
Michal Simek | 2af6746 | 2018-05-30 11:18:38 +0200 | [diff] [blame] | 97 | |
Simon Glass | 3ff49ec | 2021-07-24 09:03:29 -0600 | [diff] [blame^] | 98 | fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL); |
| 99 | fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL); |
Siva Durga Prasad Paladugu | 8f039b1 | 2018-05-31 15:10:21 +0530 | [diff] [blame] | 100 | |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 101 | if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH && |
| 102 | fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) { |
| 103 | debug("fpga: Use <fpga load> for NonSecure bitstream\n"); |
| 104 | return CMD_RET_USAGE; |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 105 | } |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 106 | |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 107 | if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY && |
| 108 | !fpga_sec_info.userkey_addr) { |
| 109 | debug("fpga: User key not provided\n"); |
Michal Simek | f4337f3 | 2018-05-30 10:04:34 +0200 | [diff] [blame] | 110 | return CMD_RET_USAGE; |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 111 | } |
| 112 | |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 113 | ret = do_fpga_check_params(&dev, &fpga_data, &data_size, |
| 114 | cmdtp, argc, argv); |
| 115 | if (ret) |
| 116 | return ret; |
Stefan Roese | 5f1cf2d | 2006-08-15 14:15:51 +0200 | [diff] [blame] | 117 | |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 118 | return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 119 | } |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 120 | #endif |
Michal Simek | e284678 | 2018-06-04 15:51:16 +0200 | [diff] [blame] | 121 | |
| 122 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 123 | static int do_fpga_loadfs(struct cmd_tbl *cmdtp, int flag, int argc, |
Michal Simek | e284678 | 2018-06-04 15:51:16 +0200 | [diff] [blame] | 124 | char *const argv[]) |
| 125 | { |
| 126 | size_t data_size = 0; |
| 127 | long fpga_data, dev; |
| 128 | int ret; |
| 129 | fpga_fs_info fpga_fsinfo; |
| 130 | |
| 131 | ret = do_fpga_check_params(&dev, &fpga_data, &data_size, |
| 132 | cmdtp, argc, argv); |
| 133 | if (ret) |
| 134 | return ret; |
| 135 | |
| 136 | fpga_fsinfo.fstype = FS_TYPE_ANY; |
Simon Glass | 3ff49ec | 2021-07-24 09:03:29 -0600 | [diff] [blame^] | 137 | fpga_fsinfo.blocksize = (unsigned int)hextoul(argv[3], NULL); |
Michal Simek | e284678 | 2018-06-04 15:51:16 +0200 | [diff] [blame] | 138 | fpga_fsinfo.interface = argv[4]; |
| 139 | fpga_fsinfo.dev_part = argv[5]; |
| 140 | fpga_fsinfo.filename = argv[6]; |
| 141 | |
| 142 | return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo); |
| 143 | } |
| 144 | #endif |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 145 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 146 | static int do_fpga_info(struct cmd_tbl *cmdtp, int flag, int argc, |
| 147 | char *const argv[]) |
Michal Simek | 02d95c0 | 2018-06-04 14:57:34 +0200 | [diff] [blame] | 148 | { |
| 149 | long dev = do_fpga_get_device(argv[0]); |
| 150 | |
| 151 | return fpga_info(dev); |
| 152 | } |
| 153 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 154 | static int do_fpga_dump(struct cmd_tbl *cmdtp, int flag, int argc, |
| 155 | char *const argv[]) |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 156 | { |
| 157 | size_t data_size = 0; |
| 158 | long fpga_data, dev; |
| 159 | int ret; |
| 160 | |
| 161 | ret = do_fpga_check_params(&dev, &fpga_data, &data_size, |
| 162 | cmdtp, argc, argv); |
| 163 | if (ret) |
| 164 | return ret; |
| 165 | |
| 166 | return fpga_dump(dev, (void *)fpga_data, data_size); |
| 167 | } |
| 168 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 169 | static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc, |
| 170 | char *const argv[]) |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 171 | { |
| 172 | size_t data_size = 0; |
| 173 | long fpga_data, dev; |
| 174 | int ret; |
| 175 | |
| 176 | ret = do_fpga_check_params(&dev, &fpga_data, &data_size, |
| 177 | cmdtp, argc, argv); |
| 178 | if (ret) |
| 179 | return ret; |
| 180 | |
| 181 | return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL); |
| 182 | } |
| 183 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 184 | static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc, |
| 185 | char *const argv[]) |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 186 | { |
| 187 | size_t data_size = 0; |
| 188 | long fpga_data, dev; |
| 189 | int ret; |
| 190 | |
| 191 | ret = do_fpga_check_params(&dev, &fpga_data, &data_size, |
| 192 | cmdtp, argc, argv); |
| 193 | if (ret) |
| 194 | return ret; |
| 195 | |
| 196 | return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL); |
| 197 | } |
| 198 | |
| 199 | #if defined(CONFIG_CMD_FPGA_LOADP) |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 200 | static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc, |
| 201 | char *const argv[]) |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 202 | { |
| 203 | size_t data_size = 0; |
| 204 | long fpga_data, dev; |
| 205 | int ret; |
| 206 | |
| 207 | ret = do_fpga_check_params(&dev, &fpga_data, &data_size, |
| 208 | cmdtp, argc, argv); |
| 209 | if (ret) |
| 210 | return ret; |
| 211 | |
| 212 | return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL); |
| 213 | } |
| 214 | #endif |
| 215 | |
| 216 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 217 | static int do_fpga_loadbp(struct cmd_tbl *cmdtp, int flag, int argc, |
| 218 | char *const argv[]) |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 219 | { |
| 220 | size_t data_size = 0; |
| 221 | long fpga_data, dev; |
| 222 | int ret; |
| 223 | |
| 224 | ret = do_fpga_check_params(&dev, &fpga_data, &data_size, |
| 225 | cmdtp, argc, argv); |
| 226 | if (ret) |
| 227 | return ret; |
| 228 | |
| 229 | return fpga_loadbitstream(dev, (void *)fpga_data, data_size, |
| 230 | BIT_PARTIAL); |
| 231 | } |
| 232 | #endif |
| 233 | |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 234 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 235 | static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, |
| 236 | char *const argv[]) |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 237 | { |
| 238 | size_t data_size = 0; |
| 239 | void *fpga_data = NULL; |
| 240 | #if defined(CONFIG_FIT) |
| 241 | const char *fit_uname = NULL; |
| 242 | ulong fit_addr; |
| 243 | #endif |
| 244 | ulong dev = do_fpga_get_device(argv[0]); |
| 245 | char *datastr = env_get("fpgadata"); |
| 246 | |
Michal Simek | 1994247 | 2018-07-26 15:33:51 +0200 | [diff] [blame] | 247 | debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr); |
| 248 | |
| 249 | if (dev == FPGA_INVALID_DEVICE) { |
| 250 | debug("fpga: Invalid fpga device\n"); |
| 251 | return CMD_RET_USAGE; |
| 252 | } |
| 253 | |
| 254 | if (argc == 0 && !datastr) { |
| 255 | debug("fpga: No datastr passed\n"); |
| 256 | return CMD_RET_USAGE; |
| 257 | } |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 258 | |
| 259 | if (argc == 2) { |
Michal Simek | 1994247 | 2018-07-26 15:33:51 +0200 | [diff] [blame] | 260 | datastr = argv[1]; |
| 261 | debug("fpga: Full command with two args\n"); |
| 262 | } else if (argc == 1 && !datastr) { |
| 263 | debug("fpga: Dev is setup - fpgadata passed\n"); |
| 264 | datastr = argv[0]; |
| 265 | } |
| 266 | |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 267 | #if defined(CONFIG_FIT) |
Michal Simek | 1994247 | 2018-07-26 15:33:51 +0200 | [diff] [blame] | 268 | if (fit_parse_subimage(datastr, (ulong)fpga_data, |
| 269 | &fit_addr, &fit_uname)) { |
| 270 | fpga_data = (void *)fit_addr; |
| 271 | debug("* fpga: subimage '%s' from FIT image ", |
| 272 | fit_uname); |
| 273 | debug("at 0x%08lx\n", fit_addr); |
| 274 | } else |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 275 | #endif |
Michal Simek | 1994247 | 2018-07-26 15:33:51 +0200 | [diff] [blame] | 276 | { |
Simon Glass | 3ff49ec | 2021-07-24 09:03:29 -0600 | [diff] [blame^] | 277 | fpga_data = (void *)hextoul(datastr, NULL); |
Michal Simek | 1994247 | 2018-07-26 15:33:51 +0200 | [diff] [blame] | 278 | debug("* fpga: cmdline image address = 0x%08lx\n", |
| 279 | (ulong)fpga_data); |
| 280 | } |
| 281 | debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data); |
| 282 | if (!fpga_data) { |
| 283 | puts("Zero fpga_data address\n"); |
| 284 | return CMD_RET_USAGE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | switch (genimg_get_format(fpga_data)) { |
Tom Rini | c220bd9 | 2019-05-23 07:14:07 -0400 | [diff] [blame] | 288 | #if defined(CONFIG_LEGACY_IMAGE_FORMAT) |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 289 | case IMAGE_FORMAT_LEGACY: |
| 290 | { |
| 291 | image_header_t *hdr = (image_header_t *)fpga_data; |
| 292 | ulong data; |
| 293 | u8 comp; |
| 294 | |
| 295 | comp = image_get_comp(hdr); |
| 296 | if (comp == IH_COMP_GZIP) { |
| 297 | #if defined(CONFIG_GZIP) |
| 298 | ulong image_buf = image_get_data(hdr); |
| 299 | ulong image_size = ~0UL; |
| 300 | |
| 301 | data = image_get_load(hdr); |
| 302 | |
| 303 | if (gunzip((void *)data, ~0UL, (void *)image_buf, |
| 304 | &image_size) != 0) { |
| 305 | puts("GUNZIP: error\n"); |
Michal Simek | ec2e3dc | 2018-06-05 16:43:38 +0200 | [diff] [blame] | 306 | return CMD_RET_FAILURE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 307 | } |
| 308 | data_size = image_size; |
| 309 | #else |
| 310 | puts("Gunzip image is not supported\n"); |
| 311 | return 1; |
| 312 | #endif |
| 313 | } else { |
| 314 | data = (ulong)image_get_data(hdr); |
| 315 | data_size = image_get_data_size(hdr); |
| 316 | } |
| 317 | return fpga_load(dev, (void *)data, data_size, |
| 318 | BIT_FULL); |
| 319 | } |
| 320 | #endif |
| 321 | #if defined(CONFIG_FIT) |
| 322 | case IMAGE_FORMAT_FIT: |
| 323 | { |
| 324 | const void *fit_hdr = (const void *)fpga_data; |
| 325 | int noffset; |
| 326 | const void *fit_data; |
| 327 | |
| 328 | if (!fit_uname) { |
| 329 | puts("No FIT subimage unit name\n"); |
Michal Simek | ec2e3dc | 2018-06-05 16:43:38 +0200 | [diff] [blame] | 330 | return CMD_RET_FAILURE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 331 | } |
| 332 | |
Simon Glass | d563c25 | 2021-02-15 17:08:09 -0700 | [diff] [blame] | 333 | if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 334 | puts("Bad FIT image format\n"); |
Michal Simek | ec2e3dc | 2018-06-05 16:43:38 +0200 | [diff] [blame] | 335 | return CMD_RET_FAILURE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 336 | } |
| 337 | |
| 338 | /* get fpga component image node offset */ |
| 339 | noffset = fit_image_get_node(fit_hdr, fit_uname); |
| 340 | if (noffset < 0) { |
| 341 | printf("Can't find '%s' FIT subimage\n", fit_uname); |
Michal Simek | ec2e3dc | 2018-06-05 16:43:38 +0200 | [diff] [blame] | 342 | return CMD_RET_FAILURE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | /* verify integrity */ |
| 346 | if (!fit_image_verify(fit_hdr, noffset)) { |
| 347 | puts("Bad Data Hash\n"); |
Michal Simek | ec2e3dc | 2018-06-05 16:43:38 +0200 | [diff] [blame] | 348 | return CMD_RET_FAILURE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 349 | } |
| 350 | |
Tien Fong Chee | 3e8ebc2 | 2019-02-12 20:41:34 +0800 | [diff] [blame] | 351 | /* get fpga subimage/external data address and length */ |
| 352 | if (fit_image_get_data_and_size(fit_hdr, noffset, |
| 353 | &fit_data, &data_size)) { |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 354 | puts("Fpga subimage data not found\n"); |
Michal Simek | ec2e3dc | 2018-06-05 16:43:38 +0200 | [diff] [blame] | 355 | return CMD_RET_FAILURE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 356 | } |
| 357 | |
| 358 | return fpga_load(dev, fit_data, data_size, BIT_FULL); |
| 359 | } |
| 360 | #endif |
| 361 | default: |
| 362 | puts("** Unknown image type\n"); |
Michal Simek | ec2e3dc | 2018-06-05 16:43:38 +0200 | [diff] [blame] | 363 | return CMD_RET_FAILURE; |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 364 | } |
| 365 | } |
| 366 | #endif |
| 367 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 368 | static struct cmd_tbl fpga_commands[] = { |
Michal Simek | 02d95c0 | 2018-06-04 14:57:34 +0200 | [diff] [blame] | 369 | U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""), |
Michal Simek | 6f6be6f | 2018-06-04 15:51:23 +0200 | [diff] [blame] | 370 | U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""), |
| 371 | U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""), |
| 372 | U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""), |
| 373 | #if defined(CONFIG_CMD_FPGA_LOADP) |
| 374 | U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""), |
| 375 | #endif |
| 376 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
| 377 | U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""), |
| 378 | #endif |
Michal Simek | e284678 | 2018-06-04 15:51:16 +0200 | [diff] [blame] | 379 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
| 380 | U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""), |
| 381 | #endif |
Michal Simek | 4aeae10 | 2018-06-04 16:15:58 +0200 | [diff] [blame] | 382 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
| 383 | U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""), |
| 384 | #endif |
Michal Simek | c1fd312 | 2018-06-05 15:14:39 +0200 | [diff] [blame] | 385 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 386 | U_BOOT_CMD_MKENT(loads, 6, 1, do_fpga_loads, "", ""), |
| 387 | #endif |
Michal Simek | 9933c36 | 2018-06-04 14:55:20 +0200 | [diff] [blame] | 388 | }; |
| 389 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 390 | static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, |
Michal Simek | 9933c36 | 2018-06-04 14:55:20 +0200 | [diff] [blame] | 391 | char *const argv[]) |
| 392 | { |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 393 | struct cmd_tbl *fpga_cmd; |
Michal Simek | 9933c36 | 2018-06-04 14:55:20 +0200 | [diff] [blame] | 394 | int ret; |
| 395 | |
| 396 | if (argc < 2) |
| 397 | return CMD_RET_USAGE; |
| 398 | |
| 399 | fpga_cmd = find_cmd_tbl(argv[1], fpga_commands, |
| 400 | ARRAY_SIZE(fpga_commands)); |
Michal Simek | 9933c36 | 2018-06-04 14:55:20 +0200 | [diff] [blame] | 401 | if (!fpga_cmd) { |
| 402 | debug("fpga: non existing command\n"); |
| 403 | return CMD_RET_USAGE; |
| 404 | } |
| 405 | |
| 406 | argc -= 2; |
| 407 | argv += 2; |
| 408 | |
| 409 | if (argc > fpga_cmd->maxargs) { |
| 410 | debug("fpga: more parameters passed\n"); |
| 411 | return CMD_RET_USAGE; |
| 412 | } |
| 413 | |
| 414 | ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv); |
| 415 | |
| 416 | return cmd_process_error(fpga_cmd, ret); |
| 417 | } |
| 418 | |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 419 | #if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
Michal Simek | 9933c36 | 2018-06-04 14:55:20 +0200 | [diff] [blame] | 420 | U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper, |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 421 | #else |
Michal Simek | 9933c36 | 2018-06-04 14:55:20 +0200 | [diff] [blame] | 422 | U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper, |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 423 | #endif |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 424 | "loadable FPGA image support", |
| 425 | "[operation type] [device number] [image address] [image size]\n" |
| 426 | "fpga operations:\n" |
Michal Simek | 70da592 | 2015-01-26 08:52:27 +0100 | [diff] [blame] | 427 | " dump\t[dev] [address] [size]\tLoad device to memory buffer\n" |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 428 | " info\t[dev]\t\t\tlist known device information\n" |
| 429 | " load\t[dev] [address] [size]\tLoad device from memory buffer\n" |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 430 | #if defined(CONFIG_CMD_FPGA_LOADP) |
| 431 | " loadp\t[dev] [address] [size]\t" |
| 432 | "Load device from memory buffer with partial bitstream\n" |
| 433 | #endif |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 434 | " loadb\t[dev] [address] [size]\t" |
| 435 | "Load device from bitstream buffer (Xilinx only)\n" |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 436 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
| 437 | " loadbp\t[dev] [address] [size]\t" |
| 438 | "Load device from bitstream buffer with partial bitstream" |
| 439 | "(Xilinx only)\n" |
| 440 | #endif |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 441 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
| 442 | "Load device from filesystem (FAT by default) (Xilinx only)\n" |
| 443 | " loadfs [dev] [address] [image size] [blocksize] <interface>\n" |
| 444 | " [<dev[:part]>] <filename>\n" |
| 445 | #endif |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 446 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 447 | " loadmk [dev] [address]\tLoad device generated with mkimage" |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 448 | #if defined(CONFIG_FIT) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 449 | "\n" |
| 450 | "\tFor loadmk operating on FIT format uImage address must include\n" |
| 451 | "\tsubimage unit name in the form of addr:<subimg_uname>" |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 452 | #endif |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 453 | #endif |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 454 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 455 | "Load encrypted bitstream (Xilinx only)\n" |
| 456 | " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n" |
| 457 | " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n" |
| 458 | "Loads the secure bistreams(authenticated/encrypted/both\n" |
| 459 | "authenticated and encrypted) of [size] from [address].\n" |
| 460 | "The auth-OCM/DDR flag specifies to perform authentication\n" |
| 461 | "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n" |
| 462 | "The enc flag specifies which key to be used for decryption\n" |
| 463 | "0-device key, 1-user key, 2-no encryption.\n" |
| 464 | "The optional Userkey address specifies from which address key\n" |
| 465 | "has to be used for decryption if user key is selected.\n" |
Robert P. J. Day | da62514 | 2019-05-28 11:33:27 -0400 | [diff] [blame] | 466 | "NOTE: the secure bitstream has to be created using Xilinx\n" |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 467 | "bootgen tool only.\n" |
| 468 | #endif |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 469 | ); |