blob: 3fdd0b35e80f3cb00328dc5aa5e269a2b54a5e7f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -060012#include <env.h>
wdenk57b2d802003-06-27 21:31:46 +000013#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053014#include <fs.h>
Simon Glass1a974af2019-08-01 09:46:36 -060015#include <gzip.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060016#include <image.h>
Simon Glass0f2af882020-05-10 11:40:05 -060017#include <log.h>
wdenk525d7b62005-01-22 18:13:04 +000018#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000019
Michal Simek02d95c02018-06-04 14:57:34 +020020static long do_fpga_get_device(char *arg)
21{
22 long dev = FPGA_INVALID_DEVICE;
23 char *devstr = env_get("fpga");
24
25 if (devstr)
26 /* Should be strtol to handle -1 cases */
27 dev = simple_strtol(devstr, NULL, 16);
28
Michal Simek19942472018-07-26 15:33:51 +020029 if (dev == FPGA_INVALID_DEVICE && arg)
Michal Simek02d95c02018-06-04 14:57:34 +020030 dev = simple_strtol(arg, NULL, 16);
31
32 debug("%s: device = %ld\n", __func__, dev);
33
34 return dev;
35}
36
Michal Simek6f6be6f2018-06-04 15:51:23 +020037static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
Simon Glassed38aef2020-05-10 11:40:03 -060038 struct cmd_tbl *cmdtp, int argc,
39 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +020040{
41 size_t local_data_size;
42 long local_fpga_data;
43
44 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
45
46 if (argc != cmdtp->maxargs) {
47 debug("fpga: incorrect parameters passed\n");
48 return CMD_RET_USAGE;
49 }
50
51 *dev = do_fpga_get_device(argv[0]);
52
53 local_fpga_data = simple_strtol(argv[1], NULL, 16);
54 if (!local_fpga_data) {
55 debug("fpga: zero fpga_data address\n");
56 return CMD_RET_USAGE;
57 }
58 *fpga_data = local_fpga_data;
59
Simon Glass3ff49ec2021-07-24 09:03:29 -060060 local_data_size = hextoul(argv[2], NULL);
Michal Simek6f6be6f2018-06-04 15:51:23 +020061 if (!local_data_size) {
62 debug("fpga: zero size\n");
63 return CMD_RET_USAGE;
64 }
65 *data_size = local_data_size;
66
67 return 0;
68}
69
Michal Simeka2555972018-05-30 10:00:40 +020070#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Simon Glassed38aef2020-05-10 11:40:03 -060071int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000072{
wdenk1ebf41e2004-01-02 14:00:00 +000073 size_t data_size = 0;
Michal Simekc1fd3122018-06-05 15:14:39 +020074 long fpga_data, dev;
75 int ret;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053076 struct fpga_secure_info fpga_sec_info;
77
78 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
wdenk4a9cbbe2002-08-27 09:48:53 +000079
Michal Simekc1fd3122018-06-05 15:14:39 +020080 if (argc < 5) {
81 debug("fpga: incorrect parameters passed\n");
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053082 return CMD_RET_USAGE;
83 }
84
Michal Simekc1fd3122018-06-05 15:14:39 +020085 if (argc == 6)
86 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
87 simple_strtoull(argv[5],
88 NULL, 16);
89 else
90 /*
91 * If 6th parameter is not passed then do_fpga_check_params
92 * will get 5 instead of expected 6 which means that function
93 * return CMD_RET_USAGE. Increase number of params +1 to pass
94 * this.
95 */
96 argc++;
Michal Simek2af67462018-05-30 11:18:38 +020097
Simon Glass3ff49ec2021-07-24 09:03:29 -060098 fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL);
99 fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL);
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530100
Michal Simekc1fd3122018-06-05 15:14:39 +0200101 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
102 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
103 debug("fpga: Use <fpga load> for NonSecure bitstream\n");
104 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000105 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000106
Michal Simekc1fd3122018-06-05 15:14:39 +0200107 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
108 !fpga_sec_info.userkey_addr) {
109 debug("fpga: User key not provided\n");
Michal Simekf4337f32018-05-30 10:04:34 +0200110 return CMD_RET_USAGE;
Stefano Babic67d7f562010-10-19 09:22:52 +0200111 }
112
Michal Simekc1fd3122018-06-05 15:14:39 +0200113 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
114 cmdtp, argc, argv);
115 if (ret)
116 return ret;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200117
Michal Simekc1fd3122018-06-05 15:14:39 +0200118 return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info);
wdenk4a9cbbe2002-08-27 09:48:53 +0000119}
Michal Simekc1fd3122018-06-05 15:14:39 +0200120#endif
Michal Simeke2846782018-06-04 15:51:16 +0200121
122#if defined(CONFIG_CMD_FPGA_LOADFS)
Simon Glassed38aef2020-05-10 11:40:03 -0600123static int do_fpga_loadfs(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simeke2846782018-06-04 15:51:16 +0200124 char *const argv[])
125{
126 size_t data_size = 0;
127 long fpga_data, dev;
128 int ret;
129 fpga_fs_info fpga_fsinfo;
130
131 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
132 cmdtp, argc, argv);
133 if (ret)
134 return ret;
135
136 fpga_fsinfo.fstype = FS_TYPE_ANY;
Simon Glass3ff49ec2021-07-24 09:03:29 -0600137 fpga_fsinfo.blocksize = (unsigned int)hextoul(argv[3], NULL);
Michal Simeke2846782018-06-04 15:51:16 +0200138 fpga_fsinfo.interface = argv[4];
139 fpga_fsinfo.dev_part = argv[5];
140 fpga_fsinfo.filename = argv[6];
141
142 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
143}
144#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000145
Simon Glassed38aef2020-05-10 11:40:03 -0600146static int do_fpga_info(struct cmd_tbl *cmdtp, int flag, int argc,
147 char *const argv[])
Michal Simek02d95c02018-06-04 14:57:34 +0200148{
149 long dev = do_fpga_get_device(argv[0]);
150
151 return fpga_info(dev);
152}
153
Simon Glassed38aef2020-05-10 11:40:03 -0600154static int do_fpga_dump(struct cmd_tbl *cmdtp, int flag, int argc,
155 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200156{
157 size_t data_size = 0;
158 long fpga_data, dev;
159 int ret;
160
161 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
162 cmdtp, argc, argv);
163 if (ret)
164 return ret;
165
166 return fpga_dump(dev, (void *)fpga_data, data_size);
167}
168
Simon Glassed38aef2020-05-10 11:40:03 -0600169static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc,
170 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200171{
172 size_t data_size = 0;
173 long fpga_data, dev;
174 int ret;
175
176 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
177 cmdtp, argc, argv);
178 if (ret)
179 return ret;
180
181 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL);
182}
183
Simon Glassed38aef2020-05-10 11:40:03 -0600184static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc,
185 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200186{
187 size_t data_size = 0;
188 long fpga_data, dev;
189 int ret;
190
191 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
192 cmdtp, argc, argv);
193 if (ret)
194 return ret;
195
196 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
197}
198
199#if defined(CONFIG_CMD_FPGA_LOADP)
Simon Glassed38aef2020-05-10 11:40:03 -0600200static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc,
201 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200202{
203 size_t data_size = 0;
204 long fpga_data, dev;
205 int ret;
206
207 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
208 cmdtp, argc, argv);
209 if (ret)
210 return ret;
211
212 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL);
213}
214#endif
215
216#if defined(CONFIG_CMD_FPGA_LOADBP)
Simon Glassed38aef2020-05-10 11:40:03 -0600217static int do_fpga_loadbp(struct cmd_tbl *cmdtp, int flag, int argc,
218 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200219{
220 size_t data_size = 0;
221 long fpga_data, dev;
222 int ret;
223
224 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
225 cmdtp, argc, argv);
226 if (ret)
227 return ret;
228
229 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
230 BIT_PARTIAL);
231}
232#endif
233
Michal Simek4aeae102018-06-04 16:15:58 +0200234#if defined(CONFIG_CMD_FPGA_LOADMK)
Simon Glassed38aef2020-05-10 11:40:03 -0600235static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
236 char *const argv[])
Michal Simek4aeae102018-06-04 16:15:58 +0200237{
238 size_t data_size = 0;
239 void *fpga_data = NULL;
240#if defined(CONFIG_FIT)
241 const char *fit_uname = NULL;
242 ulong fit_addr;
243#endif
244 ulong dev = do_fpga_get_device(argv[0]);
245 char *datastr = env_get("fpgadata");
246
Michal Simek19942472018-07-26 15:33:51 +0200247 debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
248
249 if (dev == FPGA_INVALID_DEVICE) {
250 debug("fpga: Invalid fpga device\n");
251 return CMD_RET_USAGE;
252 }
253
254 if (argc == 0 && !datastr) {
255 debug("fpga: No datastr passed\n");
256 return CMD_RET_USAGE;
257 }
Michal Simek4aeae102018-06-04 16:15:58 +0200258
259 if (argc == 2) {
Michal Simek19942472018-07-26 15:33:51 +0200260 datastr = argv[1];
261 debug("fpga: Full command with two args\n");
262 } else if (argc == 1 && !datastr) {
263 debug("fpga: Dev is setup - fpgadata passed\n");
264 datastr = argv[0];
265 }
266
Michal Simek4aeae102018-06-04 16:15:58 +0200267#if defined(CONFIG_FIT)
Michal Simek19942472018-07-26 15:33:51 +0200268 if (fit_parse_subimage(datastr, (ulong)fpga_data,
269 &fit_addr, &fit_uname)) {
270 fpga_data = (void *)fit_addr;
271 debug("* fpga: subimage '%s' from FIT image ",
272 fit_uname);
273 debug("at 0x%08lx\n", fit_addr);
274 } else
Michal Simek4aeae102018-06-04 16:15:58 +0200275#endif
Michal Simek19942472018-07-26 15:33:51 +0200276 {
Simon Glass3ff49ec2021-07-24 09:03:29 -0600277 fpga_data = (void *)hextoul(datastr, NULL);
Michal Simek19942472018-07-26 15:33:51 +0200278 debug("* fpga: cmdline image address = 0x%08lx\n",
279 (ulong)fpga_data);
280 }
281 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
282 if (!fpga_data) {
283 puts("Zero fpga_data address\n");
284 return CMD_RET_USAGE;
Michal Simek4aeae102018-06-04 16:15:58 +0200285 }
286
287 switch (genimg_get_format(fpga_data)) {
Tom Rinic220bd92019-05-23 07:14:07 -0400288#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
Michal Simek4aeae102018-06-04 16:15:58 +0200289 case IMAGE_FORMAT_LEGACY:
290 {
291 image_header_t *hdr = (image_header_t *)fpga_data;
292 ulong data;
293 u8 comp;
294
295 comp = image_get_comp(hdr);
296 if (comp == IH_COMP_GZIP) {
297#if defined(CONFIG_GZIP)
298 ulong image_buf = image_get_data(hdr);
299 ulong image_size = ~0UL;
300
301 data = image_get_load(hdr);
302
303 if (gunzip((void *)data, ~0UL, (void *)image_buf,
304 &image_size) != 0) {
305 puts("GUNZIP: error\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200306 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200307 }
308 data_size = image_size;
309#else
310 puts("Gunzip image is not supported\n");
311 return 1;
312#endif
313 } else {
314 data = (ulong)image_get_data(hdr);
315 data_size = image_get_data_size(hdr);
316 }
317 return fpga_load(dev, (void *)data, data_size,
318 BIT_FULL);
319 }
320#endif
321#if defined(CONFIG_FIT)
322 case IMAGE_FORMAT_FIT:
323 {
324 const void *fit_hdr = (const void *)fpga_data;
325 int noffset;
326 const void *fit_data;
327
328 if (!fit_uname) {
329 puts("No FIT subimage unit name\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200330 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200331 }
332
Simon Glassd563c252021-02-15 17:08:09 -0700333 if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
Michal Simek4aeae102018-06-04 16:15:58 +0200334 puts("Bad FIT image format\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200335 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200336 }
337
338 /* get fpga component image node offset */
339 noffset = fit_image_get_node(fit_hdr, fit_uname);
340 if (noffset < 0) {
341 printf("Can't find '%s' FIT subimage\n", fit_uname);
Michal Simekec2e3dc2018-06-05 16:43:38 +0200342 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200343 }
344
345 /* verify integrity */
346 if (!fit_image_verify(fit_hdr, noffset)) {
347 puts("Bad Data Hash\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200348 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200349 }
350
Tien Fong Chee3e8ebc22019-02-12 20:41:34 +0800351 /* get fpga subimage/external data address and length */
352 if (fit_image_get_data_and_size(fit_hdr, noffset,
353 &fit_data, &data_size)) {
Michal Simek4aeae102018-06-04 16:15:58 +0200354 puts("Fpga subimage data not found\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200355 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200356 }
357
358 return fpga_load(dev, fit_data, data_size, BIT_FULL);
359 }
360#endif
361 default:
362 puts("** Unknown image type\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200363 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200364 }
365}
366#endif
367
Simon Glassed38aef2020-05-10 11:40:03 -0600368static struct cmd_tbl fpga_commands[] = {
Michal Simek02d95c02018-06-04 14:57:34 +0200369 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek6f6be6f2018-06-04 15:51:23 +0200370 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
371 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
372 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
373#if defined(CONFIG_CMD_FPGA_LOADP)
374 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
375#endif
376#if defined(CONFIG_CMD_FPGA_LOADBP)
377 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
378#endif
Michal Simeke2846782018-06-04 15:51:16 +0200379#if defined(CONFIG_CMD_FPGA_LOADFS)
380 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
381#endif
Michal Simek4aeae102018-06-04 16:15:58 +0200382#if defined(CONFIG_CMD_FPGA_LOADMK)
383 U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""),
384#endif
Michal Simekc1fd3122018-06-05 15:14:39 +0200385#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
386 U_BOOT_CMD_MKENT(loads, 6, 1, do_fpga_loads, "", ""),
387#endif
Michal Simek9933c362018-06-04 14:55:20 +0200388};
389
Simon Glassed38aef2020-05-10 11:40:03 -0600390static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simek9933c362018-06-04 14:55:20 +0200391 char *const argv[])
392{
Simon Glassed38aef2020-05-10 11:40:03 -0600393 struct cmd_tbl *fpga_cmd;
Michal Simek9933c362018-06-04 14:55:20 +0200394 int ret;
395
396 if (argc < 2)
397 return CMD_RET_USAGE;
398
399 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
400 ARRAY_SIZE(fpga_commands));
Michal Simek9933c362018-06-04 14:55:20 +0200401 if (!fpga_cmd) {
402 debug("fpga: non existing command\n");
403 return CMD_RET_USAGE;
404 }
405
406 argc -= 2;
407 argv += 2;
408
409 if (argc > fpga_cmd->maxargs) {
410 debug("fpga: more parameters passed\n");
411 return CMD_RET_USAGE;
412 }
413
414 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
415
416 return cmd_process_error(fpga_cmd, ret);
417}
418
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530419#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9933c362018-06-04 14:55:20 +0200420U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530421#else
Michal Simek9933c362018-06-04 14:55:20 +0200422U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530423#endif
Michal Simeka888af72013-04-26 13:10:07 +0200424 "loadable FPGA image support",
425 "[operation type] [device number] [image address] [image size]\n"
426 "fpga operations:\n"
Michal Simek70da5922015-01-26 08:52:27 +0100427 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simeka888af72013-04-26 13:10:07 +0200428 " info\t[dev]\t\t\tlist known device information\n"
429 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200430#if defined(CONFIG_CMD_FPGA_LOADP)
431 " loadp\t[dev] [address] [size]\t"
432 "Load device from memory buffer with partial bitstream\n"
433#endif
Michal Simeka888af72013-04-26 13:10:07 +0200434 " loadb\t[dev] [address] [size]\t"
435 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200436#if defined(CONFIG_CMD_FPGA_LOADBP)
437 " loadbp\t[dev] [address] [size]\t"
438 "Load device from bitstream buffer with partial bitstream"
439 "(Xilinx only)\n"
440#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530441#if defined(CONFIG_CMD_FPGA_LOADFS)
442 "Load device from filesystem (FAT by default) (Xilinx only)\n"
443 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
444 " [<dev[:part]>] <filename>\n"
445#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530446#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200447 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100448#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200449 "\n"
450 "\tFor loadmk operating on FIT format uImage address must include\n"
451 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100452#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530453#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530454#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
455 "Load encrypted bitstream (Xilinx only)\n"
456 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
457 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
458 "Loads the secure bistreams(authenticated/encrypted/both\n"
459 "authenticated and encrypted) of [size] from [address].\n"
460 "The auth-OCM/DDR flag specifies to perform authentication\n"
461 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
462 "The enc flag specifies which key to be used for decryption\n"
463 "0-device key, 1-user key, 2-no encryption.\n"
464 "The optional Userkey address specifies from which address key\n"
465 "has to be used for decryption if user key is selected.\n"
Robert P. J. Dayda625142019-05-28 11:33:27 -0400466 "NOTE: the secure bitstream has to be created using Xilinx\n"
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530467 "bootgen tool only.\n"
468#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100469);