blob: 212f421739fa9807daa10488f3ad3b6bfc2f4025 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
wdenk4a9cbbe2002-08-27 09:48:53 +000010#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -060011#include <env.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
Simon Glass1a974af2019-08-01 09:46:36 -060014#include <gzip.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060015#include <image.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
wdenk525d7b62005-01-22 18:13:04 +000017#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000018
Michal Simek02d95c02018-06-04 14:57:34 +020019static long do_fpga_get_device(char *arg)
20{
21 long dev = FPGA_INVALID_DEVICE;
22 char *devstr = env_get("fpga");
23
24 if (devstr)
25 /* Should be strtol to handle -1 cases */
26 dev = simple_strtol(devstr, NULL, 16);
27
Michal Simek19942472018-07-26 15:33:51 +020028 if (dev == FPGA_INVALID_DEVICE && arg)
Michal Simek02d95c02018-06-04 14:57:34 +020029 dev = simple_strtol(arg, NULL, 16);
30
31 debug("%s: device = %ld\n", __func__, dev);
32
33 return dev;
34}
35
Michal Simek6f6be6f2018-06-04 15:51:23 +020036static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
Simon Glassed38aef2020-05-10 11:40:03 -060037 struct cmd_tbl *cmdtp, int argc,
38 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +020039{
40 size_t local_data_size;
41 long local_fpga_data;
42
43 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
44
45 if (argc != cmdtp->maxargs) {
46 debug("fpga: incorrect parameters passed\n");
47 return CMD_RET_USAGE;
48 }
49
50 *dev = do_fpga_get_device(argv[0]);
51
52 local_fpga_data = simple_strtol(argv[1], NULL, 16);
53 if (!local_fpga_data) {
54 debug("fpga: zero fpga_data address\n");
55 return CMD_RET_USAGE;
56 }
57 *fpga_data = local_fpga_data;
58
Simon Glass3ff49ec2021-07-24 09:03:29 -060059 local_data_size = hextoul(argv[2], NULL);
Michal Simek6f6be6f2018-06-04 15:51:23 +020060 if (!local_data_size) {
61 debug("fpga: zero size\n");
62 return CMD_RET_USAGE;
63 }
64 *data_size = local_data_size;
65
66 return 0;
67}
68
Michal Simeka2555972018-05-30 10:00:40 +020069#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Simon Glassed38aef2020-05-10 11:40:03 -060070int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000071{
wdenk1ebf41e2004-01-02 14:00:00 +000072 size_t data_size = 0;
Michal Simekc1fd3122018-06-05 15:14:39 +020073 long fpga_data, dev;
74 int ret;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053075 struct fpga_secure_info fpga_sec_info;
76
77 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
wdenk4a9cbbe2002-08-27 09:48:53 +000078
Michal Simekc1fd3122018-06-05 15:14:39 +020079 if (argc < 5) {
80 debug("fpga: incorrect parameters passed\n");
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053081 return CMD_RET_USAGE;
82 }
83
Michal Simekc1fd3122018-06-05 15:14:39 +020084 if (argc == 6)
85 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
86 simple_strtoull(argv[5],
87 NULL, 16);
88 else
89 /*
90 * If 6th parameter is not passed then do_fpga_check_params
91 * will get 5 instead of expected 6 which means that function
92 * return CMD_RET_USAGE. Increase number of params +1 to pass
93 * this.
94 */
95 argc++;
Michal Simek2af67462018-05-30 11:18:38 +020096
Simon Glass3ff49ec2021-07-24 09:03:29 -060097 fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL);
98 fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL);
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053099
Michal Simekc1fd3122018-06-05 15:14:39 +0200100 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
101 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
102 debug("fpga: Use <fpga load> for NonSecure bitstream\n");
103 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000104 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000105
Michal Simekc1fd3122018-06-05 15:14:39 +0200106 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
107 !fpga_sec_info.userkey_addr) {
108 debug("fpga: User key not provided\n");
Michal Simekf4337f32018-05-30 10:04:34 +0200109 return CMD_RET_USAGE;
Stefano Babic67d7f562010-10-19 09:22:52 +0200110 }
111
Michal Simekc1fd3122018-06-05 15:14:39 +0200112 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
113 cmdtp, argc, argv);
114 if (ret)
115 return ret;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200116
Michal Simekc1fd3122018-06-05 15:14:39 +0200117 return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info);
wdenk4a9cbbe2002-08-27 09:48:53 +0000118}
Michal Simekc1fd3122018-06-05 15:14:39 +0200119#endif
Michal Simeke2846782018-06-04 15:51:16 +0200120
121#if defined(CONFIG_CMD_FPGA_LOADFS)
Simon Glassed38aef2020-05-10 11:40:03 -0600122static int do_fpga_loadfs(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simeke2846782018-06-04 15:51:16 +0200123 char *const argv[])
124{
125 size_t data_size = 0;
126 long fpga_data, dev;
127 int ret;
128 fpga_fs_info fpga_fsinfo;
129
130 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
131 cmdtp, argc, argv);
132 if (ret)
133 return ret;
134
135 fpga_fsinfo.fstype = FS_TYPE_ANY;
Simon Glass3ff49ec2021-07-24 09:03:29 -0600136 fpga_fsinfo.blocksize = (unsigned int)hextoul(argv[3], NULL);
Michal Simeke2846782018-06-04 15:51:16 +0200137 fpga_fsinfo.interface = argv[4];
138 fpga_fsinfo.dev_part = argv[5];
139 fpga_fsinfo.filename = argv[6];
140
141 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
142}
143#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000144
Simon Glassed38aef2020-05-10 11:40:03 -0600145static int do_fpga_info(struct cmd_tbl *cmdtp, int flag, int argc,
146 char *const argv[])
Michal Simek02d95c02018-06-04 14:57:34 +0200147{
148 long dev = do_fpga_get_device(argv[0]);
149
150 return fpga_info(dev);
151}
152
Simon Glassed38aef2020-05-10 11:40:03 -0600153static int do_fpga_dump(struct cmd_tbl *cmdtp, int flag, int argc,
154 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200155{
156 size_t data_size = 0;
157 long fpga_data, dev;
158 int ret;
159
160 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
161 cmdtp, argc, argv);
162 if (ret)
163 return ret;
164
165 return fpga_dump(dev, (void *)fpga_data, data_size);
166}
167
Simon Glassed38aef2020-05-10 11:40:03 -0600168static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc,
169 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200170{
171 size_t data_size = 0;
172 long fpga_data, dev;
173 int ret;
174
175 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
176 cmdtp, argc, argv);
177 if (ret)
178 return ret;
179
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300180 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL, 0);
Michal Simek6f6be6f2018-06-04 15:51:23 +0200181}
182
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000183#if defined(CONFIG_CMD_FPGA_LOADB)
Simon Glassed38aef2020-05-10 11:40:03 -0600184static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc,
185 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200186{
187 size_t data_size = 0;
188 long fpga_data, dev;
189 int ret;
190
191 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
192 cmdtp, argc, argv);
193 if (ret)
194 return ret;
195
196 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
197}
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000198#endif
Michal Simek6f6be6f2018-06-04 15:51:23 +0200199#if defined(CONFIG_CMD_FPGA_LOADP)
Simon Glassed38aef2020-05-10 11:40:03 -0600200static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc,
201 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200202{
203 size_t data_size = 0;
204 long fpga_data, dev;
205 int ret;
206
207 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
208 cmdtp, argc, argv);
209 if (ret)
210 return ret;
211
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300212 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL, 0);
Michal Simek6f6be6f2018-06-04 15:51:23 +0200213}
214#endif
215
216#if defined(CONFIG_CMD_FPGA_LOADBP)
Simon Glassed38aef2020-05-10 11:40:03 -0600217static int do_fpga_loadbp(struct cmd_tbl *cmdtp, int flag, int argc,
218 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200219{
220 size_t data_size = 0;
221 long fpga_data, dev;
222 int ret;
223
224 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
225 cmdtp, argc, argv);
226 if (ret)
227 return ret;
228
229 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
230 BIT_PARTIAL);
231}
232#endif
233
Michal Simek4aeae102018-06-04 16:15:58 +0200234#if defined(CONFIG_CMD_FPGA_LOADMK)
Simon Glassed38aef2020-05-10 11:40:03 -0600235static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
236 char *const argv[])
Michal Simek4aeae102018-06-04 16:15:58 +0200237{
238 size_t data_size = 0;
239 void *fpga_data = NULL;
240#if defined(CONFIG_FIT)
241 const char *fit_uname = NULL;
242 ulong fit_addr;
243#endif
244 ulong dev = do_fpga_get_device(argv[0]);
245 char *datastr = env_get("fpgadata");
246
Michal Simek19942472018-07-26 15:33:51 +0200247 debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
248
249 if (dev == FPGA_INVALID_DEVICE) {
250 debug("fpga: Invalid fpga device\n");
251 return CMD_RET_USAGE;
252 }
253
254 if (argc == 0 && !datastr) {
255 debug("fpga: No datastr passed\n");
256 return CMD_RET_USAGE;
257 }
Michal Simek4aeae102018-06-04 16:15:58 +0200258
259 if (argc == 2) {
Michal Simek19942472018-07-26 15:33:51 +0200260 datastr = argv[1];
261 debug("fpga: Full command with two args\n");
262 } else if (argc == 1 && !datastr) {
263 debug("fpga: Dev is setup - fpgadata passed\n");
264 datastr = argv[0];
265 }
266
Michal Simek4aeae102018-06-04 16:15:58 +0200267#if defined(CONFIG_FIT)
Michal Simek19942472018-07-26 15:33:51 +0200268 if (fit_parse_subimage(datastr, (ulong)fpga_data,
269 &fit_addr, &fit_uname)) {
270 fpga_data = (void *)fit_addr;
271 debug("* fpga: subimage '%s' from FIT image ",
272 fit_uname);
273 debug("at 0x%08lx\n", fit_addr);
274 } else
Michal Simek4aeae102018-06-04 16:15:58 +0200275#endif
Michal Simek19942472018-07-26 15:33:51 +0200276 {
Simon Glass3ff49ec2021-07-24 09:03:29 -0600277 fpga_data = (void *)hextoul(datastr, NULL);
Michal Simek19942472018-07-26 15:33:51 +0200278 debug("* fpga: cmdline image address = 0x%08lx\n",
279 (ulong)fpga_data);
280 }
281 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
282 if (!fpga_data) {
283 puts("Zero fpga_data address\n");
284 return CMD_RET_USAGE;
Michal Simek4aeae102018-06-04 16:15:58 +0200285 }
286
287 switch (genimg_get_format(fpga_data)) {
Tom Rinic220bd92019-05-23 07:14:07 -0400288#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
Michal Simek4aeae102018-06-04 16:15:58 +0200289 case IMAGE_FORMAT_LEGACY:
290 {
Simon Glassbb7d3bb2022-09-06 20:26:52 -0600291 struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)fpga_data;
Michal Simek4aeae102018-06-04 16:15:58 +0200292 ulong data;
293 u8 comp;
294
295 comp = image_get_comp(hdr);
296 if (comp == IH_COMP_GZIP) {
297#if defined(CONFIG_GZIP)
298 ulong image_buf = image_get_data(hdr);
299 ulong image_size = ~0UL;
300
301 data = image_get_load(hdr);
302
303 if (gunzip((void *)data, ~0UL, (void *)image_buf,
304 &image_size) != 0) {
305 puts("GUNZIP: error\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200306 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200307 }
308 data_size = image_size;
309#else
310 puts("Gunzip image is not supported\n");
311 return 1;
312#endif
313 } else {
314 data = (ulong)image_get_data(hdr);
315 data_size = image_get_data_size(hdr);
316 }
317 return fpga_load(dev, (void *)data, data_size,
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300318 BIT_FULL, 0);
Michal Simek4aeae102018-06-04 16:15:58 +0200319 }
320#endif
321#if defined(CONFIG_FIT)
322 case IMAGE_FORMAT_FIT:
323 {
324 const void *fit_hdr = (const void *)fpga_data;
Sean Andersonb89d61a2022-08-16 11:16:05 -0400325 int err;
Michal Simek4aeae102018-06-04 16:15:58 +0200326 const void *fit_data;
327
328 if (!fit_uname) {
329 puts("No FIT subimage unit name\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200330 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200331 }
332
Simon Glassd563c252021-02-15 17:08:09 -0700333 if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
Michal Simek4aeae102018-06-04 16:15:58 +0200334 puts("Bad FIT image format\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200335 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200336 }
337
Sean Andersonb89d61a2022-08-16 11:16:05 -0400338 err = fit_get_data_node(fit_hdr, fit_uname, &fit_data,
339 &data_size);
340 if (err) {
341 printf("Could not load '%s' subimage (err %d)\n",
342 fit_uname, err);
Michal Simekec2e3dc2018-06-05 16:43:38 +0200343 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200344 }
345
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300346 return fpga_load(dev, fit_data, data_size, BIT_FULL, 0);
Michal Simek4aeae102018-06-04 16:15:58 +0200347 }
348#endif
349 default:
350 puts("** Unknown image type\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200351 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200352 }
353}
354#endif
355
Simon Glassed38aef2020-05-10 11:40:03 -0600356static struct cmd_tbl fpga_commands[] = {
Michal Simek02d95c02018-06-04 14:57:34 +0200357 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek6f6be6f2018-06-04 15:51:23 +0200358 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
359 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000360#if defined(CONFIG_CMD_FPGA_LOADB)
Michal Simek6f6be6f2018-06-04 15:51:23 +0200361 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000362#endif
Michal Simek6f6be6f2018-06-04 15:51:23 +0200363#if defined(CONFIG_CMD_FPGA_LOADP)
364 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
365#endif
366#if defined(CONFIG_CMD_FPGA_LOADBP)
367 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
368#endif
Michal Simeke2846782018-06-04 15:51:16 +0200369#if defined(CONFIG_CMD_FPGA_LOADFS)
370 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
371#endif
Michal Simek4aeae102018-06-04 16:15:58 +0200372#if defined(CONFIG_CMD_FPGA_LOADMK)
373 U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""),
374#endif
Michal Simekc1fd3122018-06-05 15:14:39 +0200375#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
376 U_BOOT_CMD_MKENT(loads, 6, 1, do_fpga_loads, "", ""),
377#endif
Michal Simek9933c362018-06-04 14:55:20 +0200378};
379
Simon Glassed38aef2020-05-10 11:40:03 -0600380static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simek9933c362018-06-04 14:55:20 +0200381 char *const argv[])
382{
Simon Glassed38aef2020-05-10 11:40:03 -0600383 struct cmd_tbl *fpga_cmd;
Michal Simek9933c362018-06-04 14:55:20 +0200384 int ret;
385
386 if (argc < 2)
387 return CMD_RET_USAGE;
388
389 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
390 ARRAY_SIZE(fpga_commands));
Michal Simek9933c362018-06-04 14:55:20 +0200391 if (!fpga_cmd) {
392 debug("fpga: non existing command\n");
393 return CMD_RET_USAGE;
394 }
395
396 argc -= 2;
397 argv += 2;
398
399 if (argc > fpga_cmd->maxargs) {
400 debug("fpga: more parameters passed\n");
401 return CMD_RET_USAGE;
402 }
403
404 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
405
406 return cmd_process_error(fpga_cmd, ret);
407}
408
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530409#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9933c362018-06-04 14:55:20 +0200410U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530411#else
Michal Simek9933c362018-06-04 14:55:20 +0200412U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530413#endif
Ibai Erkiagaae279752025-01-21 13:01:30 +0000414 "loadable FPGA image support",
415 "info [dev] List known device information\n"
416 "fpga dump <dev> <address> <size> Load device to memory buffer\n"
417 "fpga load <dev> <address> <size> Load device from memory buffer\n"
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000418#if defined(CONFIG_CMD_FPGA_LOADP)
Ibai Erkiaga9b5b7392025-01-21 13:01:32 +0000419 "fpga loadb <dev> <address> <size> Load device from bitstream buffer\n"
Ibai Erkiaga3bec0e32025-01-21 13:01:34 +0000420#endif
Michal Simek64c70982014-05-02 13:43:39 +0200421#if defined(CONFIG_CMD_FPGA_LOADP)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000422 "fpga loadp <dev> <address> <size> Load device from memory buffer\n"
423 " with partial bitstream\n"
Michal Simek64c70982014-05-02 13:43:39 +0200424#endif
Michal Simek64c70982014-05-02 13:43:39 +0200425#if defined(CONFIG_CMD_FPGA_LOADBP)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000426 "fpga loadbp <dev> <address> <size> Load device from bitstream buffer\n"
Ibai Erkiaga0e2bc7f2025-01-21 13:01:33 +0000427 " with partial bitstream\n"
Michal Simek64c70982014-05-02 13:43:39 +0200428#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530429#if defined(CONFIG_CMD_FPGA_LOADFS)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000430 "fpga loadfs <dev> <address> <size> <blocksize> <interface> [<dev[:part]>] <filename>\n"
Ibai Erkiaga0e2bc7f2025-01-21 13:01:33 +0000431 " Load device from filesystem (FAT by default)\n"
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530432#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530433#if defined(CONFIG_CMD_FPGA_LOADMK)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000434 "fpga loadmk <dev> <address> Load device generated with mkimage\n"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100435#if defined(CONFIG_FIT)
Ibai Erkiagaae279752025-01-21 13:01:30 +0000436 " NOTE: loadmk operating on FIT must include subimage unit\n"
437 " name in the form of addr:<subimg_uname>\n"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100438#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530439#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530440#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Ibai Erkiagad4c0a452025-01-21 13:01:31 +0000441 "fpga loads <dev> <address> <size> <authflag> <encflag> [Userkey address]\n"
442 " Load device from memory buffer with secure bistream\n"
Ibai Erkiaga0e2bc7f2025-01-21 13:01:33 +0000443 " (authenticated/encrypted/both)\n"
Ibai Erkiagad4c0a452025-01-21 13:01:31 +0000444 " -authflag: 0 for OCM, 1 for DDR, 2 for no authentication\n"
445 " (specifies where to perform authentication)\n"
446 " -encflag: 0 for device key, 1 for user key, 2 for no encryption\n"
447 " -Userkey address: address where user key is stored\n"
448 " NOTE: secure bitstream has to be created using Xilinx bootgen tool\n"
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530449#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100450);