blob: d4693e3c7a937b0593ea24956f3474daeb7bcc7e [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060042 mmc4 = "/mmc4";
43 mmc5 = "/mmc5";
Bin Meng408e5902018-08-03 01:14:41 -070044 pci0 = &pci0;
45 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070046 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020047 remoteproc0 = &rproc_1;
48 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060049 rtc0 = &rtc_0;
50 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060051 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020052 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070053 testbus3 = "/some-bus";
54 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070055 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070056 testfdt3 = "/b-test";
57 testfdt5 = "/some-bus/c-test@5";
58 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070059 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020060 fdt-dummy0 = "/translation-test@8000/dev@0,0";
61 fdt-dummy1 = "/translation-test@8000/dev@1,100";
62 fdt-dummy2 = "/translation-test@8000/dev@2,200";
63 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060064 usb0 = &usb_0;
65 usb1 = &usb_1;
66 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020067 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020068 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060069 };
70
Simon Glass5e135d32022-10-20 18:23:15 -060071 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020072 };
73
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 config {
Simon Glass0034d962021-08-07 07:24:01 -060075 testing-bool;
76 testing-int = <123>;
77 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020078 environment {
79 from_fdt = "yes";
80 fdt_env_path = "";
81 };
82 };
83
Simon Glassb255efc2022-04-24 23:31:24 -060084 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -070085 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -060086 compatible = "u-boot,boot-std";
87
88 filename-prefixes = "/", "/boot/";
89 bootdev-order = "mmc2", "mmc1";
90
Simon Glassb71d7f72023-05-10 16:34:46 -060091 extlinux {
92 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -060093 };
94
95 efi {
96 compatible = "u-boot,distro-efi";
97 };
Simon Glassa9289612022-10-20 18:23:14 -060098
Simon Glassd2bc33ed2023-01-06 08:52:41 -060099 theme {
100 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600101 menu-inset = <3>;
102 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600103 };
104
Simon Glass82adc292023-08-14 16:40:30 -0600105 cedit-theme {
106 font-size = <30>;
107 menu-inset = <3>;
108 menuitem-gap-y = <1>;
109 };
110
Simon Glassf1eba352022-10-20 18:23:20 -0600111 /*
112 * This is used for the VBE OS-request tests. A FAT filesystem
113 * created in a partition with the VBE information appearing
114 * before the parititon starts
115 */
Simon Glassa9289612022-10-20 18:23:14 -0600116 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700117 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600118 compatible = "fwupd,vbe-simple";
119 storage = "mmc1";
120 skip-offset = <0x200>;
121 area-start = <0x400>;
122 area-size = <0x1000>;
123 state-offset = <0x400>;
124 state-size = <0x40>;
125 version-offset = <0x800>;
126 version-size = <0x100>;
127 };
Simon Glassf1eba352022-10-20 18:23:20 -0600128
129 /*
130 * This is used for the VBE VPL tests. The MMC device holds the
131 * binman image.bin file. The test progresses through each phase
132 * of U-Boot, loading each in turn from MMC.
133 *
134 * Note that the test enables this node (and mmc3) before
135 * running U-Boot
136 */
137 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700138 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600139 status = "disabled";
140 compatible = "fwupd,vbe-simple";
141 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200142 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600143 area-start = <0>;
144 area-size = <0xe00000>;
145 state-offset = <0xdffc00>;
146 state-size = <0x40>;
147 version-offset = <0xdffe00>;
148 version-size = <0x100>;
149 };
Simon Glassb255efc2022-04-24 23:31:24 -0600150 };
151
Simon Glass61300722023-06-01 10:23:01 -0600152 cedit: cedit {
153 };
154
Andrew Scull451b8b12022-05-30 10:00:12 +0000155 fuzzing-engine {
156 compatible = "sandbox,fuzzing-engine";
157 };
158
Nandor Han6521e5d2021-06-10 16:56:44 +0300159 reboot-mode0 {
160 compatible = "reboot-mode-gpio";
161 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
162 u-boot,env-variable = "bootstatus";
163 mode-test = <0x01>;
164 mode-download = <0x03>;
165 };
166
Nandor Han7e4067a2021-06-10 16:56:45 +0300167 reboot_mode1: reboot-mode@14 {
168 compatible = "reboot-mode-rtc";
169 rtc = <&rtc_0>;
170 reg = <0x30 4>;
171 u-boot,env-variable = "bootstatus";
172 big-endian;
173 mode-test = <0x21969147>;
174 mode-download = <0x51939147>;
175 };
176
Simon Glassed96cde2018-12-10 10:37:33 -0700177 audio: audio-codec {
178 compatible = "sandbox,audio-codec";
179 #sound-dai-cells = <1>;
180 };
181
Philippe Reynes1ee26482020-07-24 18:19:51 +0200182 buttons {
183 compatible = "gpio-keys";
184
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200185 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200186 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200187 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300188 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200189 };
190
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200191 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200192 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200193 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300194 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200195 };
196 };
197
Marek Szyprowskiad398592021-02-18 11:33:18 +0100198 buttons2 {
199 compatible = "adc-keys";
200 io-channels = <&adc 3>;
201 keyup-threshold-microvolt = <3000000>;
202
203 button-up {
204 label = "button3";
205 linux,code = <KEY_F3>;
206 press-threshold-microvolt = <1500000>;
207 };
208
209 button-down {
210 label = "button4";
211 linux,code = <KEY_F4>;
212 press-threshold-microvolt = <1000000>;
213 };
214
215 button-enter {
216 label = "button5";
217 linux,code = <KEY_F5>;
218 press-threshold-microvolt = <500000>;
219 };
220 };
221
Simon Glassc953aaf2018-12-10 10:37:34 -0700222 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600223 reg = <0 0>;
224 compatible = "google,cros-ec-sandbox";
225
226 /*
227 * This describes the flash memory within the EC. Note
228 * that the STM32L flash erases to 0, not 0xff.
229 */
230 flash {
231 image-pos = <0x08000000>;
232 size = <0x20000>;
233 erase-value = <0>;
234
235 /* Information for sandbox */
236 ro {
237 image-pos = <0>;
238 size = <0xf000>;
239 };
240 wp-ro {
241 image-pos = <0xf000>;
242 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700243 used = <0x884>;
244 compress = "lz4";
245 uncomp-size = <0xcf8>;
246 hash {
247 algo = "sha256";
248 value = [00 01 02 03 04 05 06 07
249 08 09 0a 0b 0c 0d 0e 0f
250 10 11 12 13 14 15 16 17
251 18 19 1a 1b 1c 1d 1e 1f];
252 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600253 };
254 rw {
255 image-pos = <0x10000>;
256 size = <0x10000>;
257 };
258 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300259
260 cros_ec_pwm: cros-ec-pwm {
261 compatible = "google,cros-ec-pwm";
262 #pwm-cells = <1>;
263 };
264
Simon Glass699c9ca2018-10-01 12:22:08 -0600265 };
266
Yannick Fertré9712c822019-10-07 15:29:05 +0200267 dsi_host: dsi_host {
268 compatible = "sandbox,dsi-host";
269 };
270
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600272 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700273 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600274 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700275 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700276 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100277 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
278 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700279 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100280 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
281 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
282 <&gpio_b 7 GPIO_IN 3 2 1>,
283 <&gpio_b 8 GPIO_OUT 3 2 1>,
284 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100285 test3-gpios =
286 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
287 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
288 <&gpio_c 2 GPIO_OUT>,
289 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
290 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200291 <&gpio_c 5 GPIO_IN>,
292 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
293 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530294 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
295 test5-gpios = <&gpio_a 19>;
296
Simon Glass73025392021-10-23 17:26:04 -0600297 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200298 int8-value = /bits/ 8 <0x12>;
299 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700300 int-value = <1234>;
301 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200302 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200303 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200304 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600305 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700306 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600307 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200308 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530309
310 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
311 <&muxcontroller0 2>, <&muxcontroller0 3>,
312 <&muxcontroller1>;
313 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
314 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100315 display-timings {
316 timing0: 240x320 {
317 clock-frequency = <6500000>;
318 hactive = <240>;
319 vactive = <320>;
320 hfront-porch = <6>;
321 hback-porch = <7>;
322 hsync-len = <1>;
323 vback-porch = <5>;
324 vfront-porch = <8>;
325 vsync-len = <2>;
326 hsync-active = <1>;
327 vsync-active = <0>;
328 de-active = <1>;
329 pixelclk-active = <1>;
330 interlaced;
331 doublescan;
332 doubleclk;
333 };
334 timing1: 480x800 {
335 clock-frequency = <9000000>;
336 hactive = <480>;
337 vactive = <800>;
338 hfront-porch = <10>;
339 hback-porch = <59>;
340 hsync-len = <12>;
341 vback-porch = <15>;
342 vfront-porch = <17>;
343 vsync-len = <16>;
344 hsync-active = <0>;
345 vsync-active = <1>;
346 de-active = <0>;
347 pixelclk-active = <0>;
348 };
349 timing2: 800x480 {
350 clock-frequency = <33500000>;
351 hactive = <800>;
352 vactive = <480>;
353 hback-porch = <89>;
354 hfront-porch = <164>;
355 vback-porch = <23>;
356 vfront-porch = <10>;
357 hsync-len = <11>;
358 vsync-len = <13>;
359 };
360 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200361 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530362 clock-frequency = <6500000>;
363 hactive = <240>;
364 vactive = <320>;
365 hfront-porch = <6>;
366 hback-porch = <7>;
367 hsync-len = <1>;
368 vback-porch = <5>;
369 vfront-porch = <8>;
370 vsync-len = <2>;
371 hsync-active = <1>;
372 vsync-active = <0>;
373 de-active = <1>;
374 pixelclk-active = <1>;
375 interlaced;
376 doublescan;
377 doubleclk;
378 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700379 };
380
381 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600382 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700383 compatible = "not,compatible";
384 };
385
386 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600387 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700388 };
389
Simon Glass5620cf82018-10-01 12:22:40 -0600390 backlight: backlight {
391 compatible = "pwm-backlight";
392 enable-gpios = <&gpio_a 1>;
393 power-supply = <&ldo_1>;
394 pwms = <&pwm 0 1000>;
395 default-brightness-level = <5>;
396 brightness-levels = <0 16 32 64 128 170 202 234 255>;
397 };
398
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200399 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200400 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200401 bind-test-child1 {
402 compatible = "sandbox,phy";
403 #phy-cells = <1>;
404 };
405
406 bind-test-child2 {
407 compatible = "simple-bus";
408 };
409 };
410
Simon Glassb2c1cac2014-02-26 15:59:21 -0700411 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600412 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700413 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600414 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700415 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530416
417 mux-controls = <&muxcontroller0 0>;
418 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700419 };
420
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200421 phy_provider0: gen_phy@0 {
422 compatible = "sandbox,phy";
423 #phy-cells = <1>;
424 };
425
426 phy_provider1: gen_phy@1 {
427 compatible = "sandbox,phy";
428 #phy-cells = <0>;
429 broken;
430 };
431
developer71092972020-05-02 11:35:12 +0200432 phy_provider2: gen_phy@2 {
433 compatible = "sandbox,phy";
434 #phy-cells = <0>;
435 };
436
Jonas Karlman9f89e682023-08-31 22:16:35 +0000437 phy_provider3: gen_phy@3 {
438 compatible = "sandbox,phy";
439 #phy-cells = <2>;
440 };
441
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200442 gen_phy_user: gen_phy_user {
443 compatible = "simple-bus";
444 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
445 phy-names = "phy1", "phy2", "phy3";
446 };
447
developer71092972020-05-02 11:35:12 +0200448 gen_phy_user1: gen_phy_user1 {
449 compatible = "simple-bus";
450 phys = <&phy_provider0 0>, <&phy_provider2>;
451 phy-names = "phy1", "phy2";
452 };
453
Jonas Karlman9f89e682023-08-31 22:16:35 +0000454 gen_phy_user2: gen_phy_user2 {
455 compatible = "simple-bus";
456 phys = <&phy_provider3 0 0>;
457 phy-names = "phy1";
458 };
459
Simon Glassb2c1cac2014-02-26 15:59:21 -0700460 some-bus {
461 #address-cells = <1>;
462 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600463 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600464 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600465 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700466 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600467 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700468 compatible = "denx,u-boot-fdt-test";
469 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600470 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700471 ping-add = <5>;
472 };
Simon Glass40717422014-07-23 06:55:18 -0600473 c-test@0 {
474 compatible = "denx,u-boot-fdt-test";
475 reg = <0>;
476 ping-expect = <6>;
477 ping-add = <6>;
478 };
479 c-test@1 {
480 compatible = "denx,u-boot-fdt-test";
481 reg = <1>;
482 ping-expect = <7>;
483 ping-add = <7>;
484 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700485 };
486
487 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600488 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600489 ping-expect = <6>;
490 ping-add = <6>;
491 compatible = "google,another-fdt-test";
492 };
493
494 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600495 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600496 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700497 ping-add = <6>;
498 compatible = "google,another-fdt-test";
499 };
500
Simon Glass0ccb0972015-01-25 08:27:05 -0700501 f-test {
502 compatible = "denx,u-boot-fdt-test";
503 };
504
505 g-test {
506 compatible = "denx,u-boot-fdt-test";
507 };
508
Bin Mengd9d24782018-10-10 22:07:01 -0700509 h-test {
510 compatible = "denx,u-boot-fdt-test1";
511 };
512
developercf8bc132020-05-02 11:35:10 +0200513 i-test {
514 compatible = "mediatek,u-boot-fdt-test";
515 #address-cells = <1>;
516 #size-cells = <0>;
517
518 subnode@0 {
519 reg = <0>;
520 };
521
522 subnode@1 {
523 reg = <1>;
524 };
525
526 subnode@2 {
527 reg = <2>;
528 };
529 };
530
Simon Glass204675c2019-12-29 21:19:25 -0700531 devres-test {
532 compatible = "denx,u-boot-devres-test";
533 };
534
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530535 another-test {
536 reg = <0 2>;
537 compatible = "denx,u-boot-fdt-test";
538 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
539 test5-gpios = <&gpio_a 19>;
540 };
541
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100542 mmio-bus@0 {
543 #address-cells = <1>;
544 #size-cells = <1>;
545 compatible = "denx,u-boot-test-bus";
546 dma-ranges = <0x10000000 0x00000000 0x00040000>;
547
548 subnode@0 {
549 compatible = "denx,u-boot-fdt-test";
550 };
551 };
552
553 mmio-bus@1 {
554 #address-cells = <1>;
555 #size-cells = <1>;
556 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100557
558 subnode@0 {
559 compatible = "denx,u-boot-fdt-test";
560 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100561 };
562
Simon Glass3c601b12020-07-07 13:12:06 -0600563 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600564 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600565 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600566 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600567 child {
568 compatible = "denx,u-boot-acpi-test";
569 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600570 };
571
Simon Glass3c601b12020-07-07 13:12:06 -0600572 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600573 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600574 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600575 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600576 };
577
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200578 clocks {
579 clk_fixed: clk-fixed {
580 compatible = "fixed-clock";
581 #clock-cells = <0>;
582 clock-frequency = <1234>;
583 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000584
585 clk_fixed_factor: clk-fixed-factor {
586 compatible = "fixed-factor-clock";
587 #clock-cells = <0>;
588 clock-div = <3>;
589 clock-mult = <2>;
590 clocks = <&clk_fixed>;
591 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200592
593 osc {
594 compatible = "fixed-clock";
595 #clock-cells = <0>;
596 clock-frequency = <20000000>;
597 };
Stephen Warrena9622432016-06-17 09:44:00 -0600598 };
599
600 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600601 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600602 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200603 assigned-clocks = <&clk_sandbox 3>;
604 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600605 };
606
607 clk-test {
608 compatible = "sandbox,clk-test";
609 clocks = <&clk_fixed>,
610 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200611 <&clk_sandbox 0>,
612 <&clk_sandbox 3>,
613 <&clk_sandbox 2>;
614 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600615 };
616
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200617 ccf: clk-ccf {
618 compatible = "sandbox,clk-ccf";
619 };
620
Simon Glass507ab962021-12-04 08:56:31 -0700621 efi-media {
622 compatible = "sandbox,efi-media";
623 };
624
Simon Glass5b968632015-05-22 15:42:15 -0600625 eth@10002000 {
626 compatible = "sandbox,eth";
627 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600628 };
629
630 eth_5: eth@10003000 {
631 compatible = "sandbox,eth";
632 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400633 nvmem-cells = <&eth5_addr>;
634 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600635 };
636
Bin Meng04a11cb2015-08-27 22:25:53 -0700637 eth_3: sbe5 {
638 compatible = "sandbox,eth";
639 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400640 nvmem-cells = <&eth3_addr>;
641 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700642 };
643
Simon Glass5b968632015-05-22 15:42:15 -0600644 eth@10004000 {
645 compatible = "sandbox,eth";
646 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600647 };
648
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200649 phy_eth0: phy-test-eth {
650 compatible = "sandbox,eth";
651 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400652 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200653 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200654 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200655 };
656
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800657 dsa_eth0: dsa-test-eth {
658 compatible = "sandbox,eth";
659 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400660 nvmem-cells = <&eth4_addr>;
661 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800662 };
663
664 dsa-test {
665 compatible = "sandbox,dsa";
666
667 ports {
668 #address-cells = <1>;
669 #size-cells = <0>;
670 swp_0: port@0 {
671 reg = <0>;
672 label = "lan0";
673 phy-mode = "rgmii-rxid";
674
675 fixed-link {
676 speed = <100>;
677 full-duplex;
678 };
679 };
680
681 swp_1: port@1 {
682 reg = <1>;
683 label = "lan1";
684 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800685 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800686 };
687
688 port@2 {
689 reg = <2>;
690 ethernet = <&dsa_eth0>;
691
692 fixed-link {
693 speed = <1000>;
694 full-duplex;
695 };
696 };
697 };
698 };
699
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700700 firmware {
701 sandbox_firmware: sandbox-firmware {
702 compatible = "sandbox,firmware";
703 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200704
Etienne Carriere09665cb2022-02-21 09:22:39 +0100705 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200706 compatible = "sandbox,scmi-agent";
707 #address-cells = <1>;
708 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200709
Etienne Carriere09665cb2022-02-21 09:22:39 +0100710 protocol@10 {
711 reg = <0x10>;
712 };
713
714 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200715 reg = <0x14>;
716 #clock-cells = <1>;
717 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200718
Etienne Carriere09665cb2022-02-21 09:22:39 +0100719 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200720 reg = <0x16>;
721 #reset-cells = <1>;
722 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100723
724 protocol@17 {
725 reg = <0x17>;
726
727 regulators {
728 #address-cells = <1>;
729 #size-cells = <0>;
730
Etienne Carriere09665cb2022-02-21 09:22:39 +0100731 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100732 reg = <0>;
733 regulator-name = "sandbox-voltd0";
734 regulator-min-microvolt = <1100000>;
735 regulator-max-microvolt = <3300000>;
736 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100737 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100738 reg = <0x1>;
739 regulator-name = "sandbox-voltd1";
740 regulator-min-microvolt = <1800000>;
741 };
742 };
743 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200744 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700745 };
746
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200747 fpga {
748 compatible = "sandbox,fpga";
749 };
750
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100751 pinctrl-gpio {
752 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700753
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100754 gpio_a: base-gpios {
755 compatible = "sandbox,gpio";
756 gpio-controller;
757 #gpio-cells = <1>;
758 gpio-bank-name = "a";
759 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200760 hog_input_active_low {
761 gpio-hog;
762 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200763 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200764 };
765 hog_input_active_high {
766 gpio-hog;
767 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200768 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200769 };
770 hog_output_low {
771 gpio-hog;
772 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200773 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200774 };
775 hog_output_high {
776 gpio-hog;
777 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200778 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200779 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100780 };
781
782 gpio_b: extra-gpios {
783 compatible = "sandbox,gpio";
784 gpio-controller;
785 #gpio-cells = <5>;
786 gpio-bank-name = "b";
787 sandbox,gpio-count = <10>;
788 };
Simon Glass25348a42014-10-13 23:42:11 -0600789
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100790 gpio_c: pinmux-gpios {
791 compatible = "sandbox,gpio";
792 gpio-controller;
793 #gpio-cells = <2>;
794 gpio-bank-name = "c";
795 sandbox,gpio-count = <10>;
796 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100797 };
798
Simon Glass7df766e2014-12-10 08:55:55 -0700799 i2c@0 {
800 #address-cells = <1>;
801 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600802 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700803 compatible = "sandbox,i2c";
804 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200805 pinctrl-names = "default";
806 pinctrl-0 = <&pinmux_i2c0_pins>;
807
Simon Glass7df766e2014-12-10 08:55:55 -0700808 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400809 #address-cells = <1>;
810 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700811 reg = <0x2c>;
812 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700813 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200814 partitions {
815 compatible = "fixed-partitions";
816 #address-cells = <1>;
817 #size-cells = <1>;
818 bootcount_i2c: bootcount@10 {
819 reg = <10 2>;
820 };
821 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400822
823 eth3_addr: mac-address@24 {
824 reg = <24 6>;
825 };
Simon Glass7df766e2014-12-10 08:55:55 -0700826 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200827
Simon Glass336b2952015-05-22 15:42:17 -0600828 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400829 #address-cells = <1>;
830 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600831 reg = <0x43>;
832 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700833 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400834
835 eth4_addr: mac-address@40 {
836 reg = <0x40 6>;
837 };
Simon Glass336b2952015-05-22 15:42:17 -0600838 };
839
840 rtc_1: rtc@61 {
841 reg = <0x61>;
842 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700843 sandbox,emul = <&emul1>;
844 };
845
846 i2c_emul: emul {
847 reg = <0xff>;
848 compatible = "sandbox,i2c-emul-parent";
849 emul_eeprom: emul-eeprom {
850 compatible = "sandbox,i2c-eeprom";
851 sandbox,filename = "i2c.bin";
852 sandbox,size = <256>;
853 };
854 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700855 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700856 };
857 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700858 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600859 };
860 };
861
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200862 sandbox_pmic: sandbox_pmic {
863 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700864 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200865 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200866
867 mc34708: pmic@41 {
868 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700869 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200870 };
Simon Glass7df766e2014-12-10 08:55:55 -0700871 };
872
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100873 bootcount@0 {
874 compatible = "u-boot,bootcount-rtc";
875 rtc = <&rtc_1>;
876 offset = <0x13>;
877 };
878
Michal Simek4f18f922020-05-28 11:48:55 +0200879 bootcount {
880 compatible = "u-boot,bootcount-i2c-eeprom";
881 i2c-eeprom = <&bootcount_i2c>;
882 };
883
Nandor Han88895812021-06-10 15:40:38 +0300884 bootcount_4@0 {
885 compatible = "u-boot,bootcount-syscon";
886 syscon = <&syscon0>;
887 reg = <0x0 0x04>, <0x0 0x04>;
888 reg-names = "syscon_reg", "offset";
889 };
890
891 bootcount_2@0 {
892 compatible = "u-boot,bootcount-syscon";
893 syscon = <&syscon0>;
894 reg = <0x0 0x04>, <0x0 0x02> ;
895 reg-names = "syscon_reg", "offset";
896 };
897
Marek Szyprowskiad398592021-02-18 11:33:18 +0100898 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100899 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100900 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100901 vdd-supply = <&buck2>;
902 vss-microvolts = <0>;
903 };
904
Mark Kettenis67748ee2021-10-23 16:58:02 +0200905 iommu: iommu@0 {
906 compatible = "sandbox,iommu";
907 #iommu-cells = <0>;
908 };
909
Simon Glass515dcff2020-02-06 09:55:00 -0700910 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700911 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700912 interrupt-controller;
913 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700914 };
915
Simon Glass90b6fef2016-01-18 19:52:26 -0700916 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700917 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700918 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200919 pinctrl-names = "default";
920 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700921 xres = <1366>;
922 yres = <768>;
923 };
924
Simon Glassd783eb32015-07-06 12:54:34 -0600925 leds {
926 compatible = "gpio-leds";
927
928 iracibble {
929 gpios = <&gpio_a 1 0>;
930 label = "sandbox:red";
931 };
932
933 martinet {
934 gpios = <&gpio_a 2 0>;
935 label = "sandbox:green";
936 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200937
938 default_on {
939 gpios = <&gpio_a 5 0>;
940 label = "sandbox:default_on";
941 default-state = "on";
942 };
943
944 default_off {
945 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400946 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200947 default-state = "off";
948 };
Simon Glassd783eb32015-07-06 12:54:34 -0600949 };
950
Paul Doelle709f0372022-07-04 09:00:25 +0000951 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200952 gpios = <&gpio_a 7 0>;
953 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200954 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000955 hw_algo = "toggle";
956 always-running;
957 };
958
959 wdt-gpio-level {
960 gpios = <&gpio_a 7 0>;
961 compatible = "linux,wdt-gpio";
962 hw_margin_ms = <100>;
963 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200964 always-running;
965 };
966
Stephen Warren62f2c902016-05-16 17:41:37 -0600967 mbox: mbox {
968 compatible = "sandbox,mbox";
969 #mbox-cells = <1>;
970 };
971
972 mbox-test {
973 compatible = "sandbox,mbox-test";
974 mboxes = <&mbox 100>, <&mbox 1>;
975 mbox-names = "other", "test";
976 };
977
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900978 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200979 #address-cells = <1>;
980 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400981 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200982 cpu1: cpu@1 {
983 device_type = "cpu";
984 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400985 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900986 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700987 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900988 };
Mario Sixdea5df72018-08-06 10:23:44 +0200989
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200990 cpu2: cpu@2 {
991 device_type = "cpu";
992 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900993 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700994 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900995 };
Mario Sixdea5df72018-08-06 10:23:44 +0200996
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200997 cpu3: cpu@3 {
998 device_type = "cpu";
999 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001000 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001001 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001002 };
Mario Sixdea5df72018-08-06 10:23:44 +02001003 };
1004
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001005 chipid: chipid {
1006 compatible = "sandbox,soc";
1007 };
1008
Simon Glassc953aaf2018-12-10 10:37:34 -07001009 i2s: i2s {
1010 compatible = "sandbox,i2s";
1011 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001012 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001013 };
1014
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001015 nop-test_0 {
1016 compatible = "sandbox,nop_sandbox1";
1017 nop-test_1 {
1018 compatible = "sandbox,nop_sandbox2";
1019 bind = "True";
1020 };
1021 nop-test_2 {
1022 compatible = "sandbox,nop_sandbox2";
1023 bind = "False";
1024 };
1025 };
1026
Roger Quadrosb0679a72022-10-20 16:30:46 +03001027 memory-controller {
1028 compatible = "sandbox,memory";
1029 };
1030
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001031 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001032 #address-cells = <1>;
1033 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001034 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001035
1036 eth5_addr: mac-address@10 {
1037 reg = <0x10 6>;
1038 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001039 };
1040
Simon Glasse4fef742017-04-23 20:02:07 -06001041 mmc2 {
1042 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001043 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001044 };
1045
Simon Glassb255efc2022-04-24 23:31:24 -06001046 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001047 mmc1 {
1048 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001049 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001050 };
1051
Simon Glassb255efc2022-04-24 23:31:24 -06001052 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301053 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001054 compatible = "sandbox,mmc";
1055 };
1056
Simon Glassf1eba352022-10-20 18:23:20 -06001057 /* This is used for VBE VPL tests */
1058 mmc3 {
1059 status = "disabled";
1060 compatible = "sandbox,mmc";
1061 filename = "image.bin";
1062 non-removable;
1063 };
1064
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001065 /* This is used for bootstd bootmenu tests */
1066 mmc4 {
1067 status = "disabled";
1068 compatible = "sandbox,mmc";
1069 filename = "mmc4.img";
1070 };
1071
Simon Glassfff928c2023-08-24 13:55:41 -06001072 /* This is used for ChromiumOS tests */
1073 mmc5 {
1074 status = "disabled";
1075 compatible = "sandbox,mmc";
1076 filename = "mmc5.img";
1077 };
1078
Simon Glass53a68b32019-02-16 20:24:50 -07001079 pch {
1080 compatible = "sandbox,pch";
1081 };
1082
Tom Rini4a3ca482020-02-11 12:41:23 -05001083 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001084 compatible = "sandbox,pci";
1085 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001086 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001087 #address-cells = <3>;
1088 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001089 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001090 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001091 iommu-map = <0x0010 &iommu 0 1>;
1092 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001093 pci@0,0 {
1094 compatible = "pci-generic";
1095 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001096 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001097 };
Alex Margineanf1274432019-06-07 11:24:24 +03001098 pci@1,0 {
1099 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001100 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1101 reg = <0x02000814 0 0 0 0
1102 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001103 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001104 };
Simon Glass937bb472019-12-06 21:41:57 -07001105 p2sb-pci@2,0 {
1106 compatible = "sandbox,p2sb";
1107 reg = <0x02001010 0 0 0 0>;
1108 sandbox,emul = <&p2sb_emul>;
1109
1110 adder {
1111 intel,p2sb-port-id = <3>;
1112 compatible = "sandbox,adder";
1113 };
1114 };
Simon Glass8c501022019-12-06 21:41:54 -07001115 pci@1e,0 {
1116 compatible = "sandbox,pmc";
1117 reg = <0xf000 0 0 0 0>;
1118 sandbox,emul = <&pmc_emul1e>;
1119 acpi-base = <0x400>;
1120 gpe0-dwx-mask = <0xf>;
1121 gpe0-dwx-shift-base = <4>;
1122 gpe0-dw = <6 7 9>;
1123 gpe0-sts = <0x20>;
1124 gpe0-en = <0x30>;
1125 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001126 pci@1f,0 {
1127 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001128 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1129 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001130 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001131 };
1132 };
1133
Simon Glassb98ba4c2019-09-25 08:56:10 -06001134 pci-emul0 {
1135 compatible = "sandbox,pci-emul-parent";
1136 swap_case_emul0_0: emul0@0,0 {
1137 compatible = "sandbox,swap-case";
1138 };
1139 swap_case_emul0_1: emul0@1,0 {
1140 compatible = "sandbox,swap-case";
1141 use-ea;
1142 };
1143 swap_case_emul0_1f: emul0@1f,0 {
1144 compatible = "sandbox,swap-case";
1145 };
Simon Glass937bb472019-12-06 21:41:57 -07001146 p2sb_emul: emul@2,0 {
1147 compatible = "sandbox,p2sb-emul";
1148 };
Simon Glass8c501022019-12-06 21:41:54 -07001149 pmc_emul1e: emul@1e,0 {
1150 compatible = "sandbox,pmc-emul";
1151 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001152 };
1153
Tom Rini4a3ca482020-02-11 12:41:23 -05001154 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001155 compatible = "sandbox,pci";
1156 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001157 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001158 #address-cells = <3>;
1159 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001160 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001161 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001162 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001163 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001164 0x0c 0x00 0x1234 0x5678
1165 0x10 0x00 0x1234 0x5678>;
1166 pci@10,0 {
1167 reg = <0x8000 0 0 0 0>;
1168 };
Bin Meng408e5902018-08-03 01:14:41 -07001169 };
1170
Tom Rini4a3ca482020-02-11 12:41:23 -05001171 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001172 compatible = "sandbox,pci";
1173 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001174 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001175 #address-cells = <3>;
1176 #size-cells = <2>;
1177 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1178 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1179 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1180 pci@1f,0 {
1181 compatible = "pci-generic";
1182 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001183 sandbox,emul = <&swap_case_emul2_1f>;
1184 };
1185 };
1186
1187 pci-emul2 {
1188 compatible = "sandbox,pci-emul-parent";
1189 swap_case_emul2_1f: emul2@1f,0 {
1190 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001191 };
1192 };
1193
Ramon Friedc64f19b2019-04-27 11:15:23 +03001194 pci_ep: pci_ep {
1195 compatible = "sandbox,pci_ep";
1196 };
1197
Simon Glass9c433fe2017-04-23 20:10:44 -06001198 probing {
1199 compatible = "simple-bus";
1200 test1 {
1201 compatible = "denx,u-boot-probe-test";
1202 };
1203
1204 test2 {
1205 compatible = "denx,u-boot-probe-test";
1206 };
1207
1208 test3 {
1209 compatible = "denx,u-boot-probe-test";
1210 };
1211
1212 test4 {
1213 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001214 first-syscon = <&syscon0>;
1215 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001216 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001217 };
1218 };
1219
Stephen Warren92c67fa2016-07-13 13:45:31 -06001220 pwrdom: power-domain {
1221 compatible = "sandbox,power-domain";
1222 #power-domain-cells = <1>;
1223 };
1224
1225 power-domain-test {
1226 compatible = "sandbox,power-domain-test";
1227 power-domains = <&pwrdom 2>;
1228 };
1229
Simon Glass5620cf82018-10-01 12:22:40 -06001230 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001231 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001232 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001233 pinctrl-names = "default";
1234 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001235 };
1236
1237 pwm2 {
1238 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001239 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001240 };
1241
Simon Glass3d355e62015-07-06 12:54:31 -06001242 ram {
1243 compatible = "sandbox,ram";
1244 };
1245
Simon Glassd860f222015-07-06 12:54:29 -06001246 reset@0 {
1247 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001248 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001249 };
1250
1251 reset@1 {
1252 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001253 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001254 };
1255
Stephen Warren6488e642016-06-17 09:43:59 -06001256 resetc: reset-ctl {
1257 compatible = "sandbox,reset-ctl";
1258 #reset-cells = <1>;
1259 };
1260
1261 reset-ctl-test {
1262 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001263 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1264 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001265 };
1266
Sughosh Ganu23e37512019-12-28 23:58:31 +05301267 rng {
1268 compatible = "sandbox,sandbox-rng";
1269 };
1270
Nishanth Menonedf85812015-09-17 15:42:41 -05001271 rproc_1: rproc@1 {
1272 compatible = "sandbox,test-processor";
1273 remoteproc-name = "remoteproc-test-dev1";
1274 };
1275
1276 rproc_2: rproc@2 {
1277 compatible = "sandbox,test-processor";
1278 internal-memory-mapped;
1279 remoteproc-name = "remoteproc-test-dev2";
1280 };
1281
Simon Glass5620cf82018-10-01 12:22:40 -06001282 panel {
1283 compatible = "simple-panel";
1284 backlight = <&backlight 0 100>;
1285 };
1286
Simon Glass509f32e2022-09-21 16:21:47 +02001287 scsi {
1288 compatible = "sandbox,scsi";
1289 sandbox,filepath = "scsi.img";
1290 };
1291
Ramon Fried26ed32e2018-07-02 02:57:59 +03001292 smem@0 {
1293 compatible = "sandbox,smem";
1294 };
1295
Simon Glass76072ac2018-12-10 10:37:36 -07001296 sound {
1297 compatible = "sandbox,sound";
1298 cpu {
1299 sound-dai = <&i2s 0>;
1300 };
1301
1302 codec {
1303 sound-dai = <&audio 0>;
1304 };
1305 };
1306
Simon Glass25348a42014-10-13 23:42:11 -06001307 spi@0 {
1308 #address-cells = <1>;
1309 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001310 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001311 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001312 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001313 pinctrl-names = "default";
1314 pinctrl-0 = <&pinmux_spi0_pins>;
1315
Simon Glass25348a42014-10-13 23:42:11 -06001316 spi.bin@0 {
1317 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001318 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001319 spi-max-frequency = <40000000>;
1320 sandbox,filename = "spi.bin";
1321 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001322 spi.bin@1 {
1323 reg = <1>;
1324 compatible = "spansion,m25p16", "jedec,spi-nor";
1325 spi-max-frequency = <50000000>;
1326 sandbox,filename = "spi.bin";
1327 spi-cpol;
1328 spi-cpha;
1329 };
Simon Glass25348a42014-10-13 23:42:11 -06001330 };
1331
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001332 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001333 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001334 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001335 };
1336
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001337 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001338 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001339 reg = <0x20 5
1340 0x28 6
1341 0x30 7
1342 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001343 };
1344
Patrick Delaunayee010432019-03-07 09:57:13 +01001345 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001346 compatible = "simple-mfd", "syscon";
1347 reg = <0x40 5
1348 0x48 6
1349 0x50 7
1350 0x58 8>;
1351 };
1352
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301353 syscon3: syscon@3 {
1354 compatible = "simple-mfd", "syscon";
1355 reg = <0x000100 0x10>;
1356
1357 muxcontroller0: a-mux-controller {
1358 compatible = "mmio-mux";
1359 #mux-control-cells = <1>;
1360
1361 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1362 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1363 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1364 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1365 u-boot,mux-autoprobe;
1366 };
1367 };
1368
1369 muxcontroller1: emul-mux-controller {
1370 compatible = "mux-emul";
1371 #mux-control-cells = <0>;
1372 u-boot,mux-autoprobe;
1373 idle-state = <0xabcd>;
1374 };
1375
Simon Glass791a17f2020-12-16 21:20:27 -07001376 testfdtm0 {
1377 compatible = "denx,u-boot-fdtm-test";
1378 };
1379
1380 testfdtm1: testfdtm1 {
1381 compatible = "denx,u-boot-fdtm-test";
1382 };
1383
1384 testfdtm2 {
1385 compatible = "denx,u-boot-fdtm-test";
1386 };
1387
Sean Anderson79d3bba2020-09-28 10:52:23 -04001388 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001389 compatible = "sandbox,timer";
1390 clock-frequency = <1000000>;
1391 };
1392
Sean Anderson79d3bba2020-09-28 10:52:23 -04001393 timer@1 {
1394 compatible = "sandbox,timer";
1395 sandbox,timebase-frequency-fallback;
1396 };
1397
Miquel Raynal80938c12018-05-15 11:57:27 +02001398 tpm2 {
1399 compatible = "sandbox,tpm2";
1400 };
1401
Simon Glasseef107e2023-02-21 06:24:51 -07001402 tpm {
1403 compatible = "google,sandbox-tpm";
1404 };
1405
Simon Glass5b968632015-05-22 15:42:15 -06001406 uart0: serial {
1407 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001408 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001409 pinctrl-names = "default";
1410 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001411 };
1412
Simon Glass31680482015-03-25 12:23:05 -06001413 usb_0: usb@0 {
1414 compatible = "sandbox,usb";
1415 status = "disabled";
1416 hub {
1417 compatible = "sandbox,usb-hub";
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1420 flash-stick {
1421 reg = <0>;
1422 compatible = "sandbox,usb-flash";
1423 };
1424 };
1425 };
1426
1427 usb_1: usb@1 {
1428 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001429 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001430 hub {
1431 compatible = "usb-hub";
1432 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001433 #address-cells = <1>;
1434 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001435 hub-emul {
1436 compatible = "sandbox,usb-hub";
1437 #address-cells = <1>;
1438 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001439 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001440 reg = <0>;
1441 compatible = "sandbox,usb-flash";
1442 sandbox,filepath = "testflash.bin";
1443 };
1444
Simon Glass4700fe52015-11-08 23:48:01 -07001445 flash-stick@1 {
1446 reg = <1>;
1447 compatible = "sandbox,usb-flash";
1448 sandbox,filepath = "testflash1.bin";
1449 };
1450
1451 flash-stick@2 {
1452 reg = <2>;
1453 compatible = "sandbox,usb-flash";
1454 sandbox,filepath = "testflash2.bin";
1455 };
1456
Simon Glassc0ccc722015-11-08 23:48:08 -07001457 keyb@3 {
1458 reg = <3>;
1459 compatible = "sandbox,usb-keyb";
1460 };
1461
Simon Glass31680482015-03-25 12:23:05 -06001462 };
Michael Walle7c961322020-06-02 01:47:07 +02001463
1464 usbstor@1 {
1465 reg = <1>;
1466 };
1467 usbstor@3 {
1468 reg = <3>;
1469 };
Simon Glass31680482015-03-25 12:23:05 -06001470 };
1471 };
1472
1473 usb_2: usb@2 {
1474 compatible = "sandbox,usb";
1475 status = "disabled";
1476 };
1477
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001478 spmi: spmi@0 {
1479 compatible = "sandbox,spmi";
1480 #address-cells = <0x1>;
1481 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001482 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001483 pm8916@0 {
1484 compatible = "qcom,spmi-pmic";
1485 reg = <0x0 0x1>;
1486 #address-cells = <0x1>;
1487 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001488 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001489
1490 spmi_gpios: gpios@c000 {
1491 compatible = "qcom,pm8916-gpio";
1492 reg = <0xc000 0x400>;
1493 gpio-controller;
1494 gpio-count = <4>;
1495 #gpio-cells = <2>;
1496 gpio-bank-name="spmi";
1497 };
1498 };
1499 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001500
1501 wdt0: wdt@0 {
1502 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001503 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001504 };
Rob Clarka471b672018-01-10 11:33:30 +01001505
Mario Six95922152018-08-09 14:51:19 +02001506 axi: axi@0 {
1507 compatible = "sandbox,axi";
1508 #address-cells = <0x1>;
1509 #size-cells = <0x1>;
1510 store@0 {
1511 compatible = "sandbox,sandbox_store";
1512 reg = <0x0 0x400>;
1513 };
1514 };
1515
Rob Clarka471b672018-01-10 11:33:30 +01001516 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001517 #address-cells = <1>;
1518 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001519 setting = "sunrise ohoka";
1520 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001521 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001522 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001523 chosen-test {
1524 compatible = "denx,u-boot-fdt-test";
1525 reg = <9 1>;
1526 };
1527 };
Mario Six35616ef2018-03-12 14:53:33 +01001528
1529 translation-test@8000 {
1530 compatible = "simple-bus";
1531 reg = <0x8000 0x4000>;
1532
1533 #address-cells = <0x2>;
1534 #size-cells = <0x1>;
1535
1536 ranges = <0 0x0 0x8000 0x1000
1537 1 0x100 0x9000 0x1000
1538 2 0x200 0xA000 0x1000
1539 3 0x300 0xB000 0x1000
1540 >;
1541
Fabien Dessenne22236e02019-05-31 15:11:30 +02001542 dma-ranges = <0 0x000 0x10000000 0x1000
1543 1 0x100 0x20000000 0x1000
1544 >;
1545
Mario Six35616ef2018-03-12 14:53:33 +01001546 dev@0,0 {
1547 compatible = "denx,u-boot-fdt-dummy";
1548 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001549 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001550 };
1551
1552 dev@1,100 {
1553 compatible = "denx,u-boot-fdt-dummy";
1554 reg = <1 0x100 0x1000>;
1555
1556 };
1557
1558 dev@2,200 {
1559 compatible = "denx,u-boot-fdt-dummy";
1560 reg = <2 0x200 0x1000>;
1561 };
1562
1563
1564 noxlatebus@3,300 {
1565 compatible = "simple-bus";
1566 reg = <3 0x300 0x1000>;
1567
1568 #address-cells = <0x1>;
1569 #size-cells = <0x0>;
1570
1571 dev@42 {
1572 compatible = "denx,u-boot-fdt-dummy";
1573 reg = <0x42>;
1574 };
1575 };
1576 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001577
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001578 ofnode-foreach {
1579 compatible = "foreach";
1580
1581 first {
1582 prop1 = <1>;
1583 prop2 = <2>;
1584 };
1585
1586 second {
1587 prop1 = <1>;
1588 prop2 = <2>;
1589 };
1590 };
1591
Mario Six02ad6fb2018-09-27 09:19:31 +02001592 osd {
1593 compatible = "sandbox,sandbox_osd";
1594 };
Tom Rinib93eea72018-09-30 18:16:51 -04001595
Jens Wiklander86afaa62018-09-25 16:40:16 +02001596 sandbox_tee {
1597 compatible = "sandbox,tee";
1598 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001599
1600 sandbox_virtio1 {
1601 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001602 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001603 };
1604
1605 sandbox_virtio2 {
1606 compatible = "sandbox,virtio2";
1607 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001608
Simon Glass8de5a542023-01-17 10:47:51 -07001609 sandbox-virtio-blk {
1610 compatible = "sandbox,virtio1";
1611 virtio-type = <2>; /* block */
1612 };
1613
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001614 sandbox_scmi {
1615 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001616 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001617 resets = <&reset_scmi 3>;
1618 regul0-supply = <&regul0_scmi>;
1619 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001620 };
1621
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001622 pinctrl {
1623 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001624
Sean Anderson3438e3b2020-09-14 11:01:57 -04001625 pinctrl-names = "default", "alternate";
1626 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1627 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001628
Sean Anderson3438e3b2020-09-14 11:01:57 -04001629 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001630 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001631 pins = "P5";
1632 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001633 bias-pull-up;
1634 input-disable;
1635 };
1636 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001637 pins = "P6";
1638 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001639 output-high;
1640 drive-open-drain;
1641 };
1642 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001643 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001644 bias-pull-down;
1645 input-enable;
1646 };
1647 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001648 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001649 bias-disable;
1650 };
1651 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001652
1653 pinctrl_i2c: i2c {
1654 groups {
1655 groups = "I2C_UART";
1656 function = "I2C";
1657 };
1658
1659 pins {
1660 pins = "P0", "P1";
1661 drive-open-drain;
1662 };
1663 };
1664
1665 pinctrl_i2s: i2s {
1666 groups = "SPI_I2S";
1667 function = "I2S";
1668 };
1669
1670 pinctrl_spi: spi {
1671 groups = "SPI_I2S";
1672 function = "SPI";
1673
1674 cs {
1675 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1676 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1677 };
1678 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001679 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001680
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001681 pinctrl-single-no-width {
1682 compatible = "pinctrl-single";
1683 reg = <0x0000 0x238>;
1684 #pinctrl-cells = <1>;
1685 pinctrl-single,function-mask = <0x7f>;
1686 };
1687
1688 pinctrl-single-pins {
1689 compatible = "pinctrl-single";
1690 reg = <0x0000 0x238>;
1691 #pinctrl-cells = <1>;
1692 pinctrl-single,register-width = <32>;
1693 pinctrl-single,function-mask = <0x7f>;
1694
1695 pinmux_pwm_pins: pinmux_pwm_pins {
1696 pinctrl-single,pins = < 0x48 0x06 >;
1697 };
1698
1699 pinmux_spi0_pins: pinmux_spi0_pins {
1700 pinctrl-single,pins = <
1701 0x190 0x0c
1702 0x194 0x0c
1703 0x198 0x23
1704 0x19c 0x0c
1705 >;
1706 };
1707
1708 pinmux_uart0_pins: pinmux_uart0_pins {
1709 pinctrl-single,pins = <
1710 0x70 0x30
1711 0x74 0x00
1712 >;
1713 };
1714 };
1715
1716 pinctrl-single-bits {
1717 compatible = "pinctrl-single";
1718 reg = <0x0000 0x50>;
1719 #pinctrl-cells = <2>;
1720 pinctrl-single,bit-per-mux;
1721 pinctrl-single,register-width = <32>;
1722 pinctrl-single,function-mask = <0xf>;
1723
1724 pinmux_i2c0_pins: pinmux_i2c0_pins {
1725 pinctrl-single,bits = <
1726 0x10 0x00002200 0x0000ff00
1727 >;
1728 };
1729
1730 pinmux_lcd_pins: pinmux_lcd_pins {
1731 pinctrl-single,bits = <
1732 0x40 0x22222200 0xffffff00
1733 0x44 0x22222222 0xffffffff
1734 0x48 0x00000022 0x000000ff
1735 0x48 0x02000000 0x0f000000
1736 0x4c 0x02000022 0x0f0000ff
1737 >;
1738 };
1739 };
1740
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001741 hwspinlock@0 {
1742 compatible = "sandbox,hwspinlock";
1743 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001744
1745 dma: dma {
1746 compatible = "sandbox,dma";
1747 #dma-cells = <1>;
1748
1749 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1750 dma-names = "m2m", "tx0", "rx0";
1751 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001752
Alex Marginean0649be52019-07-12 10:13:53 +03001753 /*
1754 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1755 * end of the test. If parent mdio is removed first, clean-up of the
1756 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1757 * active at the end of the test. That it turn doesn't allow the mdio
1758 * class to be destroyed, triggering an error.
1759 */
1760 mdio-mux-test {
1761 compatible = "sandbox,mdio-mux";
1762 #address-cells = <1>;
1763 #size-cells = <0>;
1764 mdio-parent-bus = <&mdio>;
1765
1766 mdio-ch-test@0 {
1767 reg = <0>;
1768 };
1769 mdio-ch-test@1 {
1770 reg = <1>;
1771 };
1772 };
1773
1774 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001775 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001776 #address-cells = <1>;
1777 #size-cells = <0>;
1778
1779 ethphy1: ethernet-phy@1 {
1780 reg = <1>;
1781 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001782 };
Sean Andersonb7860542020-06-24 06:41:12 -04001783
1784 pm-bus-test {
1785 compatible = "simple-pm-bus";
1786 clocks = <&clk_sandbox 4>;
1787 power-domains = <&pwrdom 1>;
1788 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001789
1790 resetc2: syscon-reset {
1791 compatible = "syscon-reset";
1792 #reset-cells = <1>;
1793 regmap = <&syscon0>;
1794 offset = <1>;
1795 mask = <0x27FFFFFF>;
1796 assert-high = <0>;
1797 };
1798
1799 syscon-reset-test {
1800 compatible = "sandbox,misc_sandbox";
1801 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1802 reset-names = "valid", "no_mask", "out_of_range";
1803 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301804
Simon Glass458b66a2020-11-05 06:32:05 -07001805 sysinfo {
1806 compatible = "sandbox,sysinfo-sandbox";
1807 };
1808
Sean Anderson1c830672021-04-20 10:50:58 -04001809 sysinfo-gpio {
1810 compatible = "gpio-sysinfo";
1811 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1812 revisions = <19>, <5>;
1813 names = "rev_a", "foo";
1814 };
1815
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301816 some_regmapped-bus {
1817 #address-cells = <0x1>;
1818 #size-cells = <0x1>;
1819
1820 ranges = <0x0 0x0 0x10>;
1821 compatible = "simple-bus";
1822
1823 regmap-test_0 {
1824 reg = <0 0x10>;
1825 compatible = "sandbox,regmap_test";
1826 };
1827 };
Robert Marko9cf87122022-09-06 13:30:35 +02001828
1829 thermal {
1830 compatible = "sandbox,thermal";
1831 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301832
1833 fwu-mdata {
1834 compatible = "u-boot,fwu-mdata-gpt";
1835 fwu-mdata-store = <&mmc0>;
1836 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001837
1838 nvmxip-qspi1@08000000 {
1839 compatible = "nvmxip,qspi";
1840 reg = <0x08000000 0x00200000>;
1841 lba_shift = <9>;
1842 lba = <4096>;
1843 };
1844
1845 nvmxip-qspi2@08200000 {
1846 compatible = "nvmxip,qspi";
1847 reg = <0x08200000 0x00100000>;
1848 lba_shift = <9>;
1849 lba = <2048>;
1850 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001851
1852 extcon {
1853 compatible = "sandbox,extcon";
1854 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001855
1856 arm-ffa-emul {
1857 compatible = "sandbox,arm-ffa-emul";
1858
1859 sandbox-arm-ffa {
1860 compatible = "sandbox,arm-ffa";
1861 };
1862 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001863};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001864
1865#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001866#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001867
1868#ifdef CONFIG_SANDBOX_VPL
1869#include "sandbox_vpl.dtsi"
1870#endif
Simon Glass61300722023-06-01 10:23:01 -06001871
1872#include "cedit.dtsi"