blob: c0ed2d83f3d2b974732051723a3a8eb57c79b9bf [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060042 mmc4 = "/mmc4";
43 mmc5 = "/mmc5";
Bin Meng408e5902018-08-03 01:14:41 -070044 pci0 = &pci0;
45 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070046 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020047 remoteproc0 = &rproc_1;
48 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060049 rtc0 = &rtc_0;
50 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060051 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020052 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070053 testbus3 = "/some-bus";
54 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070055 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070056 testfdt3 = "/b-test";
57 testfdt5 = "/some-bus/c-test@5";
58 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070059 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020060 fdt-dummy0 = "/translation-test@8000/dev@0,0";
61 fdt-dummy1 = "/translation-test@8000/dev@1,100";
62 fdt-dummy2 = "/translation-test@8000/dev@2,200";
63 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060064 usb0 = &usb_0;
65 usb1 = &usb_1;
66 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020067 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020068 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060069 };
70
Simon Glass5e135d32022-10-20 18:23:15 -060071 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020072 };
73
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 config {
Simon Glass0034d962021-08-07 07:24:01 -060075 testing-bool;
76 testing-int = <123>;
77 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020078 environment {
79 from_fdt = "yes";
80 fdt_env_path = "";
81 };
82 };
83
Michal Simek43c42bd2023-08-31 08:59:05 +020084 options {
85 u-boot {
86 compatible = "u-boot,config";
87 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +020088 bootscr-flash-offset = /bits/ 64 <0>;
89 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simek43c42bd2023-08-31 08:59:05 +020090 };
91 };
92
Simon Glassb255efc2022-04-24 23:31:24 -060093 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -070094 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -060095 compatible = "u-boot,boot-std";
96
97 filename-prefixes = "/", "/boot/";
98 bootdev-order = "mmc2", "mmc1";
99
Simon Glassb71d7f72023-05-10 16:34:46 -0600100 extlinux {
101 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600102 };
103
104 efi {
105 compatible = "u-boot,distro-efi";
106 };
Simon Glassa9289612022-10-20 18:23:14 -0600107
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600108 theme {
109 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600110 menu-inset = <3>;
111 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600112 };
113
Simon Glass82adc292023-08-14 16:40:30 -0600114 cedit-theme {
115 font-size = <30>;
116 menu-inset = <3>;
117 menuitem-gap-y = <1>;
118 };
119
Simon Glassf1eba352022-10-20 18:23:20 -0600120 /*
121 * This is used for the VBE OS-request tests. A FAT filesystem
122 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200123 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600124 */
Simon Glassa9289612022-10-20 18:23:14 -0600125 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700126 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600127 compatible = "fwupd,vbe-simple";
128 storage = "mmc1";
129 skip-offset = <0x200>;
130 area-start = <0x400>;
131 area-size = <0x1000>;
132 state-offset = <0x400>;
133 state-size = <0x40>;
134 version-offset = <0x800>;
135 version-size = <0x100>;
136 };
Simon Glassf1eba352022-10-20 18:23:20 -0600137
138 /*
139 * This is used for the VBE VPL tests. The MMC device holds the
140 * binman image.bin file. The test progresses through each phase
141 * of U-Boot, loading each in turn from MMC.
142 *
143 * Note that the test enables this node (and mmc3) before
144 * running U-Boot
145 */
146 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700147 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600148 status = "disabled";
149 compatible = "fwupd,vbe-simple";
150 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200151 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600152 area-start = <0>;
153 area-size = <0xe00000>;
154 state-offset = <0xdffc00>;
155 state-size = <0x40>;
156 version-offset = <0xdffe00>;
157 version-size = <0x100>;
158 };
Simon Glassb255efc2022-04-24 23:31:24 -0600159 };
160
Simon Glass61300722023-06-01 10:23:01 -0600161 cedit: cedit {
162 };
163
Andrew Scull451b8b12022-05-30 10:00:12 +0000164 fuzzing-engine {
165 compatible = "sandbox,fuzzing-engine";
166 };
167
Nandor Han6521e5d2021-06-10 16:56:44 +0300168 reboot-mode0 {
169 compatible = "reboot-mode-gpio";
170 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
171 u-boot,env-variable = "bootstatus";
172 mode-test = <0x01>;
173 mode-download = <0x03>;
174 };
175
Nandor Han7e4067a2021-06-10 16:56:45 +0300176 reboot_mode1: reboot-mode@14 {
177 compatible = "reboot-mode-rtc";
178 rtc = <&rtc_0>;
179 reg = <0x30 4>;
180 u-boot,env-variable = "bootstatus";
181 big-endian;
182 mode-test = <0x21969147>;
183 mode-download = <0x51939147>;
184 };
185
Simon Glassed96cde2018-12-10 10:37:33 -0700186 audio: audio-codec {
187 compatible = "sandbox,audio-codec";
188 #sound-dai-cells = <1>;
189 };
190
Philippe Reynes1ee26482020-07-24 18:19:51 +0200191 buttons {
192 compatible = "gpio-keys";
193
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200194 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200195 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200196 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300197 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200198 };
199
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200200 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200201 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200202 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300203 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200204 };
205 };
206
Marek Szyprowskiad398592021-02-18 11:33:18 +0100207 buttons2 {
208 compatible = "adc-keys";
209 io-channels = <&adc 3>;
210 keyup-threshold-microvolt = <3000000>;
211
212 button-up {
213 label = "button3";
214 linux,code = <KEY_F3>;
215 press-threshold-microvolt = <1500000>;
216 };
217
218 button-down {
219 label = "button4";
220 linux,code = <KEY_F4>;
221 press-threshold-microvolt = <1000000>;
222 };
223
224 button-enter {
225 label = "button5";
226 linux,code = <KEY_F5>;
227 press-threshold-microvolt = <500000>;
228 };
229 };
230
Simon Glassc953aaf2018-12-10 10:37:34 -0700231 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600232 reg = <0 0>;
233 compatible = "google,cros-ec-sandbox";
234
235 /*
236 * This describes the flash memory within the EC. Note
237 * that the STM32L flash erases to 0, not 0xff.
238 */
239 flash {
240 image-pos = <0x08000000>;
241 size = <0x20000>;
242 erase-value = <0>;
243
244 /* Information for sandbox */
245 ro {
246 image-pos = <0>;
247 size = <0xf000>;
248 };
249 wp-ro {
250 image-pos = <0xf000>;
251 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700252 used = <0x884>;
253 compress = "lz4";
254 uncomp-size = <0xcf8>;
255 hash {
256 algo = "sha256";
257 value = [00 01 02 03 04 05 06 07
258 08 09 0a 0b 0c 0d 0e 0f
259 10 11 12 13 14 15 16 17
260 18 19 1a 1b 1c 1d 1e 1f];
261 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600262 };
263 rw {
264 image-pos = <0x10000>;
265 size = <0x10000>;
266 };
267 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300268
269 cros_ec_pwm: cros-ec-pwm {
270 compatible = "google,cros-ec-pwm";
271 #pwm-cells = <1>;
272 };
273
Simon Glass699c9ca2018-10-01 12:22:08 -0600274 };
275
Yannick Fertré9712c822019-10-07 15:29:05 +0200276 dsi_host: dsi_host {
277 compatible = "sandbox,dsi-host";
278 };
279
Simon Glassb2c1cac2014-02-26 15:59:21 -0700280 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600281 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700282 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600283 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700284 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700285 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100286 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
287 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700288 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100289 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
290 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
291 <&gpio_b 7 GPIO_IN 3 2 1>,
292 <&gpio_b 8 GPIO_OUT 3 2 1>,
293 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100294 test3-gpios =
295 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
296 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
297 <&gpio_c 2 GPIO_OUT>,
298 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
299 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200300 <&gpio_c 5 GPIO_IN>,
301 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
302 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530303 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
304 test5-gpios = <&gpio_a 19>;
305
Simon Glass73025392021-10-23 17:26:04 -0600306 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200307 int8-value = /bits/ 8 <0x12>;
308 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700309 int-value = <1234>;
310 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200311 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200312 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200313 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600314 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700315 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600316 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200317 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530318
319 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
320 <&muxcontroller0 2>, <&muxcontroller0 3>,
321 <&muxcontroller1>;
322 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
323 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100324 display-timings {
325 timing0: 240x320 {
326 clock-frequency = <6500000>;
327 hactive = <240>;
328 vactive = <320>;
329 hfront-porch = <6>;
330 hback-porch = <7>;
331 hsync-len = <1>;
332 vback-porch = <5>;
333 vfront-porch = <8>;
334 vsync-len = <2>;
335 hsync-active = <1>;
336 vsync-active = <0>;
337 de-active = <1>;
338 pixelclk-active = <1>;
339 interlaced;
340 doublescan;
341 doubleclk;
342 };
343 timing1: 480x800 {
344 clock-frequency = <9000000>;
345 hactive = <480>;
346 vactive = <800>;
347 hfront-porch = <10>;
348 hback-porch = <59>;
349 hsync-len = <12>;
350 vback-porch = <15>;
351 vfront-porch = <17>;
352 vsync-len = <16>;
353 hsync-active = <0>;
354 vsync-active = <1>;
355 de-active = <0>;
356 pixelclk-active = <0>;
357 };
358 timing2: 800x480 {
359 clock-frequency = <33500000>;
360 hactive = <800>;
361 vactive = <480>;
362 hback-porch = <89>;
363 hfront-porch = <164>;
364 vback-porch = <23>;
365 vfront-porch = <10>;
366 hsync-len = <11>;
367 vsync-len = <13>;
368 };
369 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200370 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530371 clock-frequency = <6500000>;
372 hactive = <240>;
373 vactive = <320>;
374 hfront-porch = <6>;
375 hback-porch = <7>;
376 hsync-len = <1>;
377 vback-porch = <5>;
378 vfront-porch = <8>;
379 vsync-len = <2>;
380 hsync-active = <1>;
381 vsync-active = <0>;
382 de-active = <1>;
383 pixelclk-active = <1>;
384 interlaced;
385 doublescan;
386 doubleclk;
387 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700388 };
389
390 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600391 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700392 compatible = "not,compatible";
393 };
394
395 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600396 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700397 };
398
Simon Glass5620cf82018-10-01 12:22:40 -0600399 backlight: backlight {
400 compatible = "pwm-backlight";
401 enable-gpios = <&gpio_a 1>;
402 power-supply = <&ldo_1>;
403 pwms = <&pwm 0 1000>;
404 default-brightness-level = <5>;
405 brightness-levels = <0 16 32 64 128 170 202 234 255>;
406 };
407
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200408 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200409 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200410 bind-test-child1 {
411 compatible = "sandbox,phy";
412 #phy-cells = <1>;
413 };
414
415 bind-test-child2 {
416 compatible = "simple-bus";
417 };
418 };
419
Simon Glassb2c1cac2014-02-26 15:59:21 -0700420 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600421 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700422 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600423 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700424 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530425
426 mux-controls = <&muxcontroller0 0>;
427 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700428 };
429
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200430 phy_provider0: gen_phy@0 {
431 compatible = "sandbox,phy";
432 #phy-cells = <1>;
433 };
434
435 phy_provider1: gen_phy@1 {
436 compatible = "sandbox,phy";
437 #phy-cells = <0>;
438 broken;
439 };
440
developer71092972020-05-02 11:35:12 +0200441 phy_provider2: gen_phy@2 {
442 compatible = "sandbox,phy";
443 #phy-cells = <0>;
444 };
445
Jonas Karlman9f89e682023-08-31 22:16:35 +0000446 phy_provider3: gen_phy@3 {
447 compatible = "sandbox,phy";
448 #phy-cells = <2>;
449 };
450
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200451 gen_phy_user: gen_phy_user {
452 compatible = "simple-bus";
453 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
454 phy-names = "phy1", "phy2", "phy3";
455 };
456
developer71092972020-05-02 11:35:12 +0200457 gen_phy_user1: gen_phy_user1 {
458 compatible = "simple-bus";
459 phys = <&phy_provider0 0>, <&phy_provider2>;
460 phy-names = "phy1", "phy2";
461 };
462
Jonas Karlman9f89e682023-08-31 22:16:35 +0000463 gen_phy_user2: gen_phy_user2 {
464 compatible = "simple-bus";
465 phys = <&phy_provider3 0 0>;
466 phy-names = "phy1";
467 };
468
Simon Glassb2c1cac2014-02-26 15:59:21 -0700469 some-bus {
470 #address-cells = <1>;
471 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600472 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600473 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600474 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700475 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600476 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700477 compatible = "denx,u-boot-fdt-test";
478 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600479 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700480 ping-add = <5>;
481 };
Simon Glass40717422014-07-23 06:55:18 -0600482 c-test@0 {
483 compatible = "denx,u-boot-fdt-test";
484 reg = <0>;
485 ping-expect = <6>;
486 ping-add = <6>;
487 };
488 c-test@1 {
489 compatible = "denx,u-boot-fdt-test";
490 reg = <1>;
491 ping-expect = <7>;
492 ping-add = <7>;
493 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700494 };
495
496 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600497 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600498 ping-expect = <6>;
499 ping-add = <6>;
500 compatible = "google,another-fdt-test";
501 };
502
503 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600504 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600505 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700506 ping-add = <6>;
507 compatible = "google,another-fdt-test";
508 };
509
Simon Glass0ccb0972015-01-25 08:27:05 -0700510 f-test {
511 compatible = "denx,u-boot-fdt-test";
512 };
513
514 g-test {
515 compatible = "denx,u-boot-fdt-test";
516 };
517
Bin Mengd9d24782018-10-10 22:07:01 -0700518 h-test {
519 compatible = "denx,u-boot-fdt-test1";
520 };
521
developercf8bc132020-05-02 11:35:10 +0200522 i-test {
523 compatible = "mediatek,u-boot-fdt-test";
524 #address-cells = <1>;
525 #size-cells = <0>;
526
527 subnode@0 {
528 reg = <0>;
529 };
530
531 subnode@1 {
532 reg = <1>;
533 };
534
535 subnode@2 {
536 reg = <2>;
537 };
538 };
539
Simon Glass204675c2019-12-29 21:19:25 -0700540 devres-test {
541 compatible = "denx,u-boot-devres-test";
542 };
543
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530544 another-test {
545 reg = <0 2>;
546 compatible = "denx,u-boot-fdt-test";
547 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
548 test5-gpios = <&gpio_a 19>;
549 };
550
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100551 mmio-bus@0 {
552 #address-cells = <1>;
553 #size-cells = <1>;
554 compatible = "denx,u-boot-test-bus";
555 dma-ranges = <0x10000000 0x00000000 0x00040000>;
556
557 subnode@0 {
558 compatible = "denx,u-boot-fdt-test";
559 };
560 };
561
562 mmio-bus@1 {
563 #address-cells = <1>;
564 #size-cells = <1>;
565 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100566
567 subnode@0 {
568 compatible = "denx,u-boot-fdt-test";
569 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100570 };
571
Simon Glass3c601b12020-07-07 13:12:06 -0600572 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600573 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600574 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600575 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600576 child {
577 compatible = "denx,u-boot-acpi-test";
578 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600579 };
580
Simon Glass3c601b12020-07-07 13:12:06 -0600581 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600582 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600583 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600584 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600585 };
586
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200587 clocks {
588 clk_fixed: clk-fixed {
589 compatible = "fixed-clock";
590 #clock-cells = <0>;
591 clock-frequency = <1234>;
592 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000593
594 clk_fixed_factor: clk-fixed-factor {
595 compatible = "fixed-factor-clock";
596 #clock-cells = <0>;
597 clock-div = <3>;
598 clock-mult = <2>;
599 clocks = <&clk_fixed>;
600 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200601
602 osc {
603 compatible = "fixed-clock";
604 #clock-cells = <0>;
605 clock-frequency = <20000000>;
606 };
Stephen Warrena9622432016-06-17 09:44:00 -0600607 };
608
609 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600610 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600611 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200612 assigned-clocks = <&clk_sandbox 3>;
613 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600614 };
615
616 clk-test {
617 compatible = "sandbox,clk-test";
618 clocks = <&clk_fixed>,
619 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200620 <&clk_sandbox 0>,
621 <&clk_sandbox 3>,
622 <&clk_sandbox 2>;
623 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600624 };
625
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200626 clk-test2 {
627 compatible = "sandbox,clk-test";
628 assigned-clock-rates = <321>;
629 };
630
631 clk-test3 {
632 compatible = "sandbox,clk-test";
633 assigned-clocks = <&clk_sandbox 1>;
634 };
635
636 clk-test4 {
637 compatible = "sandbox,clk-test";
638 assigned-clock-rates = <654>, <321>;
639 assigned-clocks = <&clk_sandbox 1>;
640 };
641
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200642 ccf: clk-ccf {
643 compatible = "sandbox,clk-ccf";
644 };
645
Simon Glass507ab962021-12-04 08:56:31 -0700646 efi-media {
647 compatible = "sandbox,efi-media";
648 };
649
Simon Glass5b968632015-05-22 15:42:15 -0600650 eth@10002000 {
651 compatible = "sandbox,eth";
652 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600653 };
654
655 eth_5: eth@10003000 {
656 compatible = "sandbox,eth";
657 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400658 nvmem-cells = <&eth5_addr>;
659 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600660 };
661
Bin Meng04a11cb2015-08-27 22:25:53 -0700662 eth_3: sbe5 {
663 compatible = "sandbox,eth";
664 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400665 nvmem-cells = <&eth3_addr>;
666 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700667 };
668
Simon Glass5b968632015-05-22 15:42:15 -0600669 eth@10004000 {
670 compatible = "sandbox,eth";
671 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600672 };
673
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200674 phy_eth0: phy-test-eth {
675 compatible = "sandbox,eth";
676 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400677 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200678 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200679 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200680 };
681
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800682 dsa_eth0: dsa-test-eth {
683 compatible = "sandbox,eth";
684 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400685 nvmem-cells = <&eth4_addr>;
686 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800687 };
688
689 dsa-test {
690 compatible = "sandbox,dsa";
691
692 ports {
693 #address-cells = <1>;
694 #size-cells = <0>;
695 swp_0: port@0 {
696 reg = <0>;
697 label = "lan0";
698 phy-mode = "rgmii-rxid";
699
700 fixed-link {
701 speed = <100>;
702 full-duplex;
703 };
704 };
705
706 swp_1: port@1 {
707 reg = <1>;
708 label = "lan1";
709 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800710 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800711 };
712
713 port@2 {
714 reg = <2>;
715 ethernet = <&dsa_eth0>;
716
717 fixed-link {
718 speed = <1000>;
719 full-duplex;
720 };
721 };
722 };
723 };
724
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700725 firmware {
726 sandbox_firmware: sandbox-firmware {
727 compatible = "sandbox,firmware";
728 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200729
Etienne Carriere09665cb2022-02-21 09:22:39 +0100730 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200731 compatible = "sandbox,scmi-agent";
732 #address-cells = <1>;
733 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200734
Etienne Carriere09665cb2022-02-21 09:22:39 +0100735 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200736 reg = <0x14>;
737 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900738 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200739 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200740
Etienne Carriere09665cb2022-02-21 09:22:39 +0100741 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200742 reg = <0x16>;
743 #reset-cells = <1>;
744 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100745
746 protocol@17 {
747 reg = <0x17>;
748
749 regulators {
750 #address-cells = <1>;
751 #size-cells = <0>;
752
Etienne Carriere09665cb2022-02-21 09:22:39 +0100753 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100754 reg = <0>;
755 regulator-name = "sandbox-voltd0";
756 regulator-min-microvolt = <1100000>;
757 regulator-max-microvolt = <3300000>;
758 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100759 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100760 reg = <0x1>;
761 regulator-name = "sandbox-voltd1";
762 regulator-min-microvolt = <1800000>;
763 };
764 };
765 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200766 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700767 };
768
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200769 fpga {
770 compatible = "sandbox,fpga";
771 };
772
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100773 pinctrl-gpio {
774 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700775
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100776 gpio_a: base-gpios {
777 compatible = "sandbox,gpio";
778 gpio-controller;
779 #gpio-cells = <1>;
780 gpio-bank-name = "a";
781 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200782 hog_input_active_low {
783 gpio-hog;
784 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200785 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200786 };
787 hog_input_active_high {
788 gpio-hog;
789 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200790 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200791 };
792 hog_output_low {
793 gpio-hog;
794 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200795 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200796 };
797 hog_output_high {
798 gpio-hog;
799 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200800 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200801 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100802 };
803
804 gpio_b: extra-gpios {
805 compatible = "sandbox,gpio";
806 gpio-controller;
807 #gpio-cells = <5>;
808 gpio-bank-name = "b";
809 sandbox,gpio-count = <10>;
810 };
Simon Glass25348a42014-10-13 23:42:11 -0600811
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100812 gpio_c: pinmux-gpios {
813 compatible = "sandbox,gpio";
814 gpio-controller;
815 #gpio-cells = <2>;
816 gpio-bank-name = "c";
817 sandbox,gpio-count = <10>;
818 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100819 };
820
Simon Glass7df766e2014-12-10 08:55:55 -0700821 i2c@0 {
822 #address-cells = <1>;
823 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600824 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700825 compatible = "sandbox,i2c";
826 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200827 pinctrl-names = "default";
828 pinctrl-0 = <&pinmux_i2c0_pins>;
829
Simon Glass7df766e2014-12-10 08:55:55 -0700830 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400831 #address-cells = <1>;
832 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700833 reg = <0x2c>;
834 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700835 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200836 partitions {
837 compatible = "fixed-partitions";
838 #address-cells = <1>;
839 #size-cells = <1>;
840 bootcount_i2c: bootcount@10 {
841 reg = <10 2>;
842 };
843 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400844
845 eth3_addr: mac-address@24 {
846 reg = <24 6>;
847 };
Simon Glass7df766e2014-12-10 08:55:55 -0700848 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200849
Simon Glass336b2952015-05-22 15:42:17 -0600850 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400851 #address-cells = <1>;
852 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600853 reg = <0x43>;
854 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700855 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400856
857 eth4_addr: mac-address@40 {
858 reg = <0x40 6>;
859 };
Simon Glass336b2952015-05-22 15:42:17 -0600860 };
861
862 rtc_1: rtc@61 {
863 reg = <0x61>;
864 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700865 sandbox,emul = <&emul1>;
866 };
867
868 i2c_emul: emul {
869 reg = <0xff>;
870 compatible = "sandbox,i2c-emul-parent";
871 emul_eeprom: emul-eeprom {
872 compatible = "sandbox,i2c-eeprom";
873 sandbox,filename = "i2c.bin";
874 sandbox,size = <256>;
875 };
876 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700877 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700878 };
879 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700880 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600881 };
882 };
883
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200884 sandbox_pmic: sandbox_pmic {
885 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700886 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200887 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200888
889 mc34708: pmic@41 {
890 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700891 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200892 };
Simon Glass7df766e2014-12-10 08:55:55 -0700893 };
894
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100895 bootcount@0 {
896 compatible = "u-boot,bootcount-rtc";
897 rtc = <&rtc_1>;
898 offset = <0x13>;
899 };
900
Michal Simek4f18f922020-05-28 11:48:55 +0200901 bootcount {
902 compatible = "u-boot,bootcount-i2c-eeprom";
903 i2c-eeprom = <&bootcount_i2c>;
904 };
905
Nandor Han88895812021-06-10 15:40:38 +0300906 bootcount_4@0 {
907 compatible = "u-boot,bootcount-syscon";
908 syscon = <&syscon0>;
909 reg = <0x0 0x04>, <0x0 0x04>;
910 reg-names = "syscon_reg", "offset";
911 };
912
913 bootcount_2@0 {
914 compatible = "u-boot,bootcount-syscon";
915 syscon = <&syscon0>;
916 reg = <0x0 0x04>, <0x0 0x02> ;
917 reg-names = "syscon_reg", "offset";
918 };
919
Marek Szyprowskiad398592021-02-18 11:33:18 +0100920 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100921 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100922 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100923 vdd-supply = <&buck2>;
924 vss-microvolts = <0>;
925 };
926
Mark Kettenis67748ee2021-10-23 16:58:02 +0200927 iommu: iommu@0 {
928 compatible = "sandbox,iommu";
929 #iommu-cells = <0>;
930 };
931
Simon Glass515dcff2020-02-06 09:55:00 -0700932 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700933 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700934 interrupt-controller;
935 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700936 };
937
Simon Glass90b6fef2016-01-18 19:52:26 -0700938 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700939 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700940 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200941 pinctrl-names = "default";
942 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700943 xres = <1366>;
944 yres = <768>;
945 };
946
Simon Glassd783eb32015-07-06 12:54:34 -0600947 leds {
948 compatible = "gpio-leds";
949
950 iracibble {
951 gpios = <&gpio_a 1 0>;
952 label = "sandbox:red";
953 };
954
955 martinet {
956 gpios = <&gpio_a 2 0>;
957 label = "sandbox:green";
958 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200959
960 default_on {
961 gpios = <&gpio_a 5 0>;
962 label = "sandbox:default_on";
963 default-state = "on";
964 };
965
966 default_off {
967 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400968 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200969 default-state = "off";
970 };
Simon Glassd783eb32015-07-06 12:54:34 -0600971 };
972
Paul Doelle709f0372022-07-04 09:00:25 +0000973 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200974 gpios = <&gpio_a 7 0>;
975 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200976 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000977 hw_algo = "toggle";
978 always-running;
979 };
980
981 wdt-gpio-level {
982 gpios = <&gpio_a 7 0>;
983 compatible = "linux,wdt-gpio";
984 hw_margin_ms = <100>;
985 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200986 always-running;
987 };
988
Stephen Warren62f2c902016-05-16 17:41:37 -0600989 mbox: mbox {
990 compatible = "sandbox,mbox";
991 #mbox-cells = <1>;
992 };
993
994 mbox-test {
995 compatible = "sandbox,mbox-test";
996 mboxes = <&mbox 100>, <&mbox 1>;
997 mbox-names = "other", "test";
998 };
999
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001000 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001001 #address-cells = <1>;
1002 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001003 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001004 cpu1: cpu@1 {
1005 device_type = "cpu";
1006 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001007 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001008 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001009 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001010 };
Mario Sixdea5df72018-08-06 10:23:44 +02001011
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001012 cpu2: cpu@2 {
1013 device_type = "cpu";
1014 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001015 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001016 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001017 };
Mario Sixdea5df72018-08-06 10:23:44 +02001018
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001019 cpu3: cpu@3 {
1020 device_type = "cpu";
1021 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001022 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001023 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001024 };
Mario Sixdea5df72018-08-06 10:23:44 +02001025 };
1026
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001027 chipid: chipid {
1028 compatible = "sandbox,soc";
1029 };
1030
Simon Glassc953aaf2018-12-10 10:37:34 -07001031 i2s: i2s {
1032 compatible = "sandbox,i2s";
1033 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001034 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001035 };
1036
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001037 nop-test_0 {
1038 compatible = "sandbox,nop_sandbox1";
1039 nop-test_1 {
1040 compatible = "sandbox,nop_sandbox2";
1041 bind = "True";
1042 };
1043 nop-test_2 {
1044 compatible = "sandbox,nop_sandbox2";
1045 bind = "False";
1046 };
1047 };
1048
Roger Quadrosb0679a72022-10-20 16:30:46 +03001049 memory-controller {
1050 compatible = "sandbox,memory";
1051 };
1052
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001053 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001054 #address-cells = <1>;
1055 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001056 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001057
1058 eth5_addr: mac-address@10 {
1059 reg = <0x10 6>;
1060 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001061 };
1062
Simon Glasse4fef742017-04-23 20:02:07 -06001063 mmc2 {
1064 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001065 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001066 };
1067
Simon Glassb255efc2022-04-24 23:31:24 -06001068 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001069 mmc1 {
1070 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001071 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001072 };
1073
Simon Glassb255efc2022-04-24 23:31:24 -06001074 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301075 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001076 compatible = "sandbox,mmc";
1077 };
1078
Simon Glassf1eba352022-10-20 18:23:20 -06001079 /* This is used for VBE VPL tests */
1080 mmc3 {
1081 status = "disabled";
1082 compatible = "sandbox,mmc";
1083 filename = "image.bin";
1084 non-removable;
1085 };
1086
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001087 /* This is used for bootstd bootmenu tests */
1088 mmc4 {
1089 status = "disabled";
1090 compatible = "sandbox,mmc";
1091 filename = "mmc4.img";
1092 };
1093
Simon Glassfff928c2023-08-24 13:55:41 -06001094 /* This is used for ChromiumOS tests */
1095 mmc5 {
1096 status = "disabled";
1097 compatible = "sandbox,mmc";
1098 filename = "mmc5.img";
1099 };
1100
Simon Glass53a68b32019-02-16 20:24:50 -07001101 pch {
1102 compatible = "sandbox,pch";
1103 };
1104
Tom Rini4a3ca482020-02-11 12:41:23 -05001105 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001106 compatible = "sandbox,pci";
1107 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001108 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001109 #address-cells = <3>;
1110 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001111 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001112 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001113 iommu-map = <0x0010 &iommu 0 1>;
1114 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001115 pci@0,0 {
1116 compatible = "pci-generic";
1117 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001118 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001119 };
Alex Margineanf1274432019-06-07 11:24:24 +03001120 pci@1,0 {
1121 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001122 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001123 reg = <0x02000814 0 0 0x80 0
1124 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001125 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001126 };
Simon Glass937bb472019-12-06 21:41:57 -07001127 p2sb-pci@2,0 {
1128 compatible = "sandbox,p2sb";
1129 reg = <0x02001010 0 0 0 0>;
1130 sandbox,emul = <&p2sb_emul>;
1131
1132 adder {
1133 intel,p2sb-port-id = <3>;
1134 compatible = "sandbox,adder";
1135 };
1136 };
Simon Glass8c501022019-12-06 21:41:54 -07001137 pci@1e,0 {
1138 compatible = "sandbox,pmc";
1139 reg = <0xf000 0 0 0 0>;
1140 sandbox,emul = <&pmc_emul1e>;
1141 acpi-base = <0x400>;
1142 gpe0-dwx-mask = <0xf>;
1143 gpe0-dwx-shift-base = <4>;
1144 gpe0-dw = <6 7 9>;
1145 gpe0-sts = <0x20>;
1146 gpe0-en = <0x30>;
1147 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001148 pci@1f,0 {
1149 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001150 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001151 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001152 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001153 };
1154 };
1155
Simon Glassb98ba4c2019-09-25 08:56:10 -06001156 pci-emul0 {
1157 compatible = "sandbox,pci-emul-parent";
1158 swap_case_emul0_0: emul0@0,0 {
1159 compatible = "sandbox,swap-case";
1160 };
1161 swap_case_emul0_1: emul0@1,0 {
1162 compatible = "sandbox,swap-case";
1163 use-ea;
1164 };
1165 swap_case_emul0_1f: emul0@1f,0 {
1166 compatible = "sandbox,swap-case";
1167 };
Simon Glass937bb472019-12-06 21:41:57 -07001168 p2sb_emul: emul@2,0 {
1169 compatible = "sandbox,p2sb-emul";
1170 };
Simon Glass8c501022019-12-06 21:41:54 -07001171 pmc_emul1e: emul@1e,0 {
1172 compatible = "sandbox,pmc-emul";
1173 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001174 };
1175
Tom Rini4a3ca482020-02-11 12:41:23 -05001176 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001177 compatible = "sandbox,pci";
1178 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001179 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001180 #address-cells = <3>;
1181 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001182 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001183 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001184 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001185 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001186 0x0c 0x00 0x1234 0x5678
1187 0x10 0x00 0x1234 0x5678>;
1188 pci@10,0 {
1189 reg = <0x8000 0 0 0 0>;
1190 };
Bin Meng408e5902018-08-03 01:14:41 -07001191 };
1192
Tom Rini4a3ca482020-02-11 12:41:23 -05001193 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001194 compatible = "sandbox,pci";
1195 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001196 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001197 #address-cells = <3>;
1198 #size-cells = <2>;
1199 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1200 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1201 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1202 pci@1f,0 {
1203 compatible = "pci-generic";
1204 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001205 sandbox,emul = <&swap_case_emul2_1f>;
1206 };
1207 };
1208
1209 pci-emul2 {
1210 compatible = "sandbox,pci-emul-parent";
1211 swap_case_emul2_1f: emul2@1f,0 {
1212 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001213 };
1214 };
1215
Ramon Friedc64f19b2019-04-27 11:15:23 +03001216 pci_ep: pci_ep {
1217 compatible = "sandbox,pci_ep";
1218 };
1219
Simon Glass9c433fe2017-04-23 20:10:44 -06001220 probing {
1221 compatible = "simple-bus";
1222 test1 {
1223 compatible = "denx,u-boot-probe-test";
1224 };
1225
1226 test2 {
1227 compatible = "denx,u-boot-probe-test";
1228 };
1229
1230 test3 {
1231 compatible = "denx,u-boot-probe-test";
1232 };
1233
1234 test4 {
1235 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001236 first-syscon = <&syscon0>;
1237 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001238 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001239 };
1240 };
1241
Stephen Warren92c67fa2016-07-13 13:45:31 -06001242 pwrdom: power-domain {
1243 compatible = "sandbox,power-domain";
1244 #power-domain-cells = <1>;
1245 };
1246
1247 power-domain-test {
1248 compatible = "sandbox,power-domain-test";
1249 power-domains = <&pwrdom 2>;
1250 };
1251
Simon Glass5620cf82018-10-01 12:22:40 -06001252 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001253 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001254 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001255 pinctrl-names = "default";
1256 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001257 };
1258
1259 pwm2 {
1260 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001261 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001262 };
1263
Simon Glass3d355e62015-07-06 12:54:31 -06001264 ram {
1265 compatible = "sandbox,ram";
1266 };
1267
Simon Glassd860f222015-07-06 12:54:29 -06001268 reset@0 {
1269 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001270 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001271 };
1272
1273 reset@1 {
1274 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001275 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001276 };
1277
Stephen Warren6488e642016-06-17 09:43:59 -06001278 resetc: reset-ctl {
1279 compatible = "sandbox,reset-ctl";
1280 #reset-cells = <1>;
1281 };
1282
1283 reset-ctl-test {
1284 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001285 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1286 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001287 };
1288
Sughosh Ganu23e37512019-12-28 23:58:31 +05301289 rng {
1290 compatible = "sandbox,sandbox-rng";
1291 };
1292
Nishanth Menonedf85812015-09-17 15:42:41 -05001293 rproc_1: rproc@1 {
1294 compatible = "sandbox,test-processor";
1295 remoteproc-name = "remoteproc-test-dev1";
1296 };
1297
1298 rproc_2: rproc@2 {
1299 compatible = "sandbox,test-processor";
1300 internal-memory-mapped;
1301 remoteproc-name = "remoteproc-test-dev2";
1302 };
1303
Simon Glass5620cf82018-10-01 12:22:40 -06001304 panel {
1305 compatible = "simple-panel";
1306 backlight = <&backlight 0 100>;
1307 };
1308
Simon Glass509f32e2022-09-21 16:21:47 +02001309 scsi {
1310 compatible = "sandbox,scsi";
1311 sandbox,filepath = "scsi.img";
1312 };
1313
Ramon Fried26ed32e2018-07-02 02:57:59 +03001314 smem@0 {
1315 compatible = "sandbox,smem";
1316 };
1317
Simon Glass76072ac2018-12-10 10:37:36 -07001318 sound {
1319 compatible = "sandbox,sound";
1320 cpu {
1321 sound-dai = <&i2s 0>;
1322 };
1323
1324 codec {
1325 sound-dai = <&audio 0>;
1326 };
1327 };
1328
Simon Glass25348a42014-10-13 23:42:11 -06001329 spi@0 {
1330 #address-cells = <1>;
1331 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001332 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001333 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001334 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001335 pinctrl-names = "default";
1336 pinctrl-0 = <&pinmux_spi0_pins>;
1337
Simon Glass25348a42014-10-13 23:42:11 -06001338 spi.bin@0 {
1339 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001340 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001341 spi-max-frequency = <40000000>;
1342 sandbox,filename = "spi.bin";
1343 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001344 spi.bin@1 {
1345 reg = <1>;
1346 compatible = "spansion,m25p16", "jedec,spi-nor";
1347 spi-max-frequency = <50000000>;
1348 sandbox,filename = "spi.bin";
1349 spi-cpol;
1350 spi-cpha;
1351 };
Simon Glass25348a42014-10-13 23:42:11 -06001352 };
1353
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001354 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001355 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001356 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001357 };
1358
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001359 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001360 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001361 reg = <0x20 5
1362 0x28 6
1363 0x30 7
1364 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001365 };
1366
Patrick Delaunayee010432019-03-07 09:57:13 +01001367 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001368 compatible = "simple-mfd", "syscon";
1369 reg = <0x40 5
1370 0x48 6
1371 0x50 7
1372 0x58 8>;
1373 };
1374
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301375 syscon3: syscon@3 {
1376 compatible = "simple-mfd", "syscon";
1377 reg = <0x000100 0x10>;
1378
1379 muxcontroller0: a-mux-controller {
1380 compatible = "mmio-mux";
1381 #mux-control-cells = <1>;
1382
1383 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1384 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1385 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1386 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1387 u-boot,mux-autoprobe;
1388 };
1389 };
1390
1391 muxcontroller1: emul-mux-controller {
1392 compatible = "mux-emul";
1393 #mux-control-cells = <0>;
1394 u-boot,mux-autoprobe;
1395 idle-state = <0xabcd>;
1396 };
1397
Simon Glass791a17f2020-12-16 21:20:27 -07001398 testfdtm0 {
1399 compatible = "denx,u-boot-fdtm-test";
1400 };
1401
1402 testfdtm1: testfdtm1 {
1403 compatible = "denx,u-boot-fdtm-test";
1404 };
1405
1406 testfdtm2 {
1407 compatible = "denx,u-boot-fdtm-test";
1408 };
1409
Sean Anderson79d3bba2020-09-28 10:52:23 -04001410 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001411 compatible = "sandbox,timer";
1412 clock-frequency = <1000000>;
1413 };
1414
Sean Anderson79d3bba2020-09-28 10:52:23 -04001415 timer@1 {
1416 compatible = "sandbox,timer";
1417 sandbox,timebase-frequency-fallback;
1418 };
1419
Miquel Raynal80938c12018-05-15 11:57:27 +02001420 tpm2 {
1421 compatible = "sandbox,tpm2";
1422 };
1423
Simon Glasseef107e2023-02-21 06:24:51 -07001424 tpm {
1425 compatible = "google,sandbox-tpm";
1426 };
1427
Simon Glass5b968632015-05-22 15:42:15 -06001428 uart0: serial {
1429 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001430 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001431 pinctrl-names = "default";
1432 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001433 };
1434
Simon Glass31680482015-03-25 12:23:05 -06001435 usb_0: usb@0 {
1436 compatible = "sandbox,usb";
1437 status = "disabled";
1438 hub {
1439 compatible = "sandbox,usb-hub";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1442 flash-stick {
1443 reg = <0>;
1444 compatible = "sandbox,usb-flash";
1445 };
1446 };
1447 };
1448
1449 usb_1: usb@1 {
1450 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001451 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001452 hub {
1453 compatible = "usb-hub";
1454 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001455 #address-cells = <1>;
1456 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001457 hub-emul {
1458 compatible = "sandbox,usb-hub";
1459 #address-cells = <1>;
1460 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001461 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001462 reg = <0>;
1463 compatible = "sandbox,usb-flash";
1464 sandbox,filepath = "testflash.bin";
1465 };
1466
Simon Glass4700fe52015-11-08 23:48:01 -07001467 flash-stick@1 {
1468 reg = <1>;
1469 compatible = "sandbox,usb-flash";
1470 sandbox,filepath = "testflash1.bin";
1471 };
1472
1473 flash-stick@2 {
1474 reg = <2>;
1475 compatible = "sandbox,usb-flash";
1476 sandbox,filepath = "testflash2.bin";
1477 };
1478
Simon Glassc0ccc722015-11-08 23:48:08 -07001479 keyb@3 {
1480 reg = <3>;
1481 compatible = "sandbox,usb-keyb";
1482 };
1483
Simon Glass31680482015-03-25 12:23:05 -06001484 };
Michael Walle7c961322020-06-02 01:47:07 +02001485
1486 usbstor@1 {
1487 reg = <1>;
1488 };
1489 usbstor@3 {
1490 reg = <3>;
1491 };
Simon Glass31680482015-03-25 12:23:05 -06001492 };
1493 };
1494
1495 usb_2: usb@2 {
1496 compatible = "sandbox,usb";
1497 status = "disabled";
1498 };
1499
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001500 spmi: spmi@0 {
1501 compatible = "sandbox,spmi";
1502 #address-cells = <0x1>;
1503 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001504 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001505 pm8916@0 {
1506 compatible = "qcom,spmi-pmic";
1507 reg = <0x0 0x1>;
1508 #address-cells = <0x1>;
1509 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001510 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001511
1512 spmi_gpios: gpios@c000 {
1513 compatible = "qcom,pm8916-gpio";
1514 reg = <0xc000 0x400>;
1515 gpio-controller;
1516 gpio-count = <4>;
1517 #gpio-cells = <2>;
1518 gpio-bank-name="spmi";
1519 };
1520 };
1521 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001522
1523 wdt0: wdt@0 {
1524 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001525 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001526 };
Rob Clarka471b672018-01-10 11:33:30 +01001527
Mario Six95922152018-08-09 14:51:19 +02001528 axi: axi@0 {
1529 compatible = "sandbox,axi";
1530 #address-cells = <0x1>;
1531 #size-cells = <0x1>;
1532 store@0 {
1533 compatible = "sandbox,sandbox_store";
1534 reg = <0x0 0x400>;
1535 };
1536 };
1537
Rob Clarka471b672018-01-10 11:33:30 +01001538 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001539 #address-cells = <1>;
1540 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001541 setting = "sunrise ohoka";
1542 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001543 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001544 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001545 chosen-test {
1546 compatible = "denx,u-boot-fdt-test";
1547 reg = <9 1>;
1548 };
1549 };
Mario Six35616ef2018-03-12 14:53:33 +01001550
1551 translation-test@8000 {
1552 compatible = "simple-bus";
1553 reg = <0x8000 0x4000>;
1554
1555 #address-cells = <0x2>;
1556 #size-cells = <0x1>;
1557
1558 ranges = <0 0x0 0x8000 0x1000
1559 1 0x100 0x9000 0x1000
1560 2 0x200 0xA000 0x1000
1561 3 0x300 0xB000 0x1000
1562 >;
1563
Fabien Dessenne22236e02019-05-31 15:11:30 +02001564 dma-ranges = <0 0x000 0x10000000 0x1000
1565 1 0x100 0x20000000 0x1000
1566 >;
1567
Mario Six35616ef2018-03-12 14:53:33 +01001568 dev@0,0 {
1569 compatible = "denx,u-boot-fdt-dummy";
1570 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001571 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001572 };
1573
1574 dev@1,100 {
1575 compatible = "denx,u-boot-fdt-dummy";
1576 reg = <1 0x100 0x1000>;
1577
1578 };
1579
1580 dev@2,200 {
1581 compatible = "denx,u-boot-fdt-dummy";
1582 reg = <2 0x200 0x1000>;
1583 };
1584
1585
1586 noxlatebus@3,300 {
1587 compatible = "simple-bus";
1588 reg = <3 0x300 0x1000>;
1589
1590 #address-cells = <0x1>;
1591 #size-cells = <0x0>;
1592
1593 dev@42 {
1594 compatible = "denx,u-boot-fdt-dummy";
1595 reg = <0x42>;
1596 };
1597 };
1598 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001599
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001600 ofnode-foreach {
1601 compatible = "foreach";
1602
1603 first {
1604 prop1 = <1>;
1605 prop2 = <2>;
1606 };
1607
1608 second {
1609 prop1 = <1>;
1610 prop2 = <2>;
1611 };
1612 };
1613
Mario Six02ad6fb2018-09-27 09:19:31 +02001614 osd {
1615 compatible = "sandbox,sandbox_osd";
1616 };
Tom Rinib93eea72018-09-30 18:16:51 -04001617
Jens Wiklander86afaa62018-09-25 16:40:16 +02001618 sandbox_tee {
1619 compatible = "sandbox,tee";
1620 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001621
1622 sandbox_virtio1 {
1623 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001624 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001625 };
1626
1627 sandbox_virtio2 {
1628 compatible = "sandbox,virtio2";
1629 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001630
Simon Glass8de5a542023-01-17 10:47:51 -07001631 sandbox-virtio-blk {
1632 compatible = "sandbox,virtio1";
1633 virtio-type = <2>; /* block */
1634 };
1635
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001636 sandbox_scmi {
1637 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001638 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001639 resets = <&reset_scmi 3>;
1640 regul0-supply = <&regul0_scmi>;
1641 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001642 };
1643
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001644 pinctrl {
1645 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001646
Sean Anderson3438e3b2020-09-14 11:01:57 -04001647 pinctrl-names = "default", "alternate";
1648 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1649 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001650
Sean Anderson3438e3b2020-09-14 11:01:57 -04001651 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001652 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001653 pins = "P5";
1654 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001655 bias-pull-up;
1656 input-disable;
1657 };
1658 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001659 pins = "P6";
1660 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001661 output-high;
1662 drive-open-drain;
1663 };
1664 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001665 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001666 bias-pull-down;
1667 input-enable;
1668 };
1669 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001670 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001671 bias-disable;
1672 };
1673 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001674
1675 pinctrl_i2c: i2c {
1676 groups {
1677 groups = "I2C_UART";
1678 function = "I2C";
1679 };
1680
1681 pins {
1682 pins = "P0", "P1";
1683 drive-open-drain;
1684 };
1685 };
1686
1687 pinctrl_i2s: i2s {
1688 groups = "SPI_I2S";
1689 function = "I2S";
1690 };
1691
1692 pinctrl_spi: spi {
1693 groups = "SPI_I2S";
1694 function = "SPI";
1695
1696 cs {
1697 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1698 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1699 };
1700 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001701 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001702
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001703 pinctrl-single-no-width {
1704 compatible = "pinctrl-single";
1705 reg = <0x0000 0x238>;
1706 #pinctrl-cells = <1>;
1707 pinctrl-single,function-mask = <0x7f>;
1708 };
1709
1710 pinctrl-single-pins {
1711 compatible = "pinctrl-single";
1712 reg = <0x0000 0x238>;
1713 #pinctrl-cells = <1>;
1714 pinctrl-single,register-width = <32>;
1715 pinctrl-single,function-mask = <0x7f>;
1716
1717 pinmux_pwm_pins: pinmux_pwm_pins {
1718 pinctrl-single,pins = < 0x48 0x06 >;
1719 };
1720
1721 pinmux_spi0_pins: pinmux_spi0_pins {
1722 pinctrl-single,pins = <
1723 0x190 0x0c
1724 0x194 0x0c
1725 0x198 0x23
1726 0x19c 0x0c
1727 >;
1728 };
1729
1730 pinmux_uart0_pins: pinmux_uart0_pins {
1731 pinctrl-single,pins = <
1732 0x70 0x30
1733 0x74 0x00
1734 >;
1735 };
1736 };
1737
1738 pinctrl-single-bits {
1739 compatible = "pinctrl-single";
1740 reg = <0x0000 0x50>;
1741 #pinctrl-cells = <2>;
1742 pinctrl-single,bit-per-mux;
1743 pinctrl-single,register-width = <32>;
1744 pinctrl-single,function-mask = <0xf>;
1745
1746 pinmux_i2c0_pins: pinmux_i2c0_pins {
1747 pinctrl-single,bits = <
1748 0x10 0x00002200 0x0000ff00
1749 >;
1750 };
1751
1752 pinmux_lcd_pins: pinmux_lcd_pins {
1753 pinctrl-single,bits = <
1754 0x40 0x22222200 0xffffff00
1755 0x44 0x22222222 0xffffffff
1756 0x48 0x00000022 0x000000ff
1757 0x48 0x02000000 0x0f000000
1758 0x4c 0x02000022 0x0f0000ff
1759 >;
1760 };
1761 };
1762
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001763 hwspinlock@0 {
1764 compatible = "sandbox,hwspinlock";
1765 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001766
1767 dma: dma {
1768 compatible = "sandbox,dma";
1769 #dma-cells = <1>;
1770
1771 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1772 dma-names = "m2m", "tx0", "rx0";
1773 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001774
Alex Marginean0649be52019-07-12 10:13:53 +03001775 /*
1776 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1777 * end of the test. If parent mdio is removed first, clean-up of the
1778 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1779 * active at the end of the test. That it turn doesn't allow the mdio
1780 * class to be destroyed, triggering an error.
1781 */
1782 mdio-mux-test {
1783 compatible = "sandbox,mdio-mux";
1784 #address-cells = <1>;
1785 #size-cells = <0>;
1786 mdio-parent-bus = <&mdio>;
1787
1788 mdio-ch-test@0 {
1789 reg = <0>;
1790 };
1791 mdio-ch-test@1 {
1792 reg = <1>;
1793 };
1794 };
1795
1796 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001797 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001798 #address-cells = <1>;
1799 #size-cells = <0>;
1800
1801 ethphy1: ethernet-phy@1 {
1802 reg = <1>;
1803 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001804 };
Sean Andersonb7860542020-06-24 06:41:12 -04001805
1806 pm-bus-test {
1807 compatible = "simple-pm-bus";
1808 clocks = <&clk_sandbox 4>;
1809 power-domains = <&pwrdom 1>;
1810 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001811
1812 resetc2: syscon-reset {
1813 compatible = "syscon-reset";
1814 #reset-cells = <1>;
1815 regmap = <&syscon0>;
1816 offset = <1>;
1817 mask = <0x27FFFFFF>;
1818 assert-high = <0>;
1819 };
1820
1821 syscon-reset-test {
1822 compatible = "sandbox,misc_sandbox";
1823 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1824 reset-names = "valid", "no_mask", "out_of_range";
1825 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301826
Simon Glass458b66a2020-11-05 06:32:05 -07001827 sysinfo {
1828 compatible = "sandbox,sysinfo-sandbox";
1829 };
1830
Sean Anderson1c830672021-04-20 10:50:58 -04001831 sysinfo-gpio {
1832 compatible = "gpio-sysinfo";
1833 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1834 revisions = <19>, <5>;
1835 names = "rev_a", "foo";
1836 };
1837
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301838 some_regmapped-bus {
1839 #address-cells = <0x1>;
1840 #size-cells = <0x1>;
1841
1842 ranges = <0x0 0x0 0x10>;
1843 compatible = "simple-bus";
1844
1845 regmap-test_0 {
1846 reg = <0 0x10>;
1847 compatible = "sandbox,regmap_test";
1848 };
1849 };
Robert Marko9cf87122022-09-06 13:30:35 +02001850
1851 thermal {
1852 compatible = "sandbox,thermal";
1853 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301854
1855 fwu-mdata {
1856 compatible = "u-boot,fwu-mdata-gpt";
1857 fwu-mdata-store = <&mmc0>;
1858 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001859
1860 nvmxip-qspi1@08000000 {
1861 compatible = "nvmxip,qspi";
1862 reg = <0x08000000 0x00200000>;
1863 lba_shift = <9>;
1864 lba = <4096>;
1865 };
1866
1867 nvmxip-qspi2@08200000 {
1868 compatible = "nvmxip,qspi";
1869 reg = <0x08200000 0x00100000>;
1870 lba_shift = <9>;
1871 lba = <2048>;
1872 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001873
1874 extcon {
1875 compatible = "sandbox,extcon";
1876 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001877
1878 arm-ffa-emul {
1879 compatible = "sandbox,arm-ffa-emul";
1880
1881 sandbox-arm-ffa {
1882 compatible = "sandbox,arm-ffa";
1883 };
1884 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001885};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001886
1887#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001888#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001889
1890#ifdef CONFIG_SANDBOX_VPL
1891#include "sandbox_vpl.dtsi"
1892#endif
Simon Glass61300722023-06-01 10:23:01 -06001893
1894#include "cedit.dtsi"