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Vikas Manocha1b51c932016-02-11 15:47:20 -08001/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02002 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha1b51c932016-02-11 15:47:20 -08004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
Patrice Chotard789ee0e2017-10-23 09:53:58 +02007
Vikas Manocha1b51c932016-02-11 15:47:20 -08008#include <common.h>
Vikas Manochadaaeaab2017-02-12 10:25:45 -08009#include <clk-uclass.h>
10#include <dm.h>
Patrice Chotard03f10a12017-11-15 13:14:51 +010011#include <stm32_rcc.h>
Patrice Chotard22768d52017-11-15 13:14:44 +010012
Vikas Manocha1b51c932016-02-11 15:47:20 -080013#include <asm/io.h>
Vikas Manocha1b51c932016-02-11 15:47:20 -080014#include <asm/arch/stm32.h>
Patrice Chotard22768d52017-11-15 13:14:44 +010015#include <asm/arch/stm32_pwr.h>
Vikas Manocha1b51c932016-02-11 15:47:20 -080016
Patrice Chotard7bdf9712017-07-18 09:29:05 +020017#include <dt-bindings/mfd/stm32f7-rcc.h>
18
Michael Kurzc204fb72017-01-22 16:04:24 +010019#define RCC_CR_HSION BIT(0)
20#define RCC_CR_HSEON BIT(16)
21#define RCC_CR_HSERDY BIT(17)
22#define RCC_CR_HSEBYP BIT(18)
23#define RCC_CR_CSSON BIT(19)
24#define RCC_CR_PLLON BIT(24)
25#define RCC_CR_PLLRDY BIT(25)
Patrice Chotard369d4832017-11-15 13:14:52 +010026#define RCC_CR_PLLSAION BIT(28)
27#define RCC_CR_PLLSAIRDY BIT(29)
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090028
Michael Kurzc204fb72017-01-22 16:04:24 +010029#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
30#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
31#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
32#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
33#define RCC_PLLCFGR_PLLSRC BIT(22)
34#define RCC_PLLCFGR_PLLM_SHIFT 0
35#define RCC_PLLCFGR_PLLN_SHIFT 6
36#define RCC_PLLCFGR_PLLP_SHIFT 16
37#define RCC_PLLCFGR_PLLQ_SHIFT 24
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090038
Michael Kurzc204fb72017-01-22 16:04:24 +010039#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
40#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
41#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
42#define RCC_CFGR_SW0 BIT(0)
43#define RCC_CFGR_SW1 BIT(1)
44#define RCC_CFGR_SW_MASK GENMASK(1, 0)
45#define RCC_CFGR_SW_HSI 0
46#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
47#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
48#define RCC_CFGR_SWS0 BIT(2)
49#define RCC_CFGR_SWS1 BIT(3)
50#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
51#define RCC_CFGR_SWS_HSI 0
52#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
53#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
54#define RCC_CFGR_HPRE_SHIFT 4
55#define RCC_CFGR_PPRE1_SHIFT 10
56#define RCC_CFGR_PPRE2_SHIFT 13
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090057
Patrice Chotard9490aca2018-02-08 17:20:46 +010058#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
59#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
Patrice Chotard8aca2d12018-02-08 17:20:48 +010060#define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
61#define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
Patrice Chotard369d4832017-11-15 13:14:52 +010062#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
63#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
Patrice Chotard8aca2d12018-02-08 17:20:48 +010064#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
65#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
Patrice Chotardd5d36552018-01-19 18:02:40 +010066#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
Patrice Chotard369d4832017-11-15 13:14:52 +010067#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
Patrice Chotardff7b11e2018-02-08 17:20:49 +010068#define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
Patrice Chotard369d4832017-11-15 13:14:52 +010069
Patrice Chotardef772872018-02-07 10:44:46 +010070#define RCC_DCKCFGRX_TIMPRE BIT(24)
Patrice Chotard369d4832017-11-15 13:14:52 +010071#define RCC_DCKCFGRX_CK48MSEL BIT(27)
72#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
73#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
74
Patrice Chotardff7b11e2018-02-08 17:20:49 +010075#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
76#define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
77#define RCC_DCKCFGR_PLLSAIDIVR_2 0
78
Patrice Chotard06fc6482017-11-15 13:14:49 +010079/*
80 * RCC AHB1ENR specific definitions
81 */
82#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
83#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
84#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
85
86/*
87 * RCC APB1ENR specific definitions
88 */
89#define RCC_APB1ENR_TIM2EN BIT(0)
90#define RCC_APB1ENR_PWREN BIT(28)
91
92/*
93 * RCC APB2ENR specific definitions
94 */
95#define RCC_APB2ENR_SYSCFGEN BIT(14)
Patrice Chotarde2d564e2018-01-18 14:10:05 +010096#define RCC_APB2ENR_SAI1EN BIT(22)
Patrice Chotard06fc6482017-11-15 13:14:49 +010097
Patrice Chotard8aca2d12018-02-08 17:20:48 +010098enum pllsai_div {
99 PLLSAIP,
100 PLLSAIQ,
101 PLLSAIR,
102};
103
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100104static const struct stm32_clk_info stm32f4_clk_info = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100105 /* 180 MHz */
106 .sys_pll_psc = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100107 .pll_n = 360,
108 .pll_p = 2,
109 .pll_q = 8,
110 .ahb_psc = AHB_PSC_1,
111 .apb1_psc = APB_PSC_4,
112 .apb2_psc = APB_PSC_2,
113 },
114 .has_overdrive = false,
Patrice Chotard369d4832017-11-15 13:14:52 +0100115 .v2 = false,
Patrice Chotard1509d662017-11-15 13:14:47 +0100116};
117
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100118static const struct stm32_clk_info stm32f7_clk_info = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100119 /* 200 MHz */
120 .sys_pll_psc = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100121 .pll_n = 400,
122 .pll_p = 2,
123 .pll_q = 8,
124 .ahb_psc = AHB_PSC_1,
125 .apb1_psc = APB_PSC_4,
126 .apb2_psc = APB_PSC_2,
127 },
128 .has_overdrive = true,
Patrice Chotard369d4832017-11-15 13:14:52 +0100129 .v2 = true,
Patrice Chotard1509d662017-11-15 13:14:47 +0100130};
131
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200132struct stm32_clk {
133 struct stm32_rcc_regs *base;
Patrice Chotard22768d52017-11-15 13:14:44 +0100134 struct stm32_pwr_regs *pwr_regs;
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100135 struct stm32_clk_info info;
136 unsigned long hse_rate;
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900137};
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900138
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100139#ifdef CONFIG_VIDEO_STM32
140static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
141#endif
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100142static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
143
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200144static int configure_clocks(struct udevice *dev)
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900145{
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200146 struct stm32_clk *priv = dev_get_priv(dev);
147 struct stm32_rcc_regs *regs = priv->base;
Patrice Chotard22768d52017-11-15 13:14:44 +0100148 struct stm32_pwr_regs *pwr = priv->pwr_regs;
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100149 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200150
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900151 /* Reset RCC configuration */
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200152 setbits_le32(&regs->cr, RCC_CR_HSION);
153 writel(0, &regs->cfgr); /* Reset CFGR */
154 clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
Patrice Chotard369d4832017-11-15 13:14:52 +0100155 | RCC_CR_PLLON | RCC_CR_PLLSAION));
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200156 writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
157 clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
158 writel(0, &regs->cir); /* Disable all interrupts */
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900159
160 /* Configure for HSE+PLL operation */
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200161 setbits_le32(&regs->cr, RCC_CR_HSEON);
162 while (!(readl(&regs->cr) & RCC_CR_HSERDY))
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900163 ;
164
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200165 setbits_le32(&regs->cfgr, ((
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100166 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
167 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
168 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900169
170 /* Configure the main PLL */
Patrice Chotardb6653f62017-10-26 13:23:19 +0200171 setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
172 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100173 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
Patrice Chotardb6653f62017-10-26 13:23:19 +0200174 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100175 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
Patrice Chotardb6653f62017-10-26 13:23:19 +0200176 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
Patrice Chotardb6653f62017-10-26 13:23:19 +0200178 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100179 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900180
Patrice Chotardcb15d282018-02-08 17:20:47 +0100181 /* configure SDMMC clock */
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100182 if (priv->info.v2) { /*stm32f7 case */
Patrice Chotardcb15d282018-02-08 17:20:47 +0100183 /* select PLLQ as 48MHz clock source */
184 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
Patrice Chotard369d4832017-11-15 13:14:52 +0100185
186 /* select 48MHz as SDMMC1 clock source */
187 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
188
189 /* select 48MHz as SDMMC2 clock source */
190 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
191 } else { /* stm32f4 case */
Patrice Chotardcb15d282018-02-08 17:20:47 +0100192 /* select PLLQ as 48MHz clock source */
193 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
Patrice Chotard369d4832017-11-15 13:14:52 +0100194
195 /* select 48MHz as SDMMC1 clock source */
196 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
197 }
198
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100199#ifdef CONFIG_VIDEO_STM32
200 /*
201 * Configure the SAI PLL to generate LTDC pixel clock
202 */
203 clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
204 RCC_PLLSAICFGR_PLLSAIR_3);
205 clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
206 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
207
208 clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
209 RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
210#endif
Patrice Chotardcb15d282018-02-08 17:20:47 +0100211 /* Enable the main PLL */
212 setbits_le32(&regs->cr, RCC_CR_PLLON);
213 while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
Patrice Chotard369d4832017-11-15 13:14:52 +0100214 ;
215
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100216#ifdef CONFIG_VIDEO_STM32
217/* Enable the SAI PLL */
218 setbits_le32(&regs->cr, RCC_CR_PLLSAION);
219 while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
220 ;
221#endif
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200222 setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
Patrice Chotard1509d662017-11-15 13:14:47 +0100223
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100224 if (priv->info.has_overdrive) {
Patrice Chotard1509d662017-11-15 13:14:47 +0100225 /*
226 * Enable high performance mode
227 * System frequency up to 200 MHz
228 */
229 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
230 /* Infinite wait! */
231 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
232 ;
233 /* Enable the Over-drive switch */
234 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
235 /* Infinite wait! */
236 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
237 ;
238 }
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900239
240 stm32_flash_latency_cfg(5);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200241 clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
242 setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900243
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200244 while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900245 RCC_CFGR_SWS_PLL)
246 ;
247
Patrice Chotarde2d564e2018-01-18 14:10:05 +0100248#ifdef CONFIG_ETH_DESIGNWARE
249 /* gate the SYSCFG clock, needed to set RMII ethernet interface */
250 setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
251#endif
252
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900253 return 0;
254}
255
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100256static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
Patrice Chotard369d4832017-11-15 13:14:52 +0100257{
258 struct stm32_rcc_regs *regs = priv->base;
Patrice Chotard369d4832017-11-15 13:14:52 +0100259
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100260 if (priv->info.v2) /*stm32f7 case */
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100261 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
Patrice Chotard369d4832017-11-15 13:14:52 +0100262 else
Patrice Chotard369d4832017-11-15 13:14:52 +0100263
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100264 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
265}
266
267static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
268{
269 struct stm32_rcc_regs *regs = priv->base;
270 u16 pllm, pllsain;
271
272 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
273 pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
274 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
275
276 return ((priv->hse_rate / pllm) * pllsain);
277}
278
279static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
280 enum pllsai_div output)
281{
282 struct stm32_rcc_regs *regs = priv->base;
283 u16 pll_div_output;
284
285 switch (output) {
286 case PLLSAIP:
287 pll_div_output = ((((readl(&regs->pllsaicfgr)
288 & RCC_PLLSAICFGR_PLLSAIP_MASK)
289 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
290 break;
291 case PLLSAIQ:
292 pll_div_output = (readl(&regs->pllsaicfgr)
293 & RCC_PLLSAICFGR_PLLSAIQ_MASK)
294 >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
295 break;
296 case PLLSAIR:
297 pll_div_output = (readl(&regs->pllsaicfgr)
298 & RCC_PLLSAICFGR_PLLSAIR_MASK)
299 >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
300 break;
301 default:
302 pr_err("incorrect PLLSAI output %d\n", output);
303 return -EINVAL;
Patrice Chotard369d4832017-11-15 13:14:52 +0100304 }
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100305
306 return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
Patrice Chotard369d4832017-11-15 13:14:52 +0100307}
308
Patrice Chotardef772872018-02-07 10:44:46 +0100309static bool stm32_get_timpre(struct stm32_clk *priv)
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200310{
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200311 struct stm32_rcc_regs *regs = priv->base;
Patrice Chotardef772872018-02-07 10:44:46 +0100312 u32 val;
313
314 if (priv->info.v2) /*stm32f7 case */
315 val = readl(&regs->dckcfgr2);
316 else
317 val = readl(&regs->dckcfgr);
318 /* get timer prescaler */
319 return !!(val & RCC_DCKCFGRX_TIMPRE);
320}
321
322static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
323{
324 u8 shift;
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200325 /* Prescaler table lookups for clock computation */
326 u8 ahb_psc_table[16] = {
327 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
328 };
Patrice Chotardef772872018-02-07 10:44:46 +0100329
330 shift = ahb_psc_table[(
331 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
332 >> RCC_CFGR_HPRE_SHIFT)];
333
334 return sysclk >> shift;
335};
336
337static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
338{
339 /* Prescaler table lookups for clock computation */
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200340 u8 apb_psc_table[8] = {
341 0, 0, 0, 0, 1, 2, 3, 4
342 };
343
Patrice Chotardef772872018-02-07 10:44:46 +0100344 if (apb == APB1)
345 return apb_psc_table[(
346 (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
347 >> RCC_CFGR_PPRE1_SHIFT)];
348 else /* APB2 */
349 return apb_psc_table[(
350 (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
351 >> RCC_CFGR_PPRE2_SHIFT)];
352};
353
354static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
355 enum apb apb)
356{
357 struct stm32_rcc_regs *regs = priv->base;
358 u8 shift = stm32_get_apb_shift(regs, apb);
359
360 if (stm32_get_timpre(priv))
361 /*
362 * if APB prescaler is configured to a
363 * division factor of 1, 2 or 4
364 */
365 switch (shift) {
366 case 0:
367 case 1:
368 case 2:
369 return stm32_get_hclk_rate(regs, sysclk);
370 default:
371 return (sysclk >> shift) * 4;
372 }
373 else
374 /*
375 * if APB prescaler is configured to a
376 * division factor of 1
377 */
378 if (shift == 0)
379 return sysclk;
380 else
381 return (sysclk >> shift) * 2;
382};
383
384static ulong stm32_clk_get_rate(struct clk *clk)
385{
386 struct stm32_clk *priv = dev_get_priv(clk->dev);
387 struct stm32_rcc_regs *regs = priv->base;
388 u32 sysclk = 0;
Patrice Chotard81d77652018-02-08 17:20:45 +0100389 u32 vco;
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100390 u32 sdmmcxsel_bit;
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100391 u32 saidivr;
392 u32 pllsai_rate;
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100393 u16 pllm, plln, pllp, pllq;
Patrice Chotardef772872018-02-07 10:44:46 +0100394
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200395 if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
396 RCC_CFGR_SWS_PLL) {
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200397 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
398 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
399 >> RCC_PLLCFGR_PLLN_SHIFT);
400 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
401 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100402 pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
403 >> RCC_PLLCFGR_PLLQ_SHIFT);
Patrice Chotard81d77652018-02-08 17:20:45 +0100404 vco = (priv->hse_rate / pllm) * plln;
405 sysclk = vco / pllp;
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200406 } else {
407 return -EINVAL;
408 }
409
410 switch (clk->id) {
411 /*
412 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
413 * AHB1, AHB2 and AHB3
414 */
415 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
Patrice Chotardef772872018-02-07 10:44:46 +0100416 return stm32_get_hclk_rate(regs, sysclk);
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200417 /* APB1 CLOCK */
418 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
Patrice Chotardef772872018-02-07 10:44:46 +0100419 /* For timer clock, an additionnal prescaler is used*/
420 switch (clk->id) {
421 case STM32F7_APB1_CLOCK(TIM2):
422 case STM32F7_APB1_CLOCK(TIM3):
423 case STM32F7_APB1_CLOCK(TIM4):
424 case STM32F7_APB1_CLOCK(TIM5):
425 case STM32F7_APB1_CLOCK(TIM6):
426 case STM32F7_APB1_CLOCK(TIM7):
427 case STM32F7_APB1_CLOCK(TIM12):
428 case STM32F7_APB1_CLOCK(TIM13):
429 case STM32F7_APB1_CLOCK(TIM14):
430 return stm32_get_timer_rate(priv, sysclk, APB1);
431 }
432 return (sysclk >> stm32_get_apb_shift(regs, APB1));
433
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200434 /* APB2 CLOCK */
Patrice Chotarde199c3a2018-02-08 17:20:51 +0100435 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100436 switch (clk->id) {
Patrice Chotard369d4832017-11-15 13:14:52 +0100437 /*
438 * particular case for SDMMC1 and SDMMC2 :
439 * 48Mhz source clock can be from main PLL or from
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100440 * PLLSAIP
Patrice Chotard369d4832017-11-15 13:14:52 +0100441 */
Patrice Chotard369d4832017-11-15 13:14:52 +0100442 case STM32F7_APB2_CLOCK(SDMMC1):
Patrice Chotard369d4832017-11-15 13:14:52 +0100443 case STM32F7_APB2_CLOCK(SDMMC2):
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100444 if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
445 sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
446 else
447 sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
448
449 if (readl(&regs->dckcfgr2) & sdmmcxsel_bit)
450 /* System clock is selected as SDMMC1 clock */
Patrice Chotard369d4832017-11-15 13:14:52 +0100451 return sysclk;
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100452 /*
453 * 48 MHz can be generated by either PLLSAIP
454 * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
455 */
456 if (stm32_clk_get_ck48msel(priv))
457 return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
Patrice Chotard369d4832017-11-15 13:14:52 +0100458 else
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100459 return (vco / pllq);
Patrice Chotard369d4832017-11-15 13:14:52 +0100460 break;
Patrice Chotardef772872018-02-07 10:44:46 +0100461
462 /* For timer clock, an additionnal prescaler is used*/
463 case STM32F7_APB2_CLOCK(TIM1):
464 case STM32F7_APB2_CLOCK(TIM8):
465 case STM32F7_APB2_CLOCK(TIM9):
466 case STM32F7_APB2_CLOCK(TIM10):
467 case STM32F7_APB2_CLOCK(TIM11):
468 return stm32_get_timer_rate(priv, sysclk, APB2);
469 break;
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100470
471 /* particular case for LTDC clock */
472 case STM32F7_APB2_CLOCK(LTDC):
473 saidivr = readl(&regs->dckcfgr);
474 saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
475 >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
476 pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
477
478 return pllsai_rate / pllsaidivr_table[saidivr];
Patrice Chotard369d4832017-11-15 13:14:52 +0100479 }
Patrice Chotardef772872018-02-07 10:44:46 +0100480 return (sysclk >> stm32_get_apb_shift(regs, APB2));
Patrice Chotard369d4832017-11-15 13:14:52 +0100481
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200482 default:
Masahiro Yamada81e10422017-09-16 14:10:41 +0900483 pr_err("clock index %ld out of range\n", clk->id);
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200484 return -EINVAL;
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200485 }
486}
487
Patrice Chotard24e85782018-01-29 18:14:14 +0100488static ulong stm32_set_rate(struct clk *clk, ulong rate)
489{
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100490#ifdef CONFIG_VIDEO_STM32
491 struct stm32_clk *priv = dev_get_priv(clk->dev);
492 struct stm32_rcc_regs *regs = priv->base;
493 u32 pllsair_rate, pllsai_vco_rate, current_rate;
494 u32 best_div, best_diff, diff;
495 u16 div;
496 u8 best_plldivr, best_pllsaidivr;
497 u8 i, j;
498 bool found = false;
499
500 /* Only set_rate for LTDC clock is implemented */
501 if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
502 pr_err("set_rate not implemented for clock index %ld\n",
503 clk->id);
504 return 0;
505 }
506
507 if (rate == stm32_clk_get_rate(clk))
508 /* already set to requested rate */
509 return rate;
510
511 /* get the current PLLSAIR output freq */
512 pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
513 best_div = pllsair_rate / rate;
514
515 /* look into pllsaidivr_table if this divider is available*/
516 for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
517 if (best_div == pllsaidivr_table[i]) {
518 /* set pll_saidivr with found value */
519 clrsetbits_le32(&regs->dckcfgr,
520 RCC_DCKCFGR_PLLSAIDIVR_MASK,
521 pllsaidivr_table[i]);
522 return rate;
523 }
524
525 /*
526 * As no pllsaidivr value is suitable to obtain requested freq,
527 * test all combination of pllsaidivr * pllsair and find the one
528 * which give freq closest to requested rate.
529 */
530
531 pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
532 best_diff = ULONG_MAX;
533 best_pllsaidivr = 0;
534 best_plldivr = 0;
535 /*
536 * start at index 2 of plldivr_table as divider value at index 0
537 * and 1 are 0)
538 */
539 for (i = 2; i < sizeof(plldivr_table); i++) {
540 for (j = 0; j < sizeof(pllsaidivr_table); j++) {
541 div = plldivr_table[i] * pllsaidivr_table[j];
542 current_rate = pllsai_vco_rate / div;
543 /* perfect combination is found ? */
544 if (current_rate == rate) {
545 best_pllsaidivr = j;
546 best_plldivr = i;
547 found = true;
548 break;
549 }
550
551 diff = (current_rate > rate) ?
552 current_rate - rate : rate - current_rate;
553
554 /* found a better combination ? */
555 if (diff < best_diff) {
556 best_diff = diff;
557 best_pllsaidivr = j;
558 best_plldivr = i;
559 }
560 }
561
562 if (found)
563 break;
564 }
565
566 /* Disable the SAI PLL */
567 clrbits_le32(&regs->cr, RCC_CR_PLLSAION);
568
569 /* set pll_saidivr with found value */
570 clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
571 best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
572
573 /* set pllsair with found value */
574 clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
575 plldivr_table[best_plldivr]
576 << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
577
578 /* Enable the SAI PLL */
579 setbits_le32(&regs->cr, RCC_CR_PLLSAION);
580 while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
581 ;
582
583 div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
584 return pllsai_vco_rate / div;
585#else
Patrice Chotard24e85782018-01-29 18:14:14 +0100586 return 0;
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100587#endif
Patrice Chotard24e85782018-01-29 18:14:14 +0100588}
589
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800590static int stm32_clk_enable(struct clk *clk)
591{
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200592 struct stm32_clk *priv = dev_get_priv(clk->dev);
593 struct stm32_rcc_regs *regs = priv->base;
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800594 u32 offset = clk->id / 32;
595 u32 bit_index = clk->id % 32;
596
597 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
598 __func__, clk->id, offset, bit_index);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200599 setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800600
601 return 0;
602}
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900603
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800604static int stm32_clk_probe(struct udevice *dev)
605{
Patrice Chotard22768d52017-11-15 13:14:44 +0100606 struct ofnode_phandle_args args;
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100607 struct udevice *fixed_clock_dev = NULL;
608 struct clk clk;
Patrice Chotard22768d52017-11-15 13:14:44 +0100609 int err;
610
Patrice Chotardd4f2d202017-11-15 13:14:48 +0100611 debug("%s\n", __func__);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200612
613 struct stm32_clk *priv = dev_get_priv(dev);
614 fdt_addr_t addr;
615
Patrice Chotard1509d662017-11-15 13:14:47 +0100616 addr = dev_read_addr(dev);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200617 if (addr == FDT_ADDR_T_NONE)
618 return -EINVAL;
619
620 priv->base = (struct stm32_rcc_regs *)addr;
Patrice Chotard03f10a12017-11-15 13:14:51 +0100621
622 switch (dev_get_driver_data(dev)) {
623 case STM32F4:
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100624 memcpy(&priv->info, &stm32f4_clk_info,
625 sizeof(struct stm32_clk_info));
Patrice Chotard03f10a12017-11-15 13:14:51 +0100626 break;
627 case STM32F7:
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100628 memcpy(&priv->info, &stm32f7_clk_info,
629 sizeof(struct stm32_clk_info));
Patrice Chotard03f10a12017-11-15 13:14:51 +0100630 break;
631 default:
632 return -EINVAL;
633 }
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200634
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100635 /* retrieve HSE frequency (external oscillator) */
636 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
637 &fixed_clock_dev);
638
639 if (err) {
640 pr_err("Can't find fixed clock (%d)", err);
641 return err;
642 }
643
644 err = clk_request(fixed_clock_dev, &clk);
645 if (err) {
646 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
647 err);
648 return err;
649 }
650
651 /*
652 * set pllm factor accordingly to the external oscillator
653 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
654 * freq at 1MHz
655 * if input PLL frequency is 25Mhz, divide it by 25
656 */
657 clk.id = 0;
658 priv->hse_rate = clk_get_rate(&clk);
659
660 if (priv->hse_rate < 1000000) {
661 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
662 priv->hse_rate);
663 return -EINVAL;
664 }
665
666 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
667
668 if (priv->info.has_overdrive) {
Patrice Chotard1509d662017-11-15 13:14:47 +0100669 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
670 &args);
671 if (err) {
672 debug("%s: can't find syscon device (%d)\n", __func__,
673 err);
674 return err;
675 }
Patrice Chotard22768d52017-11-15 13:14:44 +0100676
Patrice Chotard1509d662017-11-15 13:14:47 +0100677 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
678 }
Patrice Chotard22768d52017-11-15 13:14:44 +0100679
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200680 configure_clocks(dev);
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800681
682 return 0;
683}
684
Simon Glassb7ae2772017-05-18 20:09:40 -0600685static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800686{
687 debug("%s(clk=%p)\n", __func__, clk);
688
689 if (args->args_count != 2) {
690 debug("Invaild args_count: %d\n", args->args_count);
691 return -EINVAL;
692 }
693
694 if (args->args_count)
695 clk->id = args->args[1];
696 else
697 clk->id = 0;
698
699 return 0;
700}
701
702static struct clk_ops stm32_clk_ops = {
703 .of_xlate = stm32_clk_of_xlate,
704 .enable = stm32_clk_enable,
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200705 .get_rate = stm32_clk_get_rate,
Patrice Chotard24e85782018-01-29 18:14:14 +0100706 .set_rate = stm32_set_rate,
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800707};
708
Patrice Chotardd4f2d202017-11-15 13:14:48 +0100709U_BOOT_DRIVER(stm32fx_clk) = {
Patrice Chotard03f10a12017-11-15 13:14:51 +0100710 .name = "stm32fx_rcc_clock",
Patrice Chotardb323de52017-09-21 10:08:09 +0200711 .id = UCLASS_CLK,
Patrice Chotardb323de52017-09-21 10:08:09 +0200712 .ops = &stm32_clk_ops,
713 .probe = stm32_clk_probe,
714 .priv_auto_alloc_size = sizeof(struct stm32_clk),
715 .flags = DM_FLAG_PRE_RELOC,
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800716};