Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 1 | /* |
Patrice Chotard | 789ee0e | 2017-10-23 09:53:58 +0200 | [diff] [blame] | 2 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
| 3 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
Patrice Chotard | 789ee0e | 2017-10-23 09:53:58 +0200 | [diff] [blame] | 7 | |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 8 | #include <common.h> |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 9 | #include <clk-uclass.h> |
| 10 | #include <dm.h> |
Patrice Chotard | 03f10a1 | 2017-11-15 13:14:51 +0100 | [diff] [blame] | 11 | #include <stm32_rcc.h> |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 12 | |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 13 | #include <asm/io.h> |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 14 | #include <asm/arch/stm32.h> |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 15 | #include <asm/arch/stm32_pwr.h> |
Vikas Manocha | 1b51c93 | 2016-02-11 15:47:20 -0800 | [diff] [blame] | 16 | |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 17 | #include <dt-bindings/mfd/stm32f7-rcc.h> |
| 18 | |
Michael Kurz | c204fb7 | 2017-01-22 16:04:24 +0100 | [diff] [blame] | 19 | #define RCC_CR_HSION BIT(0) |
| 20 | #define RCC_CR_HSEON BIT(16) |
| 21 | #define RCC_CR_HSERDY BIT(17) |
| 22 | #define RCC_CR_HSEBYP BIT(18) |
| 23 | #define RCC_CR_CSSON BIT(19) |
| 24 | #define RCC_CR_PLLON BIT(24) |
| 25 | #define RCC_CR_PLLRDY BIT(25) |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 26 | #define RCC_CR_PLLSAION BIT(28) |
| 27 | #define RCC_CR_PLLSAIRDY BIT(29) |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 28 | |
Michael Kurz | c204fb7 | 2017-01-22 16:04:24 +0100 | [diff] [blame] | 29 | #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) |
| 30 | #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) |
| 31 | #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) |
| 32 | #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) |
| 33 | #define RCC_PLLCFGR_PLLSRC BIT(22) |
| 34 | #define RCC_PLLCFGR_PLLM_SHIFT 0 |
| 35 | #define RCC_PLLCFGR_PLLN_SHIFT 6 |
| 36 | #define RCC_PLLCFGR_PLLP_SHIFT 16 |
| 37 | #define RCC_PLLCFGR_PLLQ_SHIFT 24 |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 38 | |
Michael Kurz | c204fb7 | 2017-01-22 16:04:24 +0100 | [diff] [blame] | 39 | #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) |
| 40 | #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) |
| 41 | #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) |
| 42 | #define RCC_CFGR_SW0 BIT(0) |
| 43 | #define RCC_CFGR_SW1 BIT(1) |
| 44 | #define RCC_CFGR_SW_MASK GENMASK(1, 0) |
| 45 | #define RCC_CFGR_SW_HSI 0 |
| 46 | #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 |
| 47 | #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 |
| 48 | #define RCC_CFGR_SWS0 BIT(2) |
| 49 | #define RCC_CFGR_SWS1 BIT(3) |
| 50 | #define RCC_CFGR_SWS_MASK GENMASK(3, 2) |
| 51 | #define RCC_CFGR_SWS_HSI 0 |
| 52 | #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 |
| 53 | #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 |
| 54 | #define RCC_CFGR_HPRE_SHIFT 4 |
| 55 | #define RCC_CFGR_PPRE1_SHIFT 10 |
| 56 | #define RCC_CFGR_PPRE2_SHIFT 13 |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 57 | |
Patrice Chotard | 9490aca | 2018-02-08 17:20:46 +0100 | [diff] [blame] | 58 | #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6) |
| 59 | #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16) |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 60 | #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24) |
| 61 | #define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28) |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 62 | #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 |
| 63 | #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 64 | #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24 |
| 65 | #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28 |
Patrice Chotard | d5d3655 | 2018-01-19 18:02:40 +0100 | [diff] [blame] | 66 | #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 67 | #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) |
Patrice Chotard | ff7b11e | 2018-02-08 17:20:49 +0100 | [diff] [blame] | 68 | #define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28) |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 69 | |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 70 | #define RCC_DCKCFGRX_TIMPRE BIT(24) |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 71 | #define RCC_DCKCFGRX_CK48MSEL BIT(27) |
| 72 | #define RCC_DCKCFGRX_SDMMC1SEL BIT(28) |
| 73 | #define RCC_DCKCFGR2_SDMMC2SEL BIT(29) |
| 74 | |
Patrice Chotard | ff7b11e | 2018-02-08 17:20:49 +0100 | [diff] [blame] | 75 | #define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16 |
| 76 | #define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16) |
| 77 | #define RCC_DCKCFGR_PLLSAIDIVR_2 0 |
| 78 | |
Patrice Chotard | 06fc648 | 2017-11-15 13:14:49 +0100 | [diff] [blame] | 79 | /* |
| 80 | * RCC AHB1ENR specific definitions |
| 81 | */ |
| 82 | #define RCC_AHB1ENR_ETHMAC_EN BIT(25) |
| 83 | #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) |
| 84 | #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) |
| 85 | |
| 86 | /* |
| 87 | * RCC APB1ENR specific definitions |
| 88 | */ |
| 89 | #define RCC_APB1ENR_TIM2EN BIT(0) |
| 90 | #define RCC_APB1ENR_PWREN BIT(28) |
| 91 | |
| 92 | /* |
| 93 | * RCC APB2ENR specific definitions |
| 94 | */ |
| 95 | #define RCC_APB2ENR_SYSCFGEN BIT(14) |
Patrice Chotard | e2d564e | 2018-01-18 14:10:05 +0100 | [diff] [blame] | 96 | #define RCC_APB2ENR_SAI1EN BIT(22) |
Patrice Chotard | 06fc648 | 2017-11-15 13:14:49 +0100 | [diff] [blame] | 97 | |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 98 | enum pllsai_div { |
| 99 | PLLSAIP, |
| 100 | PLLSAIQ, |
| 101 | PLLSAIR, |
| 102 | }; |
| 103 | |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 104 | static const struct stm32_clk_info stm32f4_clk_info = { |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 105 | /* 180 MHz */ |
| 106 | .sys_pll_psc = { |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 107 | .pll_n = 360, |
| 108 | .pll_p = 2, |
| 109 | .pll_q = 8, |
| 110 | .ahb_psc = AHB_PSC_1, |
| 111 | .apb1_psc = APB_PSC_4, |
| 112 | .apb2_psc = APB_PSC_2, |
| 113 | }, |
| 114 | .has_overdrive = false, |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 115 | .v2 = false, |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 116 | }; |
| 117 | |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 118 | static const struct stm32_clk_info stm32f7_clk_info = { |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 119 | /* 200 MHz */ |
| 120 | .sys_pll_psc = { |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 121 | .pll_n = 400, |
| 122 | .pll_p = 2, |
| 123 | .pll_q = 8, |
| 124 | .ahb_psc = AHB_PSC_1, |
| 125 | .apb1_psc = APB_PSC_4, |
| 126 | .apb2_psc = APB_PSC_2, |
| 127 | }, |
| 128 | .has_overdrive = true, |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 129 | .v2 = true, |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 130 | }; |
| 131 | |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 132 | struct stm32_clk { |
| 133 | struct stm32_rcc_regs *base; |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 134 | struct stm32_pwr_regs *pwr_regs; |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 135 | struct stm32_clk_info info; |
| 136 | unsigned long hse_rate; |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 137 | }; |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 138 | |
Patrice Chotard | 2cd1ed1 | 2018-02-08 17:20:50 +0100 | [diff] [blame] | 139 | #ifdef CONFIG_VIDEO_STM32 |
| 140 | static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 }; |
| 141 | #endif |
Patrice Chotard | ff7b11e | 2018-02-08 17:20:49 +0100 | [diff] [blame] | 142 | static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 }; |
| 143 | |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 144 | static int configure_clocks(struct udevice *dev) |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 145 | { |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 146 | struct stm32_clk *priv = dev_get_priv(dev); |
| 147 | struct stm32_rcc_regs *regs = priv->base; |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 148 | struct stm32_pwr_regs *pwr = priv->pwr_regs; |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 149 | struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 150 | |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 151 | /* Reset RCC configuration */ |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 152 | setbits_le32(®s->cr, RCC_CR_HSION); |
| 153 | writel(0, ®s->cfgr); /* Reset CFGR */ |
| 154 | clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 155 | | RCC_CR_PLLON | RCC_CR_PLLSAION)); |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 156 | writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ |
| 157 | clrbits_le32(®s->cr, RCC_CR_HSEBYP); |
| 158 | writel(0, ®s->cir); /* Disable all interrupts */ |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 159 | |
| 160 | /* Configure for HSE+PLL operation */ |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 161 | setbits_le32(®s->cr, RCC_CR_HSEON); |
| 162 | while (!(readl(®s->cr) & RCC_CR_HSERDY)) |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 163 | ; |
| 164 | |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 165 | setbits_le32(®s->cfgr, (( |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 166 | sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT) |
| 167 | | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT) |
| 168 | | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT))); |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 169 | |
| 170 | /* Configure the main PLL */ |
Patrice Chotard | b6653f6 | 2017-10-26 13:23:19 +0200 | [diff] [blame] | 171 | setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ |
| 172 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 173 | sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT); |
Patrice Chotard | b6653f6 | 2017-10-26 13:23:19 +0200 | [diff] [blame] | 174 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 175 | sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT); |
Patrice Chotard | b6653f6 | 2017-10-26 13:23:19 +0200 | [diff] [blame] | 176 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 177 | ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); |
Patrice Chotard | b6653f6 | 2017-10-26 13:23:19 +0200 | [diff] [blame] | 178 | clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 179 | sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT); |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 180 | |
Patrice Chotard | cb15d28 | 2018-02-08 17:20:47 +0100 | [diff] [blame] | 181 | /* configure SDMMC clock */ |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 182 | if (priv->info.v2) { /*stm32f7 case */ |
Patrice Chotard | cb15d28 | 2018-02-08 17:20:47 +0100 | [diff] [blame] | 183 | /* select PLLQ as 48MHz clock source */ |
| 184 | clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 185 | |
| 186 | /* select 48MHz as SDMMC1 clock source */ |
| 187 | clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); |
| 188 | |
| 189 | /* select 48MHz as SDMMC2 clock source */ |
| 190 | clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); |
| 191 | } else { /* stm32f4 case */ |
Patrice Chotard | cb15d28 | 2018-02-08 17:20:47 +0100 | [diff] [blame] | 192 | /* select PLLQ as 48MHz clock source */ |
| 193 | clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 194 | |
| 195 | /* select 48MHz as SDMMC1 clock source */ |
| 196 | clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); |
| 197 | } |
| 198 | |
Patrice Chotard | ff7b11e | 2018-02-08 17:20:49 +0100 | [diff] [blame] | 199 | #ifdef CONFIG_VIDEO_STM32 |
| 200 | /* |
| 201 | * Configure the SAI PLL to generate LTDC pixel clock |
| 202 | */ |
| 203 | clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, |
| 204 | RCC_PLLSAICFGR_PLLSAIR_3); |
| 205 | clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK, |
| 206 | 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT); |
| 207 | |
| 208 | clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, |
| 209 | RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); |
| 210 | #endif |
Patrice Chotard | cb15d28 | 2018-02-08 17:20:47 +0100 | [diff] [blame] | 211 | /* Enable the main PLL */ |
| 212 | setbits_le32(®s->cr, RCC_CR_PLLON); |
| 213 | while (!(readl(®s->cr) & RCC_CR_PLLRDY)) |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 214 | ; |
| 215 | |
Patrice Chotard | ff7b11e | 2018-02-08 17:20:49 +0100 | [diff] [blame] | 216 | #ifdef CONFIG_VIDEO_STM32 |
| 217 | /* Enable the SAI PLL */ |
| 218 | setbits_le32(®s->cr, RCC_CR_PLLSAION); |
| 219 | while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) |
| 220 | ; |
| 221 | #endif |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 222 | setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 223 | |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 224 | if (priv->info.has_overdrive) { |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 225 | /* |
| 226 | * Enable high performance mode |
| 227 | * System frequency up to 200 MHz |
| 228 | */ |
| 229 | setbits_le32(&pwr->cr1, PWR_CR1_ODEN); |
| 230 | /* Infinite wait! */ |
| 231 | while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) |
| 232 | ; |
| 233 | /* Enable the Over-drive switch */ |
| 234 | setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); |
| 235 | /* Infinite wait! */ |
| 236 | while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) |
| 237 | ; |
| 238 | } |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 239 | |
| 240 | stm32_flash_latency_cfg(5); |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 241 | clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); |
| 242 | setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 243 | |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 244 | while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 245 | RCC_CFGR_SWS_PLL) |
| 246 | ; |
| 247 | |
Patrice Chotard | e2d564e | 2018-01-18 14:10:05 +0100 | [diff] [blame] | 248 | #ifdef CONFIG_ETH_DESIGNWARE |
| 249 | /* gate the SYSCFG clock, needed to set RMII ethernet interface */ |
| 250 | setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN); |
| 251 | #endif |
| 252 | |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 253 | return 0; |
| 254 | } |
| 255 | |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 256 | static bool stm32_clk_get_ck48msel(struct stm32_clk *priv) |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 257 | { |
| 258 | struct stm32_rcc_regs *regs = priv->base; |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 259 | |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 260 | if (priv->info.v2) /*stm32f7 case */ |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 261 | return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 262 | else |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 263 | |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 264 | return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; |
| 265 | } |
| 266 | |
| 267 | static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv) |
| 268 | { |
| 269 | struct stm32_rcc_regs *regs = priv->base; |
| 270 | u16 pllm, pllsain; |
| 271 | |
| 272 | pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); |
| 273 | pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) |
| 274 | >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); |
| 275 | |
| 276 | return ((priv->hse_rate / pllm) * pllsain); |
| 277 | } |
| 278 | |
| 279 | static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv, |
| 280 | enum pllsai_div output) |
| 281 | { |
| 282 | struct stm32_rcc_regs *regs = priv->base; |
| 283 | u16 pll_div_output; |
| 284 | |
| 285 | switch (output) { |
| 286 | case PLLSAIP: |
| 287 | pll_div_output = ((((readl(®s->pllsaicfgr) |
| 288 | & RCC_PLLSAICFGR_PLLSAIP_MASK) |
| 289 | >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); |
| 290 | break; |
| 291 | case PLLSAIQ: |
| 292 | pll_div_output = (readl(®s->pllsaicfgr) |
| 293 | & RCC_PLLSAICFGR_PLLSAIQ_MASK) |
| 294 | >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT; |
| 295 | break; |
| 296 | case PLLSAIR: |
| 297 | pll_div_output = (readl(®s->pllsaicfgr) |
| 298 | & RCC_PLLSAICFGR_PLLSAIR_MASK) |
| 299 | >> RCC_PLLSAICFGR_PLLSAIR_SHIFT; |
| 300 | break; |
| 301 | default: |
| 302 | pr_err("incorrect PLLSAI output %d\n", output); |
| 303 | return -EINVAL; |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 304 | } |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 305 | |
| 306 | return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output); |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 307 | } |
| 308 | |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 309 | static bool stm32_get_timpre(struct stm32_clk *priv) |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 310 | { |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 311 | struct stm32_rcc_regs *regs = priv->base; |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 312 | u32 val; |
| 313 | |
| 314 | if (priv->info.v2) /*stm32f7 case */ |
| 315 | val = readl(®s->dckcfgr2); |
| 316 | else |
| 317 | val = readl(®s->dckcfgr); |
| 318 | /* get timer prescaler */ |
| 319 | return !!(val & RCC_DCKCFGRX_TIMPRE); |
| 320 | } |
| 321 | |
| 322 | static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk) |
| 323 | { |
| 324 | u8 shift; |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 325 | /* Prescaler table lookups for clock computation */ |
| 326 | u8 ahb_psc_table[16] = { |
| 327 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 |
| 328 | }; |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 329 | |
| 330 | shift = ahb_psc_table[( |
| 331 | (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) |
| 332 | >> RCC_CFGR_HPRE_SHIFT)]; |
| 333 | |
| 334 | return sysclk >> shift; |
| 335 | }; |
| 336 | |
| 337 | static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb) |
| 338 | { |
| 339 | /* Prescaler table lookups for clock computation */ |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 340 | u8 apb_psc_table[8] = { |
| 341 | 0, 0, 0, 0, 1, 2, 3, 4 |
| 342 | }; |
| 343 | |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 344 | if (apb == APB1) |
| 345 | return apb_psc_table[( |
| 346 | (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) |
| 347 | >> RCC_CFGR_PPRE1_SHIFT)]; |
| 348 | else /* APB2 */ |
| 349 | return apb_psc_table[( |
| 350 | (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) |
| 351 | >> RCC_CFGR_PPRE2_SHIFT)]; |
| 352 | }; |
| 353 | |
| 354 | static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk, |
| 355 | enum apb apb) |
| 356 | { |
| 357 | struct stm32_rcc_regs *regs = priv->base; |
| 358 | u8 shift = stm32_get_apb_shift(regs, apb); |
| 359 | |
| 360 | if (stm32_get_timpre(priv)) |
| 361 | /* |
| 362 | * if APB prescaler is configured to a |
| 363 | * division factor of 1, 2 or 4 |
| 364 | */ |
| 365 | switch (shift) { |
| 366 | case 0: |
| 367 | case 1: |
| 368 | case 2: |
| 369 | return stm32_get_hclk_rate(regs, sysclk); |
| 370 | default: |
| 371 | return (sysclk >> shift) * 4; |
| 372 | } |
| 373 | else |
| 374 | /* |
| 375 | * if APB prescaler is configured to a |
| 376 | * division factor of 1 |
| 377 | */ |
| 378 | if (shift == 0) |
| 379 | return sysclk; |
| 380 | else |
| 381 | return (sysclk >> shift) * 2; |
| 382 | }; |
| 383 | |
| 384 | static ulong stm32_clk_get_rate(struct clk *clk) |
| 385 | { |
| 386 | struct stm32_clk *priv = dev_get_priv(clk->dev); |
| 387 | struct stm32_rcc_regs *regs = priv->base; |
| 388 | u32 sysclk = 0; |
Patrice Chotard | 81d7765 | 2018-02-08 17:20:45 +0100 | [diff] [blame] | 389 | u32 vco; |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 390 | u32 sdmmcxsel_bit; |
Patrice Chotard | ff7b11e | 2018-02-08 17:20:49 +0100 | [diff] [blame] | 391 | u32 saidivr; |
| 392 | u32 pllsai_rate; |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 393 | u16 pllm, plln, pllp, pllq; |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 394 | |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 395 | if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == |
| 396 | RCC_CFGR_SWS_PLL) { |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 397 | pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); |
| 398 | plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) |
| 399 | >> RCC_PLLCFGR_PLLN_SHIFT); |
| 400 | pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) |
| 401 | >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 402 | pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) |
| 403 | >> RCC_PLLCFGR_PLLQ_SHIFT); |
Patrice Chotard | 81d7765 | 2018-02-08 17:20:45 +0100 | [diff] [blame] | 404 | vco = (priv->hse_rate / pllm) * plln; |
| 405 | sysclk = vco / pllp; |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 406 | } else { |
| 407 | return -EINVAL; |
| 408 | } |
| 409 | |
| 410 | switch (clk->id) { |
| 411 | /* |
| 412 | * AHB CLOCK: 3 x 32 bits consecutive registers are used : |
| 413 | * AHB1, AHB2 and AHB3 |
| 414 | */ |
| 415 | case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 416 | return stm32_get_hclk_rate(regs, sysclk); |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 417 | /* APB1 CLOCK */ |
| 418 | case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 419 | /* For timer clock, an additionnal prescaler is used*/ |
| 420 | switch (clk->id) { |
| 421 | case STM32F7_APB1_CLOCK(TIM2): |
| 422 | case STM32F7_APB1_CLOCK(TIM3): |
| 423 | case STM32F7_APB1_CLOCK(TIM4): |
| 424 | case STM32F7_APB1_CLOCK(TIM5): |
| 425 | case STM32F7_APB1_CLOCK(TIM6): |
| 426 | case STM32F7_APB1_CLOCK(TIM7): |
| 427 | case STM32F7_APB1_CLOCK(TIM12): |
| 428 | case STM32F7_APB1_CLOCK(TIM13): |
| 429 | case STM32F7_APB1_CLOCK(TIM14): |
| 430 | return stm32_get_timer_rate(priv, sysclk, APB1); |
| 431 | } |
| 432 | return (sysclk >> stm32_get_apb_shift(regs, APB1)); |
| 433 | |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 434 | /* APB2 CLOCK */ |
Patrice Chotard | e199c3a | 2018-02-08 17:20:51 +0100 | [diff] [blame] | 435 | case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI): |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 436 | switch (clk->id) { |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 437 | /* |
| 438 | * particular case for SDMMC1 and SDMMC2 : |
| 439 | * 48Mhz source clock can be from main PLL or from |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 440 | * PLLSAIP |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 441 | */ |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 442 | case STM32F7_APB2_CLOCK(SDMMC1): |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 443 | case STM32F7_APB2_CLOCK(SDMMC2): |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 444 | if (clk->id == STM32F7_APB2_CLOCK(SDMMC1)) |
| 445 | sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL; |
| 446 | else |
| 447 | sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL; |
| 448 | |
| 449 | if (readl(®s->dckcfgr2) & sdmmcxsel_bit) |
| 450 | /* System clock is selected as SDMMC1 clock */ |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 451 | return sysclk; |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 452 | /* |
| 453 | * 48 MHz can be generated by either PLLSAIP |
| 454 | * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR |
| 455 | */ |
| 456 | if (stm32_clk_get_ck48msel(priv)) |
| 457 | return stm32_clk_get_pllsai_rate(priv, PLLSAIP); |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 458 | else |
Patrice Chotard | 8aca2d1 | 2018-02-08 17:20:48 +0100 | [diff] [blame] | 459 | return (vco / pllq); |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 460 | break; |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 461 | |
| 462 | /* For timer clock, an additionnal prescaler is used*/ |
| 463 | case STM32F7_APB2_CLOCK(TIM1): |
| 464 | case STM32F7_APB2_CLOCK(TIM8): |
| 465 | case STM32F7_APB2_CLOCK(TIM9): |
| 466 | case STM32F7_APB2_CLOCK(TIM10): |
| 467 | case STM32F7_APB2_CLOCK(TIM11): |
| 468 | return stm32_get_timer_rate(priv, sysclk, APB2); |
| 469 | break; |
Patrice Chotard | ff7b11e | 2018-02-08 17:20:49 +0100 | [diff] [blame] | 470 | |
| 471 | /* particular case for LTDC clock */ |
| 472 | case STM32F7_APB2_CLOCK(LTDC): |
| 473 | saidivr = readl(®s->dckcfgr); |
| 474 | saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK) |
| 475 | >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT; |
| 476 | pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); |
| 477 | |
| 478 | return pllsai_rate / pllsaidivr_table[saidivr]; |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 479 | } |
Patrice Chotard | ef77287 | 2018-02-07 10:44:46 +0100 | [diff] [blame] | 480 | return (sysclk >> stm32_get_apb_shift(regs, APB2)); |
Patrice Chotard | 369d483 | 2017-11-15 13:14:52 +0100 | [diff] [blame] | 481 | |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 482 | default: |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 483 | pr_err("clock index %ld out of range\n", clk->id); |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 484 | return -EINVAL; |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 485 | } |
| 486 | } |
| 487 | |
Patrice Chotard | 24e8578 | 2018-01-29 18:14:14 +0100 | [diff] [blame] | 488 | static ulong stm32_set_rate(struct clk *clk, ulong rate) |
| 489 | { |
Patrice Chotard | 2cd1ed1 | 2018-02-08 17:20:50 +0100 | [diff] [blame] | 490 | #ifdef CONFIG_VIDEO_STM32 |
| 491 | struct stm32_clk *priv = dev_get_priv(clk->dev); |
| 492 | struct stm32_rcc_regs *regs = priv->base; |
| 493 | u32 pllsair_rate, pllsai_vco_rate, current_rate; |
| 494 | u32 best_div, best_diff, diff; |
| 495 | u16 div; |
| 496 | u8 best_plldivr, best_pllsaidivr; |
| 497 | u8 i, j; |
| 498 | bool found = false; |
| 499 | |
| 500 | /* Only set_rate for LTDC clock is implemented */ |
| 501 | if (clk->id != STM32F7_APB2_CLOCK(LTDC)) { |
| 502 | pr_err("set_rate not implemented for clock index %ld\n", |
| 503 | clk->id); |
| 504 | return 0; |
| 505 | } |
| 506 | |
| 507 | if (rate == stm32_clk_get_rate(clk)) |
| 508 | /* already set to requested rate */ |
| 509 | return rate; |
| 510 | |
| 511 | /* get the current PLLSAIR output freq */ |
| 512 | pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); |
| 513 | best_div = pllsair_rate / rate; |
| 514 | |
| 515 | /* look into pllsaidivr_table if this divider is available*/ |
| 516 | for (i = 0 ; i < sizeof(pllsaidivr_table); i++) |
| 517 | if (best_div == pllsaidivr_table[i]) { |
| 518 | /* set pll_saidivr with found value */ |
| 519 | clrsetbits_le32(®s->dckcfgr, |
| 520 | RCC_DCKCFGR_PLLSAIDIVR_MASK, |
| 521 | pllsaidivr_table[i]); |
| 522 | return rate; |
| 523 | } |
| 524 | |
| 525 | /* |
| 526 | * As no pllsaidivr value is suitable to obtain requested freq, |
| 527 | * test all combination of pllsaidivr * pllsair and find the one |
| 528 | * which give freq closest to requested rate. |
| 529 | */ |
| 530 | |
| 531 | pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv); |
| 532 | best_diff = ULONG_MAX; |
| 533 | best_pllsaidivr = 0; |
| 534 | best_plldivr = 0; |
| 535 | /* |
| 536 | * start at index 2 of plldivr_table as divider value at index 0 |
| 537 | * and 1 are 0) |
| 538 | */ |
| 539 | for (i = 2; i < sizeof(plldivr_table); i++) { |
| 540 | for (j = 0; j < sizeof(pllsaidivr_table); j++) { |
| 541 | div = plldivr_table[i] * pllsaidivr_table[j]; |
| 542 | current_rate = pllsai_vco_rate / div; |
| 543 | /* perfect combination is found ? */ |
| 544 | if (current_rate == rate) { |
| 545 | best_pllsaidivr = j; |
| 546 | best_plldivr = i; |
| 547 | found = true; |
| 548 | break; |
| 549 | } |
| 550 | |
| 551 | diff = (current_rate > rate) ? |
| 552 | current_rate - rate : rate - current_rate; |
| 553 | |
| 554 | /* found a better combination ? */ |
| 555 | if (diff < best_diff) { |
| 556 | best_diff = diff; |
| 557 | best_pllsaidivr = j; |
| 558 | best_plldivr = i; |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | if (found) |
| 563 | break; |
| 564 | } |
| 565 | |
| 566 | /* Disable the SAI PLL */ |
| 567 | clrbits_le32(®s->cr, RCC_CR_PLLSAION); |
| 568 | |
| 569 | /* set pll_saidivr with found value */ |
| 570 | clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, |
| 571 | best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); |
| 572 | |
| 573 | /* set pllsair with found value */ |
| 574 | clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, |
| 575 | plldivr_table[best_plldivr] |
| 576 | << RCC_PLLSAICFGR_PLLSAIR_SHIFT); |
| 577 | |
| 578 | /* Enable the SAI PLL */ |
| 579 | setbits_le32(®s->cr, RCC_CR_PLLSAION); |
| 580 | while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) |
| 581 | ; |
| 582 | |
| 583 | div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr]; |
| 584 | return pllsai_vco_rate / div; |
| 585 | #else |
Patrice Chotard | 24e8578 | 2018-01-29 18:14:14 +0100 | [diff] [blame] | 586 | return 0; |
Patrice Chotard | 2cd1ed1 | 2018-02-08 17:20:50 +0100 | [diff] [blame] | 587 | #endif |
Patrice Chotard | 24e8578 | 2018-01-29 18:14:14 +0100 | [diff] [blame] | 588 | } |
| 589 | |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 590 | static int stm32_clk_enable(struct clk *clk) |
| 591 | { |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 592 | struct stm32_clk *priv = dev_get_priv(clk->dev); |
| 593 | struct stm32_rcc_regs *regs = priv->base; |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 594 | u32 offset = clk->id / 32; |
| 595 | u32 bit_index = clk->id % 32; |
| 596 | |
| 597 | debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", |
| 598 | __func__, clk->id, offset, bit_index); |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 599 | setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 600 | |
| 601 | return 0; |
| 602 | } |
Toshifumi NISHINAGA | 65bfb9c | 2016-07-08 01:02:24 +0900 | [diff] [blame] | 603 | |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 604 | static int stm32_clk_probe(struct udevice *dev) |
| 605 | { |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 606 | struct ofnode_phandle_args args; |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 607 | struct udevice *fixed_clock_dev = NULL; |
| 608 | struct clk clk; |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 609 | int err; |
| 610 | |
Patrice Chotard | d4f2d20 | 2017-11-15 13:14:48 +0100 | [diff] [blame] | 611 | debug("%s\n", __func__); |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 612 | |
| 613 | struct stm32_clk *priv = dev_get_priv(dev); |
| 614 | fdt_addr_t addr; |
| 615 | |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 616 | addr = dev_read_addr(dev); |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 617 | if (addr == FDT_ADDR_T_NONE) |
| 618 | return -EINVAL; |
| 619 | |
| 620 | priv->base = (struct stm32_rcc_regs *)addr; |
Patrice Chotard | 03f10a1 | 2017-11-15 13:14:51 +0100 | [diff] [blame] | 621 | |
| 622 | switch (dev_get_driver_data(dev)) { |
| 623 | case STM32F4: |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 624 | memcpy(&priv->info, &stm32f4_clk_info, |
| 625 | sizeof(struct stm32_clk_info)); |
Patrice Chotard | 03f10a1 | 2017-11-15 13:14:51 +0100 | [diff] [blame] | 626 | break; |
| 627 | case STM32F7: |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 628 | memcpy(&priv->info, &stm32f7_clk_info, |
| 629 | sizeof(struct stm32_clk_info)); |
Patrice Chotard | 03f10a1 | 2017-11-15 13:14:51 +0100 | [diff] [blame] | 630 | break; |
| 631 | default: |
| 632 | return -EINVAL; |
| 633 | } |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 634 | |
Patrice Chotard | acd97ca | 2018-01-18 13:39:30 +0100 | [diff] [blame] | 635 | /* retrieve HSE frequency (external oscillator) */ |
| 636 | err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse", |
| 637 | &fixed_clock_dev); |
| 638 | |
| 639 | if (err) { |
| 640 | pr_err("Can't find fixed clock (%d)", err); |
| 641 | return err; |
| 642 | } |
| 643 | |
| 644 | err = clk_request(fixed_clock_dev, &clk); |
| 645 | if (err) { |
| 646 | pr_err("Can't request %s clk (%d)", fixed_clock_dev->name, |
| 647 | err); |
| 648 | return err; |
| 649 | } |
| 650 | |
| 651 | /* |
| 652 | * set pllm factor accordingly to the external oscillator |
| 653 | * frequency (HSE). For STM32F4 and STM32F7, we want VCO |
| 654 | * freq at 1MHz |
| 655 | * if input PLL frequency is 25Mhz, divide it by 25 |
| 656 | */ |
| 657 | clk.id = 0; |
| 658 | priv->hse_rate = clk_get_rate(&clk); |
| 659 | |
| 660 | if (priv->hse_rate < 1000000) { |
| 661 | pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__, |
| 662 | priv->hse_rate); |
| 663 | return -EINVAL; |
| 664 | } |
| 665 | |
| 666 | priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000; |
| 667 | |
| 668 | if (priv->info.has_overdrive) { |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 669 | err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, |
| 670 | &args); |
| 671 | if (err) { |
| 672 | debug("%s: can't find syscon device (%d)\n", __func__, |
| 673 | err); |
| 674 | return err; |
| 675 | } |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 676 | |
Patrice Chotard | 1509d66 | 2017-11-15 13:14:47 +0100 | [diff] [blame] | 677 | priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); |
| 678 | } |
Patrice Chotard | 22768d5 | 2017-11-15 13:14:44 +0100 | [diff] [blame] | 679 | |
Patrice Chotard | d93fc2c | 2017-07-18 09:29:04 +0200 | [diff] [blame] | 680 | configure_clocks(dev); |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 681 | |
| 682 | return 0; |
| 683 | } |
| 684 | |
Simon Glass | b7ae277 | 2017-05-18 20:09:40 -0600 | [diff] [blame] | 685 | static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 686 | { |
| 687 | debug("%s(clk=%p)\n", __func__, clk); |
| 688 | |
| 689 | if (args->args_count != 2) { |
| 690 | debug("Invaild args_count: %d\n", args->args_count); |
| 691 | return -EINVAL; |
| 692 | } |
| 693 | |
| 694 | if (args->args_count) |
| 695 | clk->id = args->args[1]; |
| 696 | else |
| 697 | clk->id = 0; |
| 698 | |
| 699 | return 0; |
| 700 | } |
| 701 | |
| 702 | static struct clk_ops stm32_clk_ops = { |
| 703 | .of_xlate = stm32_clk_of_xlate, |
| 704 | .enable = stm32_clk_enable, |
Patrice Chotard | 7bdf971 | 2017-07-18 09:29:05 +0200 | [diff] [blame] | 705 | .get_rate = stm32_clk_get_rate, |
Patrice Chotard | 24e8578 | 2018-01-29 18:14:14 +0100 | [diff] [blame] | 706 | .set_rate = stm32_set_rate, |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 707 | }; |
| 708 | |
Patrice Chotard | d4f2d20 | 2017-11-15 13:14:48 +0100 | [diff] [blame] | 709 | U_BOOT_DRIVER(stm32fx_clk) = { |
Patrice Chotard | 03f10a1 | 2017-11-15 13:14:51 +0100 | [diff] [blame] | 710 | .name = "stm32fx_rcc_clock", |
Patrice Chotard | b323de5 | 2017-09-21 10:08:09 +0200 | [diff] [blame] | 711 | .id = UCLASS_CLK, |
Patrice Chotard | b323de5 | 2017-09-21 10:08:09 +0200 | [diff] [blame] | 712 | .ops = &stm32_clk_ops, |
| 713 | .probe = stm32_clk_probe, |
| 714 | .priv_auto_alloc_size = sizeof(struct stm32_clk), |
| 715 | .flags = DM_FLAG_PRE_RELOC, |
Vikas Manocha | daaeaab | 2017-02-12 10:25:45 -0800 | [diff] [blame] | 716 | }; |