Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 40e749bbbef23ce778fa1fa208c2d75c42ae744f / . / arch / x86 / dts / chromebook_link.dts
blob: fab919a3589dda4dfe8fa6b318ef259773aa41a4 [file] [log] [blame]
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Simon Glass7be7f3e2016-03-11 22:07:12 -0700[diff] [blame]3#include <dt-bindings/gpio/x86-gpio.h>
4
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]5/include/ "skeleton.dtsi"
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]6/include/ "keyboard.dtsi"
Bin Meng82db36c2014-12-24 13:06:38 +0800[diff] [blame]7/include/ "serial.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]8/include/ "rtc.dtsi"
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]9/include/ "tsc_timer.dtsi"
Bin Menga4470172016-10-09 04:14:18 -0700[diff] [blame]10/include/ "coreboot_fb.dtsi"
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]11
12/ {
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]13 model = "Google Link";
14 compatible = "google,link", "intel,celeron-ivybridge";
15
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]16 aliases {
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]17 spi0 = &spi;
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame]18 usb0 = &usb_0;
19 usb1 = &usb_1;
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]20 };
21
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]22 config {
23 silent_console = <0>;
24 };
25
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]29 u-boot,dm-pre-reloc;
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "intel,core-gen3";
34 reg = <0>;
35 intel,apic-id = <0>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]36 u-boot,dm-pre-reloc;
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]37 };
38
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "intel,core-gen3";
42 reg = <1>;
43 intel,apic-id = <1>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]44 u-boot,dm-pre-reloc;
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]45 };
46
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "intel,core-gen3";
50 reg = <2>;
51 intel,apic-id = <2>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]52 u-boot,dm-pre-reloc;
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]53 };
54
55 cpu@3 {
56 device_type = "cpu";
57 compatible = "intel,core-gen3";
58 reg = <3>;
59 intel,apic-id = <3>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]60 u-boot,dm-pre-reloc;
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]61 };
62
63 };
64
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]65 chosen {
66 stdout-path = "/serial";
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]67 };
68
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]69 keyboard {
70 intel,duplicate-por;
71 };
72
Simon Glass7be7f3e2016-03-11 22:07:12 -0700[diff] [blame]73 pch_pinctrl {
74 compatible = "intel,x86-pinctrl";
75 u-boot,dm-pre-reloc;
76 reg = <0 0>;
77
78 gpio_a0 {
79 gpio-offset = <0 0>;
80 mode-gpio;
81 direction = <PIN_INPUT>;
82 };
83
84 gpio_a1 {
85 gpio-offset = <0>;
86 mode-gpio;
87 direction = <PIN_OUTPUT>;
88 output-value = <1>;
89 };
90
91 gpio_a3 {
92 gpio-offset = <0 3>;
93 mode-gpio;
94 direction = <PIN_INPUT>;
95 };
96
97 gpio_a5 {
98 gpio-offset = <0 5>;
99 mode-gpio;
100 direction = <PIN_INPUT>;
101 };
102
103 gpio_a6 {
104 gpio-offset = <0 6>;
105 mode-gpio;
106 direction = <PIN_OUTPUT>;
107 output-value = <1>;
108 };
109
110 gpio_a7 {
111 gpio-offset = <0 7>;
112 mode-gpio;
113 direction = <PIN_INPUT>;
114 invert;
115 };
116
117 gpio_a8 {
118 gpio-offset = <0 8>;
119 mode-gpio;
120 direction = <PIN_INPUT>;
121 invert;
122 };
123
124 gpio_a9 {
125 gpio-offset = <0 9>;
126 mode-gpio;
127 direction = <PIN_INPUT>;
128 };
129
130 gpio_a10 {
131 u-boot,dm-pre-reloc;
132 gpio-offset = <0 10>;
133 mode-gpio;
134 direction = <PIN_INPUT>;
135 };
136
137 gpio_a11 {
138 gpio-offset = <0 11>;
139 mode-gpio;
140 direction = <PIN_INPUT>;
141 };
142
143 gpio_a12 {
144 gpio-offset = <0 12>;
145 mode-gpio;
146 direction = <PIN_INPUT>;
147 invert;
148 };
149
150 gpio_a14 {
151 gpio-offset = <0 14>;
152 mode-gpio;
153 direction = <PIN_INPUT>;
154 invert;
155 };
156
157 gpio_a15 {
158 gpio-offset = <0 15>;
159 mode-gpio;
160 direction = <PIN_INPUT>;
161 invert;
162 };
163
164 gpio_a21 {
165 gpio-offset = <0 21>;
166 mode-gpio;
167 direction = <PIN_INPUT>;
168 };
169
170 gpio_a24 {
171 gpio-offset = <0 24>;
172 mode-gpio;
173 output-value = <0>;
174 direction = <PIN_OUTPUT>;
175 };
176
177 gpio_a28 {
178 gpio-offset = <0 28>;
179 mode-gpio;
180 direction = <PIN_INPUT>;
181 };
182
183 gpio_b4 {
184 gpio-offset = <0x30 4>;
185 mode-gpio;
186 direction = <PIN_OUTPUT>;
187 output-value = <1>;
188 };
189
190 gpio_b9 {
191 u-boot,dm-pre-reloc;
192 gpio-offset = <0x30 9>;
193 mode-gpio;
194 direction = <PIN_INPUT>;
195 };
196
197 gpio_b10 {
198 u-boot,dm-pre-reloc;
199 gpio-offset = <0x30 10>;
200 mode-gpio;
201 direction = <PIN_INPUT>;
202 };
203
204 gpio_b11 {
205 u-boot,dm-pre-reloc;
206 gpio-offset = <0x30 11>;
207 mode-gpio;
208 direction = <PIN_INPUT>;
209 };
210
211 gpio_b25 {
212 gpio-offset = <0x30 25>;
213 mode-gpio;
214 direction = <PIN_INPUT>;
215 };
216
217 gpio_b28 {
218 gpio-offset = <0x30 28>;
219 mode-gpio;
220 direction = <PIN_OUTPUT>;
221 output-value = <1>;
222 };
223
224 };
225
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]226 pci {
Simon Glass582075c2016-01-17 16:11:41 -0700[diff] [blame]227 compatible = "pci-x86";
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame]228 #address-cells = <3>;
229 #size-cells = <2>;
230 u-boot,dm-pre-reloc;
231 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
232 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
233 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
Simon Glass061e9ea2016-01-17 16:11:15 -0700[diff] [blame]234
235 northbridge@0,0 {
236 reg = <0x00000000 0 0 0 0>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]237 u-boot,dm-pre-reloc;
Simon Glass061e9ea2016-01-17 16:11:15 -0700[diff] [blame]238 compatible = "intel,bd82x6x-northbridge";
Simon Glassed5652c2016-03-06 19:28:12 -0700[diff] [blame]239 board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
240 <&gpio_b 11 0>, <&gpio_a 10 0>;
Simon Glassd7729f82016-03-06 19:28:11 -0700[diff] [blame]241 spd {
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]242 u-boot,dm-pre-reloc;
Simon Glassd7729f82016-03-06 19:28:11 -0700[diff] [blame]243 #address-cells = <1>;
244 #size-cells = <0>;
245 elpida_4Gb_1600_x16 {
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]246 u-boot,dm-pre-reloc;
Simon Glassd7729f82016-03-06 19:28:11 -0700[diff] [blame]247 reg = <0>;
248 data = [92 10 0b 03 04 19 02 02
249 03 52 01 08 0a 00 fe 00
250 69 78 69 3c 69 11 18 81
251 20 08 3c 3c 01 40 83 81
252 00 00 00 00 00 00 00 00
253 00 00 00 00 00 00 00 00
254 00 00 00 00 00 00 00 00
255 00 00 00 00 0f 11 42 00
256 00 00 00 00 00 00 00 00
257 00 00 00 00 00 00 00 00
258 00 00 00 00 00 00 00 00
259 00 00 00 00 00 00 00 00
260 00 00 00 00 00 00 00 00
261 00 00 00 00 00 00 00 00
262 00 00 00 00 00 02 fe 00
263 11 52 00 00 00 07 7f 37
264 45 42 4a 32 30 55 47 36
265 45 42 55 30 2d 47 4e 2d
266 46 20 30 20 02 fe 00 00
267 00 00 00 00 00 00 00 00
268 00 00 00 00 00 00 00 00
269 00 00 00 00 00 00 00 00
270 00 00 00 00 00 00 00 00
271 00 00 00 00 00 00 00 00
272 00 00 00 00 00 00 00 00
273 00 00 00 00 00 00 00 00
274 00 00 00 00 00 00 00 00
275 00 00 00 00 00 00 00 00
276 00 00 00 00 00 00 00 00
277 00 00 00 00 00 00 00 00
278 00 00 00 00 00 00 00 00
279 00 00 00 00 00 00 00 00];
280 };
281 samsung_4Gb_1600_1.35v_x16 {
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]282 u-boot,dm-pre-reloc;
Simon Glassd7729f82016-03-06 19:28:11 -0700[diff] [blame]283 reg = <1>;
284 data = [92 11 0b 03 04 19 02 02
285 03 11 01 08 0a 00 fe 00
286 69 78 69 3c 69 11 18 81
287 f0 0a 3c 3c 01 40 83 01
288 00 80 00 00 00 00 00 00
289 00 00 00 00 00 00 00 00
290 00 00 00 00 00 00 00 00
291 00 00 00 00 0f 11 02 00
292 00 00 00 00 00 00 00 00
293 00 00 00 00 00 00 00 00
294 00 00 00 00 00 00 00 00
295 00 00 00 00 00 00 00 00
296 00 00 00 00 00 00 00 00
297 00 00 00 00 00 00 00 00
298 00 00 00 00 00 80 ce 01
299 00 00 00 00 00 00 6a 04
300 4d 34 37 31 42 35 36 37
301 34 42 48 30 2d 59 4b 30
302 20 20 00 00 80 ce 00 00
303 00 00 00 00 00 00 00 00
304 00 00 00 00 00 00 00 00
305 00 00 00 00 00 00 00 00
306 00 00 00 00 00 00 00 00
307 00 00 00 00 00 00 00 00
308 00 00 00 00 00 00 00 00
309 00 00 00 00 00 00 00 00
310 00 00 00 00 00 00 00 00
311 00 00 00 00 00 00 00 00
312 00 00 00 00 00 00 00 00
313 00 00 00 00 00 00 00 00
314 00 00 00 00 00 00 00 00
315 00 00 00 00 00 00 00 00];
316 };
317 micron_4Gb_1600_1.35v_x16 {
318 reg = <2>;
319 data = [92 11 0b 03 04 19 02 02
320 03 11 01 08 0a 00 fe 00
321 69 78 69 3c 69 11 18 81
322 20 08 3c 3c 01 40 83 05
323 00 00 00 00 00 00 00 00
324 00 00 00 00 00 00 00 00
325 00 00 00 00 00 00 00 00
326 00 00 00 00 0f 01 02 00
327 00 00 00 00 00 00 00 00
328 00 00 00 00 00 00 00 00
329 00 00 00 00 00 00 00 00
330 00 00 00 00 00 00 00 00
331 00 00 00 00 00 00 00 00
332 00 00 00 00 00 00 00 00
333 00 00 00 00 00 80 2c 00
334 00 00 00 00 00 00 ad 75
335 34 4b 54 46 32 35 36 36
336 34 48 5a 2d 31 47 36 45
337 31 20 45 31 80 2c 00 00
338 00 00 00 00 00 00 00 00
339 00 00 00 00 00 00 00 00
340 00 00 00 00 00 00 00 00
341 ff ff ff ff ff ff ff ff
342 ff ff ff ff ff ff ff ff
343 ff ff ff ff ff ff ff ff
344 ff ff ff ff ff ff ff ff
345 ff ff ff ff ff ff ff ff
346 ff ff ff ff ff ff ff ff
347 ff ff ff ff ff ff ff ff
348 ff ff ff ff ff ff ff ff
349 ff ff ff ff ff ff ff ff
350 ff ff ff ff ff ff ff ff];
351 };
352 };
Simon Glass061e9ea2016-01-17 16:11:15 -0700[diff] [blame]353 };
354
Simon Glassa75abeb2016-01-17 16:11:59 -0700[diff] [blame]355 gma@2,0 {
356 reg = <0x00001000 0 0 0 0>;
Simon Glass85ff0b12014-11-14 20:56:37 -0700[diff] [blame]357 compatible = "intel,gma";
358 intel,dp_hotplug = <0 0 0x06>;
359 intel,panel-port-select = <1>;
360 intel,panel-power-cycle-delay = <6>;
361 intel,panel-power-up-delay = <2000>;
362 intel,panel-power-down-delay = <500>;
363 intel,panel-power-backlight-on-delay = <2000>;
364 intel,panel-power-backlight-off-delay = <2000>;
365 intel,cpu-backlight = <0x00000200>;
366 intel,pch-backlight = <0x04000000>;
367 };
368
Simon Glass37a91ff2016-01-17 16:11:50 -0700[diff] [blame]369 me@16,0 {
370 reg = <0x0000b000 0 0 0 0>;
371 compatible = "intel,me";
372 u-boot,dm-pre-reloc;
373 };
374
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame]375 usb_1: usb@1a,0 {
376 reg = <0x0000d000 0 0 0 0>;
377 compatible = "ehci-pci";
378 };
379
380 usb_0: usb@1d,0 {
381 reg = <0x0000e800 0 0 0 0>;
382 compatible = "ehci-pci";
383 };
384
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]385 pch@1f,0 {
Simon Glasse0e7b362015-03-05 12:25:33 -0700[diff] [blame]386 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]387 compatible = "intel,bd82x6x", "intel,pch9";
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]388 u-boot,dm-pre-reloc;
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]389 #address-cells = <1>;
390 #size-cells = <1>;
Simon Glassc1fd69e2014-11-14 18:18:37 -0700[diff] [blame]391 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
392 0x80 0x80 0x80 0x80>;
393 intel,gpi-routing = <0 0 0 0 0 0 0 2
394 1 0 0 0 0 0 0 0>;
395 /* Enable EC SMI source */
396 intel,alt-gp-smi-enable = <0x0100>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]397
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]398 spi: spi {
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]399 #address-cells = <1>;
400 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -0800[diff] [blame]401 compatible = "intel,ich9-spi";
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]402 u-boot,dm-pre-reloc;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]403 spi-flash@0 {
404 #size-cells = <1>;
405 #address-cells = <1>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]406 u-boot,dm-pre-reloc;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]407 reg = <0>;
408 compatible = "winbond,w25q64",
409 "spi-flash";
410 memory-map = <0xff800000 0x00800000>;
411 rw-mrc-cache {
412 label = "rw-mrc-cache";
413 reg = <0x003e0000 0x00010000>;
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]414 u-boot,dm-pre-reloc;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]415 };
416 };
417 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]418
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]419 gpio_a: gpioa {
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]420 compatible = "intel,ich6-gpio";
421 u-boot,dm-pre-reloc;
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]422 #gpio-cells = <2>;
423 gpio-controller;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]424 reg = <0 0x10>;
425 bank-name = "A";
426 };
427
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]428 gpio_b: gpiob {
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]429 compatible = "intel,ich6-gpio";
430 u-boot,dm-pre-reloc;
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]431 #gpio-cells = <2>;
432 gpio-controller;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]433 reg = <0x30 0x10>;
434 bank-name = "B";
435 };
436
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]437 gpio_c: gpioc {
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]438 compatible = "intel,ich6-gpio";
439 u-boot,dm-pre-reloc;
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]440 #gpio-cells = <2>;
441 gpio-controller;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]442 reg = <0x40 0x10>;
443 bank-name = "C";
444 };
445
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]446 lpc {
447 compatible = "intel,bd82x6x-lpc";
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]448 #address-cells = <1>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]449 #size-cells = <0>;
Simon Glass044f1a02016-01-17 16:11:10 -0700[diff] [blame]450 u-boot,dm-pre-reloc;
Simon Glass62b37172016-01-17 16:11:11 -0700[diff] [blame]451 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]452 cros-ec@200 {
453 compatible = "google,cros-ec";
454 reg = <0x204 1 0x200 1 0x880 0x80>;
455
456 /*
457 * Describes the flash memory within
458 * the EC
459 */
460 #address-cells = <1>;
461 #size-cells = <1>;
462 flash@8000000 {
463 reg = <0x08000000 0x20000>;
464 erase-value = <0xff>;
465 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]466 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]467 };
468 };
Simon Glass5cc400b2016-01-17 16:11:35 -0700[diff] [blame]469
470 sata@1f,2 {
471 compatible = "intel,pantherpoint-ahci";
472 reg = <0x0000fa00 0 0 0 0>;
473 u-boot,dm-pre-reloc;
474 intel,sata-mode = "ahci";
475 intel,sata-port-map = <1>;
476 intel,sata-port0-gen3-tx = <0x00880a7f>;
477 };
Simon Glass9afcd962016-01-17 16:11:45 -0700[diff] [blame]478
479 smbus: smbus@1f,3 {
480 compatible = "intel,ich-i2c";
481 reg = <0x0000fb00 0 0 0 0>;
482 u-boot,dm-pre-reloc;
483 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]484 };
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]485
Simon Glass11328532015-08-22 18:31:37 -0600[diff] [blame]486 tpm {
487 reg = <0xfed40000 0x5000>;
488 compatible = "infineon,slb9635lpc";
489 };
490
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]491 microcode {
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]492 u-boot,dm-pre-reloc;
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]493 update@0 {
Simon Glassfc1e11c2017-01-16 07:04:24 -0700[diff] [blame]494 u-boot,dm-pre-reloc;
Simon Glass44679e72014-12-15 22:02:40 -0700[diff] [blame]495#include "microcode/m12306a9_0000001b.dtsi"
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]496 };
497 };
498
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]499};