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git01.mediatek.com / filogic / uboot / d7729f8a96e6b815b058380e2b0ca4e676b6cff5 / . / arch / x86 / dts / chromebook_link.dts
blob: 12f315e66a71567fc3d5b927fd859cfad22aa9f4 [file] [log] [blame]
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]3/include/ "skeleton.dtsi"
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]4/include/ "keyboard.dtsi"
Bin Meng82db36c2014-12-24 13:06:38 +0800[diff] [blame]5/include/ "serial.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]6/include/ "rtc.dtsi"
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]7/include/ "tsc_timer.dtsi"
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]8
9/ {
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]10 model = "Google Link";
11 compatible = "google,link", "intel,celeron-ivybridge";
12
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]13 aliases {
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]14 spi0 = &spi;
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame]15 usb0 = &usb_0;
16 usb1 = &usb_1;
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]17 };
18
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]19 config {
20 silent_console = <0>;
21 };
22
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "intel,core-gen3";
30 reg = <0>;
31 intel,apic-id = <0>;
32 };
33
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "intel,core-gen3";
37 reg = <1>;
38 intel,apic-id = <1>;
39 };
40
41 cpu@2 {
42 device_type = "cpu";
43 compatible = "intel,core-gen3";
44 reg = <2>;
45 intel,apic-id = <2>;
46 };
47
48 cpu@3 {
49 device_type = "cpu";
50 compatible = "intel,core-gen3";
51 reg = <3>;
52 intel,apic-id = <3>;
53 };
54
55 };
56
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]57 chosen {
58 stdout-path = "/serial";
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]59 };
60
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]61 keyboard {
62 intel,duplicate-por;
63 };
64
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]65 pci {
Simon Glass582075c2016-01-17 16:11:41 -0700[diff] [blame]66 compatible = "pci-x86";
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame]67 #address-cells = <3>;
68 #size-cells = <2>;
69 u-boot,dm-pre-reloc;
70 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
71 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
72 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
Simon Glass061e9ea2016-01-17 16:11:15 -0700[diff] [blame]73
74 northbridge@0,0 {
75 reg = <0x00000000 0 0 0 0>;
76 compatible = "intel,bd82x6x-northbridge";
77 u-boot,dm-pre-reloc;
Simon Glassd7729f82016-03-06 19:28:11 -0700[diff] [blame^]78 spd {
79 compatible = "memory-spd";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 elpida_4Gb_1600_x16 {
83 reg = <0>;
84 data = [92 10 0b 03 04 19 02 02
85 03 52 01 08 0a 00 fe 00
86 69 78 69 3c 69 11 18 81
87 20 08 3c 3c 01 40 83 81
88 00 00 00 00 00 00 00 00
89 00 00 00 00 00 00 00 00
90 00 00 00 00 00 00 00 00
91 00 00 00 00 0f 11 42 00
92 00 00 00 00 00 00 00 00
93 00 00 00 00 00 00 00 00
94 00 00 00 00 00 00 00 00
95 00 00 00 00 00 00 00 00
96 00 00 00 00 00 00 00 00
97 00 00 00 00 00 00 00 00
98 00 00 00 00 00 02 fe 00
99 11 52 00 00 00 07 7f 37
100 45 42 4a 32 30 55 47 36
101 45 42 55 30 2d 47 4e 2d
102 46 20 30 20 02 fe 00 00
103 00 00 00 00 00 00 00 00
104 00 00 00 00 00 00 00 00
105 00 00 00 00 00 00 00 00
106 00 00 00 00 00 00 00 00
107 00 00 00 00 00 00 00 00
108 00 00 00 00 00 00 00 00
109 00 00 00 00 00 00 00 00
110 00 00 00 00 00 00 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 00 00 00 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00];
116 };
117 samsung_4Gb_1600_1.35v_x16 {
118 reg = <1>;
119 data = [92 11 0b 03 04 19 02 02
120 03 11 01 08 0a 00 fe 00
121 69 78 69 3c 69 11 18 81
122 f0 0a 3c 3c 01 40 83 01
123 00 80 00 00 00 00 00 00
124 00 00 00 00 00 00 00 00
125 00 00 00 00 00 00 00 00
126 00 00 00 00 0f 11 02 00
127 00 00 00 00 00 00 00 00
128 00 00 00 00 00 00 00 00
129 00 00 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00
131 00 00 00 00 00 00 00 00
132 00 00 00 00 00 00 00 00
133 00 00 00 00 00 80 ce 01
134 00 00 00 00 00 00 6a 04
135 4d 34 37 31 42 35 36 37
136 34 42 48 30 2d 59 4b 30
137 20 20 00 00 80 ce 00 00
138 00 00 00 00 00 00 00 00
139 00 00 00 00 00 00 00 00
140 00 00 00 00 00 00 00 00
141 00 00 00 00 00 00 00 00
142 00 00 00 00 00 00 00 00
143 00 00 00 00 00 00 00 00
144 00 00 00 00 00 00 00 00
145 00 00 00 00 00 00 00 00
146 00 00 00 00 00 00 00 00
147 00 00 00 00 00 00 00 00
148 00 00 00 00 00 00 00 00
149 00 00 00 00 00 00 00 00
150 00 00 00 00 00 00 00 00];
151 };
152 micron_4Gb_1600_1.35v_x16 {
153 reg = <2>;
154 data = [92 11 0b 03 04 19 02 02
155 03 11 01 08 0a 00 fe 00
156 69 78 69 3c 69 11 18 81
157 20 08 3c 3c 01 40 83 05
158 00 00 00 00 00 00 00 00
159 00 00 00 00 00 00 00 00
160 00 00 00 00 00 00 00 00
161 00 00 00 00 0f 01 02 00
162 00 00 00 00 00 00 00 00
163 00 00 00 00 00 00 00 00
164 00 00 00 00 00 00 00 00
165 00 00 00 00 00 00 00 00
166 00 00 00 00 00 00 00 00
167 00 00 00 00 00 00 00 00
168 00 00 00 00 00 80 2c 00
169 00 00 00 00 00 00 ad 75
170 34 4b 54 46 32 35 36 36
171 34 48 5a 2d 31 47 36 45
172 31 20 45 31 80 2c 00 00
173 00 00 00 00 00 00 00 00
174 00 00 00 00 00 00 00 00
175 00 00 00 00 00 00 00 00
176 ff ff ff ff ff ff ff ff
177 ff ff ff ff ff ff ff ff
178 ff ff ff ff ff ff ff ff
179 ff ff ff ff ff ff ff ff
180 ff ff ff ff ff ff ff ff
181 ff ff ff ff ff ff ff ff
182 ff ff ff ff ff ff ff ff
183 ff ff ff ff ff ff ff ff
184 ff ff ff ff ff ff ff ff
185 ff ff ff ff ff ff ff ff];
186 };
187 };
Simon Glass061e9ea2016-01-17 16:11:15 -0700[diff] [blame]188 };
189
Simon Glassa75abeb2016-01-17 16:11:59 -0700[diff] [blame]190 gma@2,0 {
191 reg = <0x00001000 0 0 0 0>;
Simon Glass85ff0b12014-11-14 20:56:37 -0700[diff] [blame]192 compatible = "intel,gma";
193 intel,dp_hotplug = <0 0 0x06>;
194 intel,panel-port-select = <1>;
195 intel,panel-power-cycle-delay = <6>;
196 intel,panel-power-up-delay = <2000>;
197 intel,panel-power-down-delay = <500>;
198 intel,panel-power-backlight-on-delay = <2000>;
199 intel,panel-power-backlight-off-delay = <2000>;
200 intel,cpu-backlight = <0x00000200>;
201 intel,pch-backlight = <0x04000000>;
202 };
203
Simon Glass37a91ff2016-01-17 16:11:50 -0700[diff] [blame]204 me@16,0 {
205 reg = <0x0000b000 0 0 0 0>;
206 compatible = "intel,me";
207 u-boot,dm-pre-reloc;
208 };
209
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame]210 usb_1: usb@1a,0 {
211 reg = <0x0000d000 0 0 0 0>;
212 compatible = "ehci-pci";
213 };
214
215 usb_0: usb@1d,0 {
216 reg = <0x0000e800 0 0 0 0>;
217 compatible = "ehci-pci";
218 };
219
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]220 pch@1f,0 {
Simon Glasse0e7b362015-03-05 12:25:33 -0700[diff] [blame]221 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]222 compatible = "intel,bd82x6x", "intel,pch9";
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]223 u-boot,dm-pre-reloc;
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]224 #address-cells = <1>;
225 #size-cells = <1>;
Simon Glassc1fd69e2014-11-14 18:18:37 -0700[diff] [blame]226 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
227 0x80 0x80 0x80 0x80>;
228 intel,gpi-routing = <0 0 0 0 0 0 0 2
229 1 0 0 0 0 0 0 0>;
230 /* Enable EC SMI source */
231 intel,alt-gp-smi-enable = <0x0100>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]232
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]233 spi: spi {
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]234 #address-cells = <1>;
235 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -0800[diff] [blame]236 compatible = "intel,ich9-spi";
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]237 spi-flash@0 {
238 #size-cells = <1>;
239 #address-cells = <1>;
240 reg = <0>;
241 compatible = "winbond,w25q64",
242 "spi-flash";
243 memory-map = <0xff800000 0x00800000>;
244 rw-mrc-cache {
245 label = "rw-mrc-cache";
246 reg = <0x003e0000 0x00010000>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]247 };
248 };
249 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]250
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]251 gpio_a: gpioa {
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]252 compatible = "intel,ich6-gpio";
253 u-boot,dm-pre-reloc;
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]254 #gpio-cells = <2>;
255 gpio-controller;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]256 reg = <0 0x10>;
257 bank-name = "A";
258 };
259
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]260 gpio_b: gpiob {
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]261 compatible = "intel,ich6-gpio";
262 u-boot,dm-pre-reloc;
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]263 #gpio-cells = <2>;
264 gpio-controller;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]265 reg = <0x30 0x10>;
266 bank-name = "B";
267 };
268
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]269 gpio_c: gpioc {
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]270 compatible = "intel,ich6-gpio";
271 u-boot,dm-pre-reloc;
Simon Glass8a307ee2016-03-06 19:28:10 -0700[diff] [blame]272 #gpio-cells = <2>;
273 gpio-controller;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]274 reg = <0x40 0x10>;
275 bank-name = "C";
276 };
277
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]278 lpc {
279 compatible = "intel,bd82x6x-lpc";
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]280 #address-cells = <1>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]281 #size-cells = <0>;
Simon Glass044f1a02016-01-17 16:11:10 -0700[diff] [blame]282 u-boot,dm-pre-reloc;
Simon Glass62b37172016-01-17 16:11:11 -0700[diff] [blame]283 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]284 cros-ec@200 {
285 compatible = "google,cros-ec";
286 reg = <0x204 1 0x200 1 0x880 0x80>;
287
288 /*
289 * Describes the flash memory within
290 * the EC
291 */
292 #address-cells = <1>;
293 #size-cells = <1>;
294 flash@8000000 {
295 reg = <0x08000000 0x20000>;
296 erase-value = <0xff>;
297 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]298 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]299 };
300 };
Simon Glass5cc400b2016-01-17 16:11:35 -0700[diff] [blame]301
302 sata@1f,2 {
303 compatible = "intel,pantherpoint-ahci";
304 reg = <0x0000fa00 0 0 0 0>;
305 u-boot,dm-pre-reloc;
306 intel,sata-mode = "ahci";
307 intel,sata-port-map = <1>;
308 intel,sata-port0-gen3-tx = <0x00880a7f>;
309 };
Simon Glass9afcd962016-01-17 16:11:45 -0700[diff] [blame]310
311 smbus: smbus@1f,3 {
312 compatible = "intel,ich-i2c";
313 reg = <0x0000fb00 0 0 0 0>;
314 u-boot,dm-pre-reloc;
315 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]316 };
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]317
Simon Glass11328532015-08-22 18:31:37 -0600[diff] [blame]318 tpm {
319 reg = <0xfed40000 0x5000>;
320 compatible = "infineon,slb9635lpc";
321 };
322
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]323 microcode {
324 update@0 {
Simon Glass44679e72014-12-15 22:02:40 -0700[diff] [blame]325#include "microcode/m12306a9_0000001b.dtsi"
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]326 };
327 };
328
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]329};