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git01.mediatek.com / filogic / uboot / 74a9e6abcb5f1228bfd91bfa182b3304524289ab / . / arch / x86 / dts / chromebook_link.dts
blob: 662e5d9a00ce7eac07f88634a12e10b9a6fec9f0 [file] [log] [blame]
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]3/include/ "skeleton.dtsi"
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]4/include/ "keyboard.dtsi"
Bin Meng82db36c2014-12-24 13:06:38 +0800[diff] [blame]5/include/ "serial.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]6/include/ "rtc.dtsi"
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]7/include/ "tsc_timer.dtsi"
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]8
9/ {
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]10 model = "Google Link";
11 compatible = "google,link", "intel,celeron-ivybridge";
12
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]13 aliases {
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]14 spi0 = "/pci/pch/spi";
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame^]15 usb0 = &usb_0;
16 usb1 = &usb_1;
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]17 };
18
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]19 config {
20 silent_console = <0>;
21 };
22
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "intel,core-gen3";
30 reg = <0>;
31 intel,apic-id = <0>;
32 };
33
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "intel,core-gen3";
37 reg = <1>;
38 intel,apic-id = <1>;
39 };
40
41 cpu@2 {
42 device_type = "cpu";
43 compatible = "intel,core-gen3";
44 reg = <2>;
45 intel,apic-id = <2>;
46 };
47
48 cpu@3 {
49 device_type = "cpu";
50 compatible = "intel,core-gen3";
51 reg = <3>;
52 intel,apic-id = <3>;
53 };
54
55 };
56
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]57 gpioa {
58 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]59 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]60 reg = <0 0x10>;
61 bank-name = "A";
62 };
63
64 gpiob {
65 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]66 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]67 reg = <0x30 0x10>;
68 bank-name = "B";
69 };
70
71 gpioc {
72 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]73 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]74 reg = <0x40 0x10>;
75 bank-name = "C";
76 };
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]77
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]78 chosen {
79 stdout-path = "/serial";
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]80 };
81
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]82 keyboard {
83 intel,duplicate-por;
84 };
85
Simon Glass268eefd2014-11-12 22:42:28 -0700[diff] [blame]86 spd {
87 compatible = "memory-spd";
88 #address-cells = <1>;
89 #size-cells = <0>;
90 elpida_4Gb_1600_x16 {
91 reg = <0>;
92 data = [92 10 0b 03 04 19 02 02
93 03 52 01 08 0a 00 fe 00
94 69 78 69 3c 69 11 18 81
95 20 08 3c 3c 01 40 83 81
96 00 00 00 00 00 00 00 00
97 00 00 00 00 00 00 00 00
98 00 00 00 00 00 00 00 00
99 00 00 00 00 0f 11 42 00
100 00 00 00 00 00 00 00 00
101 00 00 00 00 00 00 00 00
102 00 00 00 00 00 00 00 00
103 00 00 00 00 00 00 00 00
104 00 00 00 00 00 00 00 00
105 00 00 00 00 00 00 00 00
106 00 00 00 00 00 02 fe 00
107 11 52 00 00 00 07 7f 37
108 45 42 4a 32 30 55 47 36
109 45 42 55 30 2d 47 4e 2d
110 46 20 30 20 02 fe 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 00 00 00 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00
116 00 00 00 00 00 00 00 00
117 00 00 00 00 00 00 00 00
118 00 00 00 00 00 00 00 00
119 00 00 00 00 00 00 00 00
120 00 00 00 00 00 00 00 00
121 00 00 00 00 00 00 00 00
122 00 00 00 00 00 00 00 00
123 00 00 00 00 00 00 00 00];
124 };
125 samsung_4Gb_1600_1.35v_x16 {
126 reg = <1>;
127 data = [92 11 0b 03 04 19 02 02
128 03 11 01 08 0a 00 fe 00
129 69 78 69 3c 69 11 18 81
130 f0 0a 3c 3c 01 40 83 01
131 00 80 00 00 00 00 00 00
132 00 00 00 00 00 00 00 00
133 00 00 00 00 00 00 00 00
134 00 00 00 00 0f 11 02 00
135 00 00 00 00 00 00 00 00
136 00 00 00 00 00 00 00 00
137 00 00 00 00 00 00 00 00
138 00 00 00 00 00 00 00 00
139 00 00 00 00 00 00 00 00
140 00 00 00 00 00 00 00 00
141 00 00 00 00 00 80 ce 01
142 00 00 00 00 00 00 6a 04
143 4d 34 37 31 42 35 36 37
144 34 42 48 30 2d 59 4b 30
145 20 20 00 00 80 ce 00 00
146 00 00 00 00 00 00 00 00
147 00 00 00 00 00 00 00 00
148 00 00 00 00 00 00 00 00
149 00 00 00 00 00 00 00 00
150 00 00 00 00 00 00 00 00
151 00 00 00 00 00 00 00 00
152 00 00 00 00 00 00 00 00
153 00 00 00 00 00 00 00 00
154 00 00 00 00 00 00 00 00
155 00 00 00 00 00 00 00 00
156 00 00 00 00 00 00 00 00
157 00 00 00 00 00 00 00 00
158 00 00 00 00 00 00 00 00];
159 };
160 micron_4Gb_1600_1.35v_x16 {
161 reg = <2>;
162 data = [92 11 0b 03 04 19 02 02
163 03 11 01 08 0a 00 fe 00
164 69 78 69 3c 69 11 18 81
165 20 08 3c 3c 01 40 83 05
166 00 00 00 00 00 00 00 00
167 00 00 00 00 00 00 00 00
168 00 00 00 00 00 00 00 00
169 00 00 00 00 0f 01 02 00
170 00 00 00 00 00 00 00 00
171 00 00 00 00 00 00 00 00
172 00 00 00 00 00 00 00 00
173 00 00 00 00 00 00 00 00
174 00 00 00 00 00 00 00 00
175 00 00 00 00 00 00 00 00
176 00 00 00 00 00 80 2c 00
177 00 00 00 00 00 00 ad 75
178 34 4b 54 46 32 35 36 36
179 34 48 5a 2d 31 47 36 45
180 31 20 45 31 80 2c 00 00
181 00 00 00 00 00 00 00 00
182 00 00 00 00 00 00 00 00
183 00 00 00 00 00 00 00 00
184 ff ff ff ff ff ff ff ff
185 ff ff ff ff ff ff ff ff
186 ff ff ff ff ff ff ff ff
187 ff ff ff ff ff ff ff ff
188 ff ff ff ff ff ff ff ff
189 ff ff ff ff ff ff ff ff
190 ff ff ff ff ff ff ff ff
191 ff ff ff ff ff ff ff ff
192 ff ff ff ff ff ff ff ff
193 ff ff ff ff ff ff ff ff];
194 };
195 };
196
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]197 pci {
Simon Glass582075c2016-01-17 16:11:41 -0700[diff] [blame]198 compatible = "pci-x86";
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame]199 #address-cells = <3>;
200 #size-cells = <2>;
201 u-boot,dm-pre-reloc;
202 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
203 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
204 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
Simon Glass061e9ea2016-01-17 16:11:15 -0700[diff] [blame]205
206 northbridge@0,0 {
207 reg = <0x00000000 0 0 0 0>;
208 compatible = "intel,bd82x6x-northbridge";
209 u-boot,dm-pre-reloc;
210 };
211
Simon Glass85ff0b12014-11-14 20:56:37 -0700[diff] [blame]212 gma {
213 compatible = "intel,gma";
214 intel,dp_hotplug = <0 0 0x06>;
215 intel,panel-port-select = <1>;
216 intel,panel-power-cycle-delay = <6>;
217 intel,panel-power-up-delay = <2000>;
218 intel,panel-power-down-delay = <500>;
219 intel,panel-power-backlight-on-delay = <2000>;
220 intel,panel-power-backlight-off-delay = <2000>;
221 intel,cpu-backlight = <0x00000200>;
222 intel,pch-backlight = <0x04000000>;
223 };
224
Simon Glass37a91ff2016-01-17 16:11:50 -0700[diff] [blame]225 me@16,0 {
226 reg = <0x0000b000 0 0 0 0>;
227 compatible = "intel,me";
228 u-boot,dm-pre-reloc;
229 };
230
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame^]231 usb_1: usb@1a,0 {
232 reg = <0x0000d000 0 0 0 0>;
233 compatible = "ehci-pci";
234 };
235
236 usb_0: usb@1d,0 {
237 reg = <0x0000e800 0 0 0 0>;
238 compatible = "ehci-pci";
239 };
240
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]241 pch@1f,0 {
Simon Glasse0e7b362015-03-05 12:25:33 -0700[diff] [blame]242 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]243 compatible = "intel,bd82x6x", "intel,pch9";
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]244 u-boot,dm-pre-reloc;
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]245 #address-cells = <1>;
246 #size-cells = <1>;
Simon Glassc1fd69e2014-11-14 18:18:37 -0700[diff] [blame]247 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
248 0x80 0x80 0x80 0x80>;
249 intel,gpi-routing = <0 0 0 0 0 0 0 2
250 1 0 0 0 0 0 0 0>;
251 /* Enable EC SMI source */
252 intel,alt-gp-smi-enable = <0x0100>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]253
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]254 spi {
255 #address-cells = <1>;
256 #size-cells = <0>;
257 compatible = "intel,ich-spi";
258 spi-flash@0 {
259 #size-cells = <1>;
260 #address-cells = <1>;
261 reg = <0>;
262 compatible = "winbond,w25q64",
263 "spi-flash";
264 memory-map = <0xff800000 0x00800000>;
265 rw-mrc-cache {
266 label = "rw-mrc-cache";
267 reg = <0x003e0000 0x00010000>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]268 };
269 };
270 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]271
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]272 lpc {
273 compatible = "intel,bd82x6x-lpc";
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]274 #address-cells = <1>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]275 #size-cells = <0>;
Simon Glass044f1a02016-01-17 16:11:10 -0700[diff] [blame]276 u-boot,dm-pre-reloc;
Simon Glass62b37172016-01-17 16:11:11 -0700[diff] [blame]277 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]278 cros-ec@200 {
279 compatible = "google,cros-ec";
280 reg = <0x204 1 0x200 1 0x880 0x80>;
281
282 /*
283 * Describes the flash memory within
284 * the EC
285 */
286 #address-cells = <1>;
287 #size-cells = <1>;
288 flash@8000000 {
289 reg = <0x08000000 0x20000>;
290 erase-value = <0xff>;
291 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]292 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]293 };
294 };
Simon Glass5cc400b2016-01-17 16:11:35 -0700[diff] [blame]295
296 sata@1f,2 {
297 compatible = "intel,pantherpoint-ahci";
298 reg = <0x0000fa00 0 0 0 0>;
299 u-boot,dm-pre-reloc;
300 intel,sata-mode = "ahci";
301 intel,sata-port-map = <1>;
302 intel,sata-port0-gen3-tx = <0x00880a7f>;
303 };
Simon Glass9afcd962016-01-17 16:11:45 -0700[diff] [blame]304
305 smbus: smbus@1f,3 {
306 compatible = "intel,ich-i2c";
307 reg = <0x0000fb00 0 0 0 0>;
308 u-boot,dm-pre-reloc;
309 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]310 };
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]311
Simon Glass11328532015-08-22 18:31:37 -0600[diff] [blame]312 tpm {
313 reg = <0xfed40000 0x5000>;
314 compatible = "infineon,slb9635lpc";
315 };
316
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]317 microcode {
318 update@0 {
Simon Glass44679e72014-12-15 22:02:40 -0700[diff] [blame]319#include "microcode/m12306a9_0000001b.dtsi"
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]320 };
321 };
322
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]323};