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git01.mediatek.com / filogic / uboot / 3356cad97a47da7c8338f49c39d45e45081d01a1 / . / arch / x86 / dts / chromebook_link.dts
blob: 7870bb172bf35521ad26a9e5c60b5c50dd890b2a [file] [log] [blame]
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]3/include/ "skeleton.dtsi"
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame^]4/include/ "keyboard.dtsi"
Bin Meng82db36c2014-12-24 13:06:38 +0800[diff] [blame]5/include/ "serial.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]6/include/ "rtc.dtsi"
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]7
8/ {
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]9 model = "Google Link";
10 compatible = "google,link", "intel,celeron-ivybridge";
11
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]12 aliases {
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]13 spi0 = "/pci/pch/spi";
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]14 };
15
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]16 config {
17 silent_console = <0>;
18 };
19
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]20 gpioa {
21 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]22 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]23 reg = <0 0x10>;
24 bank-name = "A";
25 };
26
27 gpiob {
28 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]29 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]30 reg = <0x30 0x10>;
31 bank-name = "B";
32 };
33
34 gpioc {
35 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]36 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]37 reg = <0x40 0x10>;
38 bank-name = "C";
39 };
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]40
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]41 chosen {
42 stdout-path = "/serial";
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]43 };
44
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame^]45 keyboard {
46 intel,duplicate-por;
47 };
48
Simon Glass268eefd2014-11-12 22:42:28 -0700[diff] [blame]49 spd {
50 compatible = "memory-spd";
51 #address-cells = <1>;
52 #size-cells = <0>;
53 elpida_4Gb_1600_x16 {
54 reg = <0>;
55 data = [92 10 0b 03 04 19 02 02
56 03 52 01 08 0a 00 fe 00
57 69 78 69 3c 69 11 18 81
58 20 08 3c 3c 01 40 83 81
59 00 00 00 00 00 00 00 00
60 00 00 00 00 00 00 00 00
61 00 00 00 00 00 00 00 00
62 00 00 00 00 0f 11 42 00
63 00 00 00 00 00 00 00 00
64 00 00 00 00 00 00 00 00
65 00 00 00 00 00 00 00 00
66 00 00 00 00 00 00 00 00
67 00 00 00 00 00 00 00 00
68 00 00 00 00 00 00 00 00
69 00 00 00 00 00 02 fe 00
70 11 52 00 00 00 07 7f 37
71 45 42 4a 32 30 55 47 36
72 45 42 55 30 2d 47 4e 2d
73 46 20 30 20 02 fe 00 00
74 00 00 00 00 00 00 00 00
75 00 00 00 00 00 00 00 00
76 00 00 00 00 00 00 00 00
77 00 00 00 00 00 00 00 00
78 00 00 00 00 00 00 00 00
79 00 00 00 00 00 00 00 00
80 00 00 00 00 00 00 00 00
81 00 00 00 00 00 00 00 00
82 00 00 00 00 00 00 00 00
83 00 00 00 00 00 00 00 00
84 00 00 00 00 00 00 00 00
85 00 00 00 00 00 00 00 00
86 00 00 00 00 00 00 00 00];
87 };
88 samsung_4Gb_1600_1.35v_x16 {
89 reg = <1>;
90 data = [92 11 0b 03 04 19 02 02
91 03 11 01 08 0a 00 fe 00
92 69 78 69 3c 69 11 18 81
93 f0 0a 3c 3c 01 40 83 01
94 00 80 00 00 00 00 00 00
95 00 00 00 00 00 00 00 00
96 00 00 00 00 00 00 00 00
97 00 00 00 00 0f 11 02 00
98 00 00 00 00 00 00 00 00
99 00 00 00 00 00 00 00 00
100 00 00 00 00 00 00 00 00
101 00 00 00 00 00 00 00 00
102 00 00 00 00 00 00 00 00
103 00 00 00 00 00 00 00 00
104 00 00 00 00 00 80 ce 01
105 00 00 00 00 00 00 6a 04
106 4d 34 37 31 42 35 36 37
107 34 42 48 30 2d 59 4b 30
108 20 20 00 00 80 ce 00 00
109 00 00 00 00 00 00 00 00
110 00 00 00 00 00 00 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 00 00 00 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00
116 00 00 00 00 00 00 00 00
117 00 00 00 00 00 00 00 00
118 00 00 00 00 00 00 00 00
119 00 00 00 00 00 00 00 00
120 00 00 00 00 00 00 00 00
121 00 00 00 00 00 00 00 00];
122 };
123 micron_4Gb_1600_1.35v_x16 {
124 reg = <2>;
125 data = [92 11 0b 03 04 19 02 02
126 03 11 01 08 0a 00 fe 00
127 69 78 69 3c 69 11 18 81
128 20 08 3c 3c 01 40 83 05
129 00 00 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00
131 00 00 00 00 00 00 00 00
132 00 00 00 00 0f 01 02 00
133 00 00 00 00 00 00 00 00
134 00 00 00 00 00 00 00 00
135 00 00 00 00 00 00 00 00
136 00 00 00 00 00 00 00 00
137 00 00 00 00 00 00 00 00
138 00 00 00 00 00 00 00 00
139 00 00 00 00 00 80 2c 00
140 00 00 00 00 00 00 ad 75
141 34 4b 54 46 32 35 36 36
142 34 48 5a 2d 31 47 36 45
143 31 20 45 31 80 2c 00 00
144 00 00 00 00 00 00 00 00
145 00 00 00 00 00 00 00 00
146 00 00 00 00 00 00 00 00
147 ff ff ff ff ff ff ff ff
148 ff ff ff ff ff ff ff ff
149 ff ff ff ff ff ff ff ff
150 ff ff ff ff ff ff ff ff
151 ff ff ff ff ff ff ff ff
152 ff ff ff ff ff ff ff ff
153 ff ff ff ff ff ff ff ff
154 ff ff ff ff ff ff ff ff
155 ff ff ff ff ff ff ff ff
156 ff ff ff ff ff ff ff ff];
157 };
158 };
159
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]160 pci {
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame]161 compatible = "intel,pci-ivybridge", "pci-x86";
162 #address-cells = <3>;
163 #size-cells = <2>;
164 u-boot,dm-pre-reloc;
165 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
166 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
167 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
Simon Glass585be5f2014-11-14 18:18:39 -0700[diff] [blame]168 sata {
169 compatible = "intel,pantherpoint-ahci";
170 intel,sata-mode = "ahci";
171 intel,sata-port-map = <1>;
172 intel,sata-port0-gen3-tx = <0x00880a7f>;
173 };
174
Simon Glass85ff0b12014-11-14 20:56:37 -0700[diff] [blame]175 gma {
176 compatible = "intel,gma";
177 intel,dp_hotplug = <0 0 0x06>;
178 intel,panel-port-select = <1>;
179 intel,panel-power-cycle-delay = <6>;
180 intel,panel-power-up-delay = <2000>;
181 intel,panel-power-down-delay = <500>;
182 intel,panel-power-backlight-on-delay = <2000>;
183 intel,panel-power-backlight-off-delay = <2000>;
184 intel,cpu-backlight = <0x00000200>;
185 intel,pch-backlight = <0x04000000>;
186 };
187
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]188 pch {
Simon Glasse0e7b362015-03-05 12:25:33 -0700[diff] [blame]189 reg = <0x0000f800 0 0 0 0>;
Simon Glass92784712015-04-20 07:07:03 -0600[diff] [blame]190 compatible = "intel,bd82x6x", "intel,pch";
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]191 u-boot,dm-pre-reloc;
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]192 #address-cells = <1>;
193 #size-cells = <1>;
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]194 gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glassc1fd69e2014-11-14 18:18:37 -0700[diff] [blame]195 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
196 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
197 0x80 0x80 0x80 0x80>;
198 intel,gpi-routing = <0 0 0 0 0 0 0 2
199 1 0 0 0 0 0 0 0>;
200 /* Enable EC SMI source */
201 intel,alt-gp-smi-enable = <0x0100>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]202 spi {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "intel,ich-spi";
206 spi-flash@0 {
207 #size-cells = <1>;
208 #address-cells = <1>;
209 reg = <0>;
210 compatible = "winbond,w25q64",
211 "spi-flash";
212 memory-map = <0xff800000 0x00800000>;
213 rw-mrc-cache {
214 label = "rw-mrc-cache";
215 reg = <0x003e0000 0x00010000>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]216 };
217 };
218 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]219
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]220 lpc {
221 compatible = "intel,bd82x6x-lpc";
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]222 #address-cells = <1>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]223 #size-cells = <0>;
224 cros-ec@200 {
225 compatible = "google,cros-ec";
226 reg = <0x204 1 0x200 1 0x880 0x80>;
227
228 /*
229 * Describes the flash memory within
230 * the EC
231 */
232 #address-cells = <1>;
233 #size-cells = <1>;
234 flash@8000000 {
235 reg = <0x08000000 0x20000>;
236 erase-value = <0xff>;
237 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]238 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]239 };
240 };
241 };
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]242
Simon Glass11328532015-08-22 18:31:37 -0600[diff] [blame]243 tpm {
244 reg = <0xfed40000 0x5000>;
245 compatible = "infineon,slb9635lpc";
246 };
247
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]248 microcode {
249 update@0 {
Simon Glass44679e72014-12-15 22:02:40 -0700[diff] [blame]250#include "microcode/m12306a9_0000001b.dtsi"
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]251 };
252 };
253
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]254};