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git01.mediatek.com / filogic / uboot / 585be5ffb9ed834a4f47cb393047f31e89964e59 / . / arch / x86 / dts / link.dts
blob: d3c94e0e58c4a6b2ed1dd5892b6ba58a7c0745bc [file] [log] [blame]
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Stephen Warren3f972cc2013-07-24 10:09:20 -0700[diff] [blame]3/include/ "coreboot.dtsi"
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]4
5/ {
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200[diff] [blame]6 #address-cells = <1>;
7 #size-cells = <1>;
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]8 model = "Google Link";
9 compatible = "google,link", "intel,celeron-ivybridge";
10
11 config {
12 silent_console = <0>;
13 };
14
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]15 gpioa {
16 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]17 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]18 reg = <0 0x10>;
19 bank-name = "A";
20 };
21
22 gpiob {
23 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]24 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]25 reg = <0x30 0x10>;
26 bank-name = "B";
27 };
28
29 gpioc {
30 compatible = "intel,ich6-gpio";
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]31 u-boot,dm-pre-reloc;
Simon Glass1fad1462014-10-10 07:49:19 -0600[diff] [blame]32 reg = <0x40 0x10>;
33 bank-name = "C";
34 };
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]35
36 serial {
37 reg = <0x3f8 8>;
38 clock-frequency = <115200>;
39 };
40
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200[diff] [blame]41 chosen { };
42 memory { device_type = "memory"; reg = <0 0>; };
Simon Glass87323ed2013-03-11 06:08:10 +0000[diff] [blame]43
Simon Glass268eefd2014-11-12 22:42:28 -0700[diff] [blame]44 spd {
45 compatible = "memory-spd";
46 #address-cells = <1>;
47 #size-cells = <0>;
48 elpida_4Gb_1600_x16 {
49 reg = <0>;
50 data = [92 10 0b 03 04 19 02 02
51 03 52 01 08 0a 00 fe 00
52 69 78 69 3c 69 11 18 81
53 20 08 3c 3c 01 40 83 81
54 00 00 00 00 00 00 00 00
55 00 00 00 00 00 00 00 00
56 00 00 00 00 00 00 00 00
57 00 00 00 00 0f 11 42 00
58 00 00 00 00 00 00 00 00
59 00 00 00 00 00 00 00 00
60 00 00 00 00 00 00 00 00
61 00 00 00 00 00 00 00 00
62 00 00 00 00 00 00 00 00
63 00 00 00 00 00 00 00 00
64 00 00 00 00 00 02 fe 00
65 11 52 00 00 00 07 7f 37
66 45 42 4a 32 30 55 47 36
67 45 42 55 30 2d 47 4e 2d
68 46 20 30 20 02 fe 00 00
69 00 00 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00
71 00 00 00 00 00 00 00 00
72 00 00 00 00 00 00 00 00
73 00 00 00 00 00 00 00 00
74 00 00 00 00 00 00 00 00
75 00 00 00 00 00 00 00 00
76 00 00 00 00 00 00 00 00
77 00 00 00 00 00 00 00 00
78 00 00 00 00 00 00 00 00
79 00 00 00 00 00 00 00 00
80 00 00 00 00 00 00 00 00
81 00 00 00 00 00 00 00 00];
82 };
83 samsung_4Gb_1600_1.35v_x16 {
84 reg = <1>;
85 data = [92 11 0b 03 04 19 02 02
86 03 11 01 08 0a 00 fe 00
87 69 78 69 3c 69 11 18 81
88 f0 0a 3c 3c 01 40 83 01
89 00 80 00 00 00 00 00 00
90 00 00 00 00 00 00 00 00
91 00 00 00 00 00 00 00 00
92 00 00 00 00 0f 11 02 00
93 00 00 00 00 00 00 00 00
94 00 00 00 00 00 00 00 00
95 00 00 00 00 00 00 00 00
96 00 00 00 00 00 00 00 00
97 00 00 00 00 00 00 00 00
98 00 00 00 00 00 00 00 00
99 00 00 00 00 00 80 ce 01
100 00 00 00 00 00 00 6a 04
101 4d 34 37 31 42 35 36 37
102 34 42 48 30 2d 59 4b 30
103 20 20 00 00 80 ce 00 00
104 00 00 00 00 00 00 00 00
105 00 00 00 00 00 00 00 00
106 00 00 00 00 00 00 00 00
107 00 00 00 00 00 00 00 00
108 00 00 00 00 00 00 00 00
109 00 00 00 00 00 00 00 00
110 00 00 00 00 00 00 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 00 00 00 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00
116 00 00 00 00 00 00 00 00];
117 };
118 micron_4Gb_1600_1.35v_x16 {
119 reg = <2>;
120 data = [92 11 0b 03 04 19 02 02
121 03 11 01 08 0a 00 fe 00
122 69 78 69 3c 69 11 18 81
123 20 08 3c 3c 01 40 83 05
124 00 00 00 00 00 00 00 00
125 00 00 00 00 00 00 00 00
126 00 00 00 00 00 00 00 00
127 00 00 00 00 0f 01 02 00
128 00 00 00 00 00 00 00 00
129 00 00 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00
131 00 00 00 00 00 00 00 00
132 00 00 00 00 00 00 00 00
133 00 00 00 00 00 00 00 00
134 00 00 00 00 00 80 2c 00
135 00 00 00 00 00 00 ad 75
136 34 4b 54 46 32 35 36 36
137 34 48 5a 2d 31 47 36 45
138 31 20 45 31 80 2c 00 00
139 00 00 00 00 00 00 00 00
140 00 00 00 00 00 00 00 00
141 00 00 00 00 00 00 00 00
142 ff ff ff ff ff ff ff ff
143 ff ff ff ff ff ff ff ff
144 ff ff ff ff ff ff ff ff
145 ff ff ff ff ff ff ff ff
146 ff ff ff ff ff ff ff ff
147 ff ff ff ff ff ff ff ff
148 ff ff ff ff ff ff ff ff
149 ff ff ff ff ff ff ff ff
150 ff ff ff ff ff ff ff ff
151 ff ff ff ff ff ff ff ff];
152 };
153 };
154
Simon Glass87323ed2013-03-11 06:08:10 +0000[diff] [blame]155 spi {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "intel,ich9";
159 spi-flash@0 {
160 reg = <0>;
161 compatible = "winbond,w25q64", "spi-flash";
162 memory-map = <0xff800000 0x00800000>;
163 };
164 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]165
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]166 pci {
Simon Glass585be5f2014-11-14 18:18:39 -0700[diff] [blame^]167 sata {
168 compatible = "intel,pantherpoint-ahci";
169 intel,sata-mode = "ahci";
170 intel,sata-port-map = <1>;
171 intel,sata-port0-gen3-tx = <0x00880a7f>;
172 };
173
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]174 lpc {
175 compatible = "intel,lpc";
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]176 #address-cells = <1>;
177 #size-cells = <1>;
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]178 gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glassc1fd69e2014-11-14 18:18:37 -0700[diff] [blame]179 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
180 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
181 0x80 0x80 0x80 0x80>;
182 intel,gpi-routing = <0 0 0 0 0 0 0 2
183 1 0 0 0 0 0 0 0>;
184 /* Enable EC SMI source */
185 intel,alt-gp-smi-enable = <0x0100>;
186
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]187 cros-ec@200 {
188 compatible = "google,cros-ec";
189 reg = <0x204 1 0x200 1 0x880 0x80>;
190
191 /* Describes the flash memory within the EC */
192 #address-cells = <1>;
193 #size-cells = <1>;
194 flash@8000000 {
195 reg = <0x08000000 0x20000>;
196 erase-value = <0xff>;
197 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]198 };
199 };
200 };
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]201
202 microcode {
203 update@0 {
204#include "m12206a7_00000028.dtsi"
205 };
206 update@1 {
207#include "m12306a9_00000017.dtsi"
208 };
209 };
210
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]211};