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git01.mediatek.com / filogic / uboot / 6e916cc19dbaf23351a95b5dc08c756d99d8454e / . / arch / x86 / dts / chromebook_link.dts
blob: f85e55cd6d542a2661417ed61a140648fdf96ed4 [file] [log] [blame]
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]3/include/ "skeleton.dtsi"
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]4/include/ "keyboard.dtsi"
Bin Meng82db36c2014-12-24 13:06:38 +0800[diff] [blame]5/include/ "serial.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +0800[diff] [blame]6/include/ "rtc.dtsi"
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]7/include/ "tsc_timer.dtsi"
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]8
9/ {
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]10 model = "Google Link";
11 compatible = "google,link", "intel,celeron-ivybridge";
12
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]13 aliases {
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]14 spi0 = &spi;
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame]15 usb0 = &usb_0;
16 usb1 = &usb_1;
Simon Glass7f9f6a92015-01-19 22:16:13 -0700[diff] [blame]17 };
18
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]19 config {
20 silent_console = <0>;
21 };
22
Simon Glassb4974c42016-01-17 16:11:23 -0700[diff] [blame]23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "intel,core-gen3";
30 reg = <0>;
31 intel,apic-id = <0>;
32 };
33
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "intel,core-gen3";
37 reg = <1>;
38 intel,apic-id = <1>;
39 };
40
41 cpu@2 {
42 device_type = "cpu";
43 compatible = "intel,core-gen3";
44 reg = <2>;
45 intel,apic-id = <2>;
46 };
47
48 cpu@3 {
49 device_type = "cpu";
50 compatible = "intel,core-gen3";
51 reg = <3>;
52 intel,apic-id = <3>;
53 };
54
55 };
56
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]57 chosen {
58 stdout-path = "/serial";
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]59 };
60
Simon Glass3356cad2015-11-11 10:05:43 -0700[diff] [blame]61 keyboard {
62 intel,duplicate-por;
63 };
64
Simon Glass268eefd2014-11-12 22:42:28 -0700[diff] [blame]65 spd {
66 compatible = "memory-spd";
67 #address-cells = <1>;
68 #size-cells = <0>;
69 elpida_4Gb_1600_x16 {
70 reg = <0>;
71 data = [92 10 0b 03 04 19 02 02
72 03 52 01 08 0a 00 fe 00
73 69 78 69 3c 69 11 18 81
74 20 08 3c 3c 01 40 83 81
75 00 00 00 00 00 00 00 00
76 00 00 00 00 00 00 00 00
77 00 00 00 00 00 00 00 00
78 00 00 00 00 0f 11 42 00
79 00 00 00 00 00 00 00 00
80 00 00 00 00 00 00 00 00
81 00 00 00 00 00 00 00 00
82 00 00 00 00 00 00 00 00
83 00 00 00 00 00 00 00 00
84 00 00 00 00 00 00 00 00
85 00 00 00 00 00 02 fe 00
86 11 52 00 00 00 07 7f 37
87 45 42 4a 32 30 55 47 36
88 45 42 55 30 2d 47 4e 2d
89 46 20 30 20 02 fe 00 00
90 00 00 00 00 00 00 00 00
91 00 00 00 00 00 00 00 00
92 00 00 00 00 00 00 00 00
93 00 00 00 00 00 00 00 00
94 00 00 00 00 00 00 00 00
95 00 00 00 00 00 00 00 00
96 00 00 00 00 00 00 00 00
97 00 00 00 00 00 00 00 00
98 00 00 00 00 00 00 00 00
99 00 00 00 00 00 00 00 00
100 00 00 00 00 00 00 00 00
101 00 00 00 00 00 00 00 00
102 00 00 00 00 00 00 00 00];
103 };
104 samsung_4Gb_1600_1.35v_x16 {
105 reg = <1>;
106 data = [92 11 0b 03 04 19 02 02
107 03 11 01 08 0a 00 fe 00
108 69 78 69 3c 69 11 18 81
109 f0 0a 3c 3c 01 40 83 01
110 00 80 00 00 00 00 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 0f 11 02 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00
116 00 00 00 00 00 00 00 00
117 00 00 00 00 00 00 00 00
118 00 00 00 00 00 00 00 00
119 00 00 00 00 00 00 00 00
120 00 00 00 00 00 80 ce 01
121 00 00 00 00 00 00 6a 04
122 4d 34 37 31 42 35 36 37
123 34 42 48 30 2d 59 4b 30
124 20 20 00 00 80 ce 00 00
125 00 00 00 00 00 00 00 00
126 00 00 00 00 00 00 00 00
127 00 00 00 00 00 00 00 00
128 00 00 00 00 00 00 00 00
129 00 00 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00
131 00 00 00 00 00 00 00 00
132 00 00 00 00 00 00 00 00
133 00 00 00 00 00 00 00 00
134 00 00 00 00 00 00 00 00
135 00 00 00 00 00 00 00 00
136 00 00 00 00 00 00 00 00
137 00 00 00 00 00 00 00 00];
138 };
139 micron_4Gb_1600_1.35v_x16 {
140 reg = <2>;
141 data = [92 11 0b 03 04 19 02 02
142 03 11 01 08 0a 00 fe 00
143 69 78 69 3c 69 11 18 81
144 20 08 3c 3c 01 40 83 05
145 00 00 00 00 00 00 00 00
146 00 00 00 00 00 00 00 00
147 00 00 00 00 00 00 00 00
148 00 00 00 00 0f 01 02 00
149 00 00 00 00 00 00 00 00
150 00 00 00 00 00 00 00 00
151 00 00 00 00 00 00 00 00
152 00 00 00 00 00 00 00 00
153 00 00 00 00 00 00 00 00
154 00 00 00 00 00 00 00 00
155 00 00 00 00 00 80 2c 00
156 00 00 00 00 00 00 ad 75
157 34 4b 54 46 32 35 36 36
158 34 48 5a 2d 31 47 36 45
159 31 20 45 31 80 2c 00 00
160 00 00 00 00 00 00 00 00
161 00 00 00 00 00 00 00 00
162 00 00 00 00 00 00 00 00
163 ff ff ff ff ff ff ff ff
164 ff ff ff ff ff ff ff ff
165 ff ff ff ff ff ff ff ff
166 ff ff ff ff ff ff ff ff
167 ff ff ff ff ff ff ff ff
168 ff ff ff ff ff ff ff ff
169 ff ff ff ff ff ff ff ff
170 ff ff ff ff ff ff ff ff
171 ff ff ff ff ff ff ff ff
172 ff ff ff ff ff ff ff ff];
173 };
174 };
175
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]176 pci {
Simon Glass582075c2016-01-17 16:11:41 -0700[diff] [blame]177 compatible = "pci-x86";
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame]178 #address-cells = <3>;
179 #size-cells = <2>;
180 u-boot,dm-pre-reloc;
181 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
182 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
183 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
Simon Glass061e9ea2016-01-17 16:11:15 -0700[diff] [blame]184
185 northbridge@0,0 {
186 reg = <0x00000000 0 0 0 0>;
187 compatible = "intel,bd82x6x-northbridge";
188 u-boot,dm-pre-reloc;
189 };
190
Simon Glassa75abeb2016-01-17 16:11:59 -0700[diff] [blame]191 gma@2,0 {
192 reg = <0x00001000 0 0 0 0>;
Simon Glass85ff0b12014-11-14 20:56:37 -0700[diff] [blame]193 compatible = "intel,gma";
194 intel,dp_hotplug = <0 0 0x06>;
195 intel,panel-port-select = <1>;
196 intel,panel-power-cycle-delay = <6>;
197 intel,panel-power-up-delay = <2000>;
198 intel,panel-power-down-delay = <500>;
199 intel,panel-power-backlight-on-delay = <2000>;
200 intel,panel-power-backlight-off-delay = <2000>;
201 intel,cpu-backlight = <0x00000200>;
202 intel,pch-backlight = <0x04000000>;
203 };
204
Simon Glass37a91ff2016-01-17 16:11:50 -0700[diff] [blame]205 me@16,0 {
206 reg = <0x0000b000 0 0 0 0>;
207 compatible = "intel,me";
208 u-boot,dm-pre-reloc;
209 };
210
Simon Glass74a9e6a2016-01-17 16:11:55 -0700[diff] [blame]211 usb_1: usb@1a,0 {
212 reg = <0x0000d000 0 0 0 0>;
213 compatible = "ehci-pci";
214 };
215
216 usb_0: usb@1d,0 {
217 reg = <0x0000e800 0 0 0 0>;
218 compatible = "ehci-pci";
219 };
220
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]221 pch@1f,0 {
Simon Glasse0e7b362015-03-05 12:25:33 -0700[diff] [blame]222 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]223 compatible = "intel,bd82x6x", "intel,pch9";
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]224 u-boot,dm-pre-reloc;
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]225 #address-cells = <1>;
226 #size-cells = <1>;
Simon Glassc1fd69e2014-11-14 18:18:37 -0700[diff] [blame]227 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
228 0x80 0x80 0x80 0x80>;
229 intel,gpi-routing = <0 0 0 0 0 0 0 2
230 1 0 0 0 0 0 0 0>;
231 /* Enable EC SMI source */
232 intel,alt-gp-smi-enable = <0x0100>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]233
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]234 spi: spi {
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]235 #address-cells = <1>;
236 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -0800[diff] [blame]237 compatible = "intel,ich9-spi";
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]238 spi-flash@0 {
239 #size-cells = <1>;
240 #address-cells = <1>;
241 reg = <0>;
242 compatible = "winbond,w25q64",
243 "spi-flash";
244 memory-map = <0xff800000 0x00800000>;
245 rw-mrc-cache {
246 label = "rw-mrc-cache";
247 reg = <0x003e0000 0x00010000>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]248 };
249 };
250 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]251
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame^]252 gpioa {
253 compatible = "intel,ich6-gpio";
254 u-boot,dm-pre-reloc;
255 reg = <0 0x10>;
256 bank-name = "A";
257 };
258
259 gpiob {
260 compatible = "intel,ich6-gpio";
261 u-boot,dm-pre-reloc;
262 reg = <0x30 0x10>;
263 bank-name = "B";
264 };
265
266 gpioc {
267 compatible = "intel,ich6-gpio";
268 u-boot,dm-pre-reloc;
269 reg = <0x40 0x10>;
270 bank-name = "C";
271 };
272
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]273 lpc {
274 compatible = "intel,bd82x6x-lpc";
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]275 #address-cells = <1>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]276 #size-cells = <0>;
Simon Glass044f1a02016-01-17 16:11:10 -0700[diff] [blame]277 u-boot,dm-pre-reloc;
Simon Glass62b37172016-01-17 16:11:11 -0700[diff] [blame]278 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glass06e694f2015-03-26 09:29:29 -0600[diff] [blame]279 cros-ec@200 {
280 compatible = "google,cros-ec";
281 reg = <0x204 1 0x200 1 0x880 0x80>;
282
283 /*
284 * Describes the flash memory within
285 * the EC
286 */
287 #address-cells = <1>;
288 #size-cells = <1>;
289 flash@8000000 {
290 reg = <0x08000000 0x20000>;
291 erase-value = <0xff>;
292 };
Simon Glasseec39ba2014-11-14 18:18:36 -0700[diff] [blame]293 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]294 };
295 };
Simon Glass5cc400b2016-01-17 16:11:35 -0700[diff] [blame]296
297 sata@1f,2 {
298 compatible = "intel,pantherpoint-ahci";
299 reg = <0x0000fa00 0 0 0 0>;
300 u-boot,dm-pre-reloc;
301 intel,sata-mode = "ahci";
302 intel,sata-port-map = <1>;
303 intel,sata-port0-gen3-tx = <0x00880a7f>;
304 };
Simon Glass9afcd962016-01-17 16:11:45 -0700[diff] [blame]305
306 smbus: smbus@1f,3 {
307 compatible = "intel,ich-i2c";
308 reg = <0x0000fb00 0 0 0 0>;
309 u-boot,dm-pre-reloc;
310 };
Simon Glasse4e56272014-10-10 07:30:13 -0600[diff] [blame]311 };
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]312
Simon Glass11328532015-08-22 18:31:37 -0600[diff] [blame]313 tpm {
314 reg = <0xfed40000 0x5000>;
315 compatible = "infineon,slb9635lpc";
316 };
317
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]318 microcode {
319 update@0 {
Simon Glass44679e72014-12-15 22:02:40 -0700[diff] [blame]320#include "microcode/m12306a9_0000001b.dtsi"
Simon Glass0c84eec2014-11-12 22:42:22 -0700[diff] [blame]321 };
322 };
323
Simon Glass791f61b2012-12-03 13:56:51 +0000[diff] [blame]324};