blob: d7065a80e23abb49187b098954915521566dc597 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton32464372016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +010010
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergerf0699602015-05-12 14:46:23 -050013 optional
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090014
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090015config TARGET_MALTA
16 bool "Support malta"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020017 select HAS_FIXED_TIMER_FREQUENCY
Daniel Schwierzeck45f78be2021-07-15 20:54:01 +020018 select BOARD_EARLY_INIT_R
Paul Burtona31a3df2016-05-17 07:43:28 +010019 select DM
20 select DM_SERIAL
Simon Glass3933d292021-08-01 18:54:44 -060021 select PCI
Paul Burton8d6600b2016-01-29 13:54:52 +000022 select DYNAMIC_IO_PORT_BASE
Paul Burton59a4c8b2016-09-21 11:18:56 +010023 select MIPS_CM
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +020024 select MIPS_INSERT_BOOT_CONFIG
Tom Rini3ef67ae2021-08-26 11:47:59 -040025 select SYS_CACHE_SHIFT_6
Paul Burton59a4c8b2016-09-21 11:18:56 +010026 select MIPS_L2_CACHE
Paul Burtona31a3df2016-05-17 07:43:28 +010027 select OF_CONTROL
28 select OF_ISA_BUS
Daniel Schwierzeck45f78be2021-07-15 20:54:01 +020029 select PCI_MAP_SYSTEM_MEMORY
Michal Simek84f3dec2018-07-23 15:55:13 +020030 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck256034d2014-10-26 14:14:07 +010031 select SUPPORTS_CPU_MIPS32_R1
32 select SUPPORTS_CPU_MIPS32_R2
Paul Burton1c10e0d2016-05-16 10:52:14 +010033 select SUPPORTS_CPU_MIPS32_R6
Paul Burton825cfbd2016-05-26 14:49:36 +010034 select SUPPORTS_CPU_MIPS64_R1
35 select SUPPORTS_CPU_MIPS64_R2
36 select SUPPORTS_CPU_MIPS64_R6
Jiaxun Yang33e289a2024-07-17 16:07:02 +080037 select SUPPORT_BIG_ENDIAN
38 select SUPPORT_LITTLE_ENDIAN
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +010039 select SWAP_IO_SPACE
Michal Simek2e7c8192018-07-23 15:55:14 +020040 imply CMD_DM
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090041
Wills Wang833a1a82016-03-16 16:59:52 +080042config ARCH_ATH79
43 bool "Support QCA/Atheros ath79"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020044 select HAS_FIXED_TIMER_FREQUENCY
Wills Wang833a1a82016-03-16 16:59:52 +080045 select DM
Michal Simek84f3dec2018-07-23 15:55:13 +020046 select OF_CONTROL
Michal Simek2e7c8192018-07-23 15:55:14 +020047 imply CMD_DM
Wills Wang833a1a82016-03-16 16:59:52 +080048
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010049config ARCH_MSCC
50 bool "Support MSCC VCore-III"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020051 select HAS_FIXED_TIMER_FREQUENCY
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010052 select OF_CONTROL
53 select DM
54
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020055config ARCH_BMIPS
56 bool "Support BMIPS SoCs"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020057 select HAS_FIXED_TIMER_FREQUENCY
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020058 select CLK
59 select CPU
Michal Simek84f3dec2018-07-23 15:55:13 +020060 select DM
61 select OF_CONTROL
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020062 select RAM
63 select SYSRESET
Michal Simek2e7c8192018-07-23 15:55:14 +020064 imply CMD_DM
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020065
developer89f051b2019-04-30 11:13:58 +080066config ARCH_MTMIPS
67 bool "Support MediaTek MIPS platforms"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020068 select HAS_FIXED_TIMER_FREQUENCY
developer591826e2019-09-25 17:45:43 +080069 select CLK
Stefan Roese65da15e2018-09-05 15:12:35 +020070 imply CMD_DM
71 select DISPLAY_CPUINFO
72 select DM
Stefan Roese8bbb6bf2018-10-09 08:59:09 +020073 imply DM_GPIO
developer591826e2019-09-25 17:45:43 +080074 select DM_RESET
Stefan Roese65da15e2018-09-05 15:12:35 +020075 select DM_SERIAL
developer591826e2019-09-25 17:45:43 +080076 select PINCTRL
77 select PINMUX
78 select PINCONF
79 select RESET_MTMIPS
Tom Riniddb1ec12024-01-10 13:46:10 -050080 imply MTD
Stefan Roese65da15e2018-09-05 15:12:35 +020081 imply DM_SPI
82 imply DM_SPI_FLASH
Stefan Roese17679e42019-05-28 08:11:37 +020083 select LAST_STAGE_INIT
Stefan Roese65da15e2018-09-05 15:12:35 +020084 select MIPS_TUNE_24KC
85 select OF_CONTROL
86 select ROM_EXCEPTION_VECTORS
87 select SUPPORTS_CPU_MIPS32_R1
88 select SUPPORTS_CPU_MIPS32_R2
Jiaxun Yang33e289a2024-07-17 16:07:02 +080089 select SUPPORT_LITTLE_ENDIAN
developer19d572e2020-04-21 09:28:47 +020090 select SUPPORT_SPL
Stefan Roese65da15e2018-09-05 15:12:35 +020091
Paul Burton96c68472018-12-16 19:25:22 -030092config ARCH_JZ47XX
93 bool "Support Ingenic JZ47xx"
94 select SUPPORT_SPL
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020095 select HAS_FIXED_TIMER_FREQUENCY
Paul Burton96c68472018-12-16 19:25:22 -030096 select OF_CONTROL
97 select DM
98
Aaron Williamsb2ea8182020-06-30 12:08:56 +020099config ARCH_OCTEON
100 bool "Support Marvell Octeon CN7xxx platforms"
Stefan Roese59735ef2022-04-07 09:11:46 +0200101 select ARCH_EARLY_INIT_R
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200102 select CPU_CAVIUM_OCTEON
103 select DISPLAY_CPUINFO
104 select DMA_ADDR_T_64BIT
105 select DM
Stefan Roese67b9edb2020-07-30 13:56:21 +0200106 select DM_GPIO
107 select DM_I2C
108 select DM_SERIAL
109 select DM_SPI
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200110 select MIPS_L2_CACHE
Stefan Roese15ba8022020-06-30 12:33:17 +0200111 select MIPS_MACH_EARLY_INIT
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200112 select MIPS_TUNE_OCTEON3
Tom Riniddb1ec12024-01-10 13:46:10 -0500113 select MTD
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200114 select ROM_EXCEPTION_VECTORS
Jiaxun Yang33e289a2024-07-17 16:07:02 +0800115 select SUPPORT_BIG_ENDIAN
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200116 select SUPPORTS_CPU_MIPS64_OCTEON
117 select PHYS_64BIT
118 select OF_CONTROL
119 select OF_LIVE
120 imply CMD_DM
121
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530122config MACH_PIC32
123 bool "Support Microchip PIC32"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200124 select HAS_FIXED_TIMER_FREQUENCY
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530125 select DM
Tom Rini7d3684a2023-01-16 15:46:49 -0500126 select DM_EVENT
Michal Simek84f3dec2018-07-23 15:55:13 +0200127 select OF_CONTROL
Michal Simek2e7c8192018-07-23 15:55:14 +0200128 imply CMD_DM
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530129
Paul Burtonf5de32a2016-09-08 07:47:39 +0100130config TARGET_BOSTON
131 bool "Support Boston"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200132 select HAS_FIXED_TIMER_FREQUENCY
Paul Burtonf5de32a2016-09-08 07:47:39 +0100133 select DM
134 select DM_SERIAL
Paul Burtonf5de32a2016-09-08 07:47:39 +0100135 select MIPS_CM
Tom Rini3ef67ae2021-08-26 11:47:59 -0400136 select SYS_CACHE_SHIFT_6
Paul Burtonf5de32a2016-09-08 07:47:39 +0100137 select MIPS_L2_CACHE
Paul Burtona315bcd2017-04-30 21:22:42 +0200138 select OF_BOARD_SETUP
Michal Simek84f3dec2018-07-23 15:55:13 +0200139 select OF_CONTROL
140 select ROM_EXCEPTION_VECTORS
Paul Burtonf5de32a2016-09-08 07:47:39 +0100141 select SUPPORTS_CPU_MIPS32_R1
142 select SUPPORTS_CPU_MIPS32_R2
143 select SUPPORTS_CPU_MIPS32_R6
144 select SUPPORTS_CPU_MIPS64_R1
145 select SUPPORTS_CPU_MIPS64_R2
146 select SUPPORTS_CPU_MIPS64_R6
Jiaxun Yang33e289a2024-07-17 16:07:02 +0800147 select SUPPORT_BIG_ENDIAN
148 select SUPPORT_LITTLE_ENDIAN
Michal Simek2e7c8192018-07-23 15:55:14 +0200149 imply CMD_DM
Paul Burtonf5de32a2016-09-08 07:47:39 +0100150
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100151config TARGET_XILFPGA
152 bool "Support Imagination Xilfpga"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200153 select HAS_FIXED_TIMER_FREQUENCY
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100154 select DM
Michal Simek84f3dec2018-07-23 15:55:13 +0200155 select DM_GPIO
156 select DM_SERIAL
Tom Rini3ef67ae2021-08-26 11:47:59 -0400157 select SYS_CACHE_SHIFT_4
Michal Simek84f3dec2018-07-23 15:55:13 +0200158 select OF_CONTROL
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100159 select ROM_EXCEPTION_VECTORS
Michal Simek84f3dec2018-07-23 15:55:13 +0200160 select SUPPORTS_CPU_MIPS32_R1
161 select SUPPORTS_CPU_MIPS32_R2
Jiaxun Yang33e289a2024-07-17 16:07:02 +0800162 select SUPPORT_LITTLE_ENDIAN
Michal Simek2e7c8192018-07-23 15:55:14 +0200163 imply CMD_DM
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100164 help
165 This supports IMGTEC MIPSfpga platform
166
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900167endchoice
168
Paul Burtonf5de32a2016-09-08 07:47:39 +0100169source "board/imgtec/boston/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900170source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100171source "board/imgtec/xilfpga/Kconfig"
Wills Wang833a1a82016-03-16 16:59:52 +0800172source "arch/mips/mach-ath79/Kconfig"
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +0100173source "arch/mips/mach-mscc/Kconfig"
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +0200174source "arch/mips/mach-bmips/Kconfig"
Paul Burton96c68472018-12-16 19:25:22 -0300175source "arch/mips/mach-jz47xx/Kconfig"
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530176source "arch/mips/mach-pic32/Kconfig"
developer89f051b2019-04-30 11:13:58 +0800177source "arch/mips/mach-mtmips/Kconfig"
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200178source "arch/mips/mach-octeon/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900179
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100180if MIPS
181
182choice
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100183 prompt "CPU selection"
184 default CPU_MIPS32_R2
185
186config CPU_MIPS32_R1
187 bool "MIPS32 Release 1"
188 depends on SUPPORTS_CPU_MIPS32_R1
189 select 32BIT
190 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100191 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100192 MIPS32 architecture.
193
194config CPU_MIPS32_R2
195 bool "MIPS32 Release 2"
196 depends on SUPPORTS_CPU_MIPS32_R2
197 select 32BIT
198 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100199 Choose this option to build an U-Boot for release 2 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100200 MIPS32 architecture.
201
Paul Burton55e29dd2016-05-16 10:52:12 +0100202config CPU_MIPS32_R6
203 bool "MIPS32 Release 6"
204 depends on SUPPORTS_CPU_MIPS32_R6
205 select 32BIT
206 help
207 Choose this option to build an U-Boot for release 6 or later of the
208 MIPS32 architecture.
209
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100210config CPU_MIPS64_R1
211 bool "MIPS64 Release 1"
212 depends on SUPPORTS_CPU_MIPS64_R1
213 select 64BIT
Andrew Goodbody5b5322c2024-12-16 18:07:35 +0000214 select SPL_64BIT if SPL
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100215 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100216 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100217 MIPS64 architecture.
218
219config CPU_MIPS64_R2
220 bool "MIPS64 Release 2"
221 depends on SUPPORTS_CPU_MIPS64_R2
222 select 64BIT
Andrew Goodbody5b5322c2024-12-16 18:07:35 +0000223 select SPL_64BIT if SPL
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100224 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100225 Choose this option to build a kernel for release 2 through 5 of the
226 MIPS64 architecture.
227
228config CPU_MIPS64_R6
229 bool "MIPS64 Release 6"
230 depends on SUPPORTS_CPU_MIPS64_R6
231 select 64BIT
Andrew Goodbody5b5322c2024-12-16 18:07:35 +0000232 select SPL_64BIT if SPL
Paul Burton55e29dd2016-05-16 10:52:12 +0100233 help
234 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100235 MIPS64 architecture.
236
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200237config CPU_MIPS64_OCTEON
238 bool "Marvell Octeon series of CPUs"
239 depends on SUPPORTS_CPU_MIPS64_OCTEON
240 select 64BIT
Andrew Goodbody5b5322c2024-12-16 18:07:35 +0000241 select SPL_64BIT if SPL
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200242 help
243 Choose this option for Marvell Octeon CPUs. These CPUs are between
244 MIPS64 R5 and R6 with other extensions.
245
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100246endchoice
247
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100248menu "General setup"
249
250config ROM_EXCEPTION_VECTORS
251 bool "Build U-Boot image with exception vectors"
252 help
253 Enable this to include exception vectors in the U-Boot image. This is
254 required if the U-Boot entry point is equal to the address of the
255 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
256 U-Boot booted from parallel NOR flash).
257 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
258 In that case the image size will be reduced by 0x500 bytes.
259
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200260config SYS_MIPS_TIMER_FREQ
261 int "Fixed MIPS CPU timer frequency in Hz"
262 depends on HAS_FIXED_TIMER_FREQUENCY
263 help
264 Configures a fixed CPU timer frequency.
265
Paul Burton3d6864a2017-05-12 13:26:11 +0200266config MIPS_CM_BASE
267 hex "MIPS CM GCR Base Address"
268 depends on MIPS_CM
Paul Burtona6ac9652017-04-30 21:22:41 +0200269 default 0x16100000 if TARGET_BOSTON
Paul Burton3d6864a2017-05-12 13:26:11 +0200270 default 0x1fbf8000
271 help
272 The physical base address at which to map the MIPS Coherence Manager
273 Global Configuration Registers (GCRs). This should be set such that
274 the GCRs occupy a region of the physical address space which is
275 otherwise unused, or at minimum that software doesn't need to access.
276
Daniel Schwierzecke3b432d2018-09-07 19:02:05 +0200277config MIPS_CACHE_INDEX_BASE
278 hex "Index base address for cache initialisation"
279 default 0x80000000 if CPU_MIPS32
280 default 0xffffffff80000000 if CPU_MIPS64
281 help
282 This is the base address for a memory block, which is used for
283 initialising the cache lines. This is also the base address of a memory
284 block which is used for loading and filling cache lines when
285 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
286 Normally this is CKSEG0. If the MIPS system needs to move this block
287 to some SRAM or ScratchPad RAM, adapt this option accordingly.
288
Stefan Roesec6f54b42020-06-30 12:33:16 +0200289config MIPS_MACH_EARLY_INIT
290 bool "Enable mach specific very early init code"
291 help
292 Use this to enable the call to mips_mach_early_init() very early
293 from start.S. This function can be used e.g. to do some very early
294 CPU / SoC intitialization or image copying. Its called very early
295 and at this stage the PC might not match the linking address
296 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
297
Daniel Schwierzeckc95e7f12020-07-12 00:45:57 +0200298config MIPS_CACHE_SETUP
299 bool "Allow generic start code to initialize and setup caches"
300 default n if SKIP_LOWLEVEL_INIT
301 default y
302 help
303 This allows the generic start code to invoke the generic initialization
304 of the CPU caches. Disabling this can be useful for RAM boot scenarios
305 (EJTAG, SPL payload) or for machines which don't need cache initialization
306 or which want to provide their own cache implementation.
307
308 If unsure, say yes.
309
310config MIPS_CACHE_DISABLE
311 bool "Allow generic start code to initially disable caches"
312 default n if SKIP_LOWLEVEL_INIT
313 default y
314 help
315 This allows the generic start code to initially disable the CPU caches
316 and run uncached until the caches are initialized and enabled. Disabling
317 this can be useful on machines which don't need cache initialization or
318 which want to provide their own cache implementation.
319
320 If unsure, say yes.
321
Daniel Schwierzeck80132862018-11-01 02:02:21 +0100322config MIPS_RELOCATION_TABLE_SIZE
323 hex "Relocation table size"
324 range 0x100 0x10000
Heinrich Schuchardt20e310b2024-11-03 20:01:13 +0100325 default "0xc000" if TARGET_MALTA
Daniel Schwierzeck80132862018-11-01 02:02:21 +0100326 default "0x8000"
327 ---help---
328 A table of relocation data will be appended to the U-Boot binary
329 and parsed in relocate_code() to fix up all offsets in the relocated
330 U-Boot.
331
332 This option allows the amount of space reserved for the table to be
333 adjusted in a range from 256 up to 64k. The default is 32k and should
334 be ok in most cases. Reduce this value to shrink the size of U-Boot
335 binary.
336
337 The build will fail and a valid size suggested if this is too small.
338
339 If unsure, leave at the default value.
340
developer5cbbd712020-04-21 09:28:25 +0200341config RESTORE_EXCEPTION_VECTOR_BASE
342 bool "Restore exception vector base before booting linux kernel"
developer5cbbd712020-04-21 09:28:25 +0200343 help
344 In U-Boot the exception vector base will be moved to top of memory,
345 to be used to display register dump when exception occurs.
346 But some old linux kernel does not honor the base set in CP0_EBASE.
347 A modified exception vector base will cause kernel crash.
348
349 This option will restore the exception vector base to its previous
350 value.
351
352 If unsure, say N.
353
354config OVERRIDE_EXCEPTION_VECTOR_BASE
355 bool "Override the exception vector base to be restored"
356 depends on RESTORE_EXCEPTION_VECTOR_BASE
developer5cbbd712020-04-21 09:28:25 +0200357 help
358 Enable this option if you want to use a different exception vector
359 base rather than the previously saved one.
360
361config NEW_EXCEPTION_VECTOR_BASE
362 hex "New exception vector base"
363 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
364 range 0x80000000 0xbffff000
365 default 0x80000000
366 help
367 The exception vector base to be restored before booting linux kernel
368
developer01a28282020-04-21 09:28:33 +0200369config INIT_STACK_WITHOUT_MALLOC_F
370 bool "Do not reserve malloc space on initial stack"
developer01a28282020-04-21 09:28:33 +0200371 help
372 Enable this option if you don't want to reserve malloc space on
373 initial stack. This is useful if the initial stack can't hold large
374 malloc space. Platform should set the malloc_base later when DRAM is
375 ready to use.
376
377config SPL_INIT_STACK_WITHOUT_MALLOC_F
378 bool "Do not reserve malloc space on initial stack in SPL"
developer01a28282020-04-21 09:28:33 +0200379 help
380 Enable this option if you don't want to reserve malloc space on
381 initial stack. This is useful if the initial stack can't hold large
382 malloc space. Platform should set the malloc_base later when DRAM is
383 ready to use.
384
developer25678a02020-04-21 09:28:37 +0200385config SPL_LOADER_SUPPORT
386 bool
developer25678a02020-04-21 09:28:37 +0200387 help
388 Enable this option if you want to use SPL loaders without DM enabled.
389
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100390endmenu
391
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100392menu "OS boot interface"
393
394config MIPS_BOOT_CMDLINE_LEGACY
395 bool "Hand over legacy command line to Linux kernel"
396 default y
397 help
398 Enable this option if you want U-Boot to hand over the Yamon-style
399 command line to the kernel. All bootargs will be prepared as argc/argv
400 compatible list. The argument count (argc) is stored in register $a0.
401 The address of the argument list (argv) is stored in register $a1.
402
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100403config MIPS_BOOT_ENV_LEGACY
404 bool "Hand over legacy environment to Linux kernel"
405 default y
406 help
407 Enable this option if you want U-Boot to hand over the Yamon-style
408 environment to the kernel. Information like memory size, initrd
409 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day8c60f922016-05-04 04:47:31 -0400410 The address of the environment is stored in register $a2.
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100411
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100412config MIPS_BOOT_FDT
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100413 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100414 help
415 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100416 device tree to the kernel. According to UHI register $a0 will be set
417 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100418
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100419endmenu
420
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100421config SUPPORTS_CPU_MIPS32_R1
422 bool
423
424config SUPPORTS_CPU_MIPS32_R2
425 bool
426
Paul Burton55e29dd2016-05-16 10:52:12 +0100427config SUPPORTS_CPU_MIPS32_R6
428 bool
429
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100430config SUPPORTS_CPU_MIPS64_R1
431 bool
432
433config SUPPORTS_CPU_MIPS64_R2
434 bool
435
Paul Burton55e29dd2016-05-16 10:52:12 +0100436config SUPPORTS_CPU_MIPS64_R6
437 bool
438
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200439config SUPPORTS_CPU_MIPS64_OCTEON
440 bool
441
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200442config HAS_FIXED_TIMER_FREQUENCY
443 bool
444
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200445config CPU_CAVIUM_OCTEON
446 bool
447
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100448config CPU_MIPS32
449 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100450 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100451
452config CPU_MIPS64
453 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100454 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200455 default y if CPU_MIPS64_OCTEON
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100456
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100457config MIPS_TUNE_4KC
458 bool
459
460config MIPS_TUNE_14KC
461 bool
462
463config MIPS_TUNE_24KC
464 bool
465
Daniel Schwierzeckc7661d52016-05-27 15:39:39 +0200466config MIPS_TUNE_34KC
467 bool
468
Marek Vasuta9c6e8b2016-05-06 20:10:33 +0200469config MIPS_TUNE_74KC
470 bool
471
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200472config MIPS_TUNE_OCTEON3
473 bool
474
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +0100475config SWAP_IO_SPACE
476 bool
477
Paul Burton6832bdc2015-01-29 01:28:02 +0000478config SYS_MIPS_CACHE_INIT_RAM_LOAD
479 bool
480
Daniel Schwierzeck41dc35e2016-06-04 16:13:21 +0200481config MIPS_INIT_STACK_IN_SRAM
482 bool
Daniel Schwierzeck41dc35e2016-06-04 16:13:21 +0200483 help
484 Select this if the initial stack frame could be setup in SRAM.
485 Normally the initial stack frame is set up in DRAM which is often
486 only available after lowlevel_init. With this option the initial
487 stack frame and the early C environment is set up before
488 lowlevel_init. Thus lowlevel_init does not need to be implemented
489 in assembler.
490
developereb7d3a22020-04-21 09:28:27 +0200491config MIPS_SRAM_INIT
492 bool
developereb7d3a22020-04-21 09:28:27 +0200493 depends on MIPS_INIT_STACK_IN_SRAM
494 help
495 Select this if the SRAM for initial stack needs to be initialized
496 before it can be used. If enabled, a function mips_sram_init() will
497 be called just before setup_stack_gd.
498
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200499config DMA_ADDR_T_64BIT
500 bool
501 help
502 Select this to enable 64-bit DMA addressing
503
Paul Burton5e511422016-05-27 14:28:04 +0100504config SYS_DCACHE_SIZE
505 int
506 default 0
507 help
508 The total size of the L1 Dcache, if known at compile time.
509
Paul Burton62f13522016-05-27 14:28:05 +0100510config SYS_DCACHE_LINE_SIZE
Paul Burton79e49fd2016-06-09 13:09:52 +0100511 int
Paul Burton62f13522016-05-27 14:28:05 +0100512 default 0
513 help
514 The size of L1 Dcache lines, if known at compile time.
515
Paul Burton5e511422016-05-27 14:28:04 +0100516config SYS_ICACHE_SIZE
517 int
518 default 0
519 help
520 The total size of the L1 ICache, if known at compile time.
521
Paul Burton62f13522016-05-27 14:28:05 +0100522config SYS_ICACHE_LINE_SIZE
Paul Burton5e511422016-05-27 14:28:04 +0100523 int
524 default 0
525 help
Paul Burton62f13522016-05-27 14:28:05 +0100526 The size of L1 Icache lines, if known at compile time.
Paul Burton5e511422016-05-27 14:28:04 +0100527
Ramon Fried7e07e492019-06-10 21:05:26 +0300528config SYS_SCACHE_LINE_SIZE
529 int
530 default 0
531 help
532 The size of L2 cache lines, if known at compile time.
533
534
Paul Burton5e511422016-05-27 14:28:04 +0100535config SYS_CACHE_SIZE_AUTO
536 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Ramon Fried7e07e492019-06-10 21:05:26 +0300537 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
538 SYS_SCACHE_LINE_SIZE = 0
Paul Burton5e511422016-05-27 14:28:04 +0100539 help
540 Select this (or let it be auto-selected by not defining any cache
541 sizes) in order to allow U-Boot to automatically detect the sizes
542 of caches at runtime. This has a small cost in code size & runtime
543 so if you know the cache configuration for your system at compile
544 time it would be beneficial to configure it.
545
Paul Burton81560782016-09-21 11:18:54 +0100546config MIPS_L2_CACHE
547 bool
548 help
549 Select this if your system includes an L2 cache and you want U-Boot
550 to initialise & maintain it.
551
Paul Burton8d6600b2016-01-29 13:54:52 +0000552config DYNAMIC_IO_PORT_BASE
553 bool
554
Paul Burton79ac1742016-09-21 11:18:53 +0100555config MIPS_CM
556 bool
557 help
558 Select this if your system contains a MIPS Coherence Manager and you
559 wish U-Boot to configure it or make use of it to retrieve system
560 information such as cache configuration.
561
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +0200562config MIPS_INSERT_BOOT_CONFIG
563 bool
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +0200564 help
565 Enable this to insert some board-specific boot configuration in
566 the U-Boot binary at offset 0x10.
567
568config MIPS_BOOT_CONFIG_WORD0
569 hex
570 depends on MIPS_INSERT_BOOT_CONFIG
571 default 0x420 if TARGET_MALTA
572 default 0x0
573 help
574 Value which is inserted as boot config word 0.
575
576config MIPS_BOOT_CONFIG_WORD1
577 hex
578 depends on MIPS_INSERT_BOOT_CONFIG
579 default 0x0
580 help
581 Value which is inserted as boot config word 1.
582
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100583endif
584
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900585endmenu