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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -06002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <common/debug.h>
10#include <drivers/arm/cci.h>
11#include <drivers/arm/ccn.h>
12#include <drivers/arm/gicv2.h>
Alexei Fedorov7131d832019-08-16 14:15:59 +010013#include <drivers/arm/sp804_delay_timer.h>
14#include <drivers/generic_delay_timer.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/mmio.h>
16#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000017#include <plat/arm/common/arm_config.h>
18#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000020#include <platform_def.h>
Paul Beesley45f40282019-10-15 10:57:42 +000021#include <services/spm_mm_partition.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022
Roberto Vargas2ca18d92018-02-12 12:36:17 +000023#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010024
Achin Gupta1fa7eb62015-11-03 14:18:34 +000025/* Defines for GIC Driver build time selection */
26#define FVP_GICV2 1
27#define FVP_GICV3 2
Achin Gupta1fa7eb62015-11-03 14:18:34 +000028
Achin Gupta4f6ad662013-10-25 09:08:21 +010029/*******************************************************************************
Dan Handley2b6b5742015-03-19 19:17:53 +000030 * arm_config holds the characteristics of the differences between the three FVP
31 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
Vikram Kanigirifbb13012016-02-15 11:54:14 +000032 * at each boot stage by the primary before enabling the MMU (to allow
33 * interconnect configuration) & used thereafter. Each BL will have its own copy
34 * to allow independent operation.
Achin Gupta4f6ad662013-10-25 09:08:21 +010035 ******************************************************************************/
Dan Handley2b6b5742015-03-19 19:17:53 +000036arm_config_t arm_config;
Soby Mathewb08bc042014-09-03 17:48:44 +010037
38#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
39 DEVICE0_SIZE, \
40 MT_DEVICE | MT_RW | MT_SECURE)
41
42#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
43 DEVICE1_SIZE, \
44 MT_DEVICE | MT_RW | MT_SECURE)
45
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010046/*
47 * Need to be mapped with write permissions in order to set a new non-volatile
48 * counter value.
49 */
Juan Castillo31a68f02015-04-14 12:49:03 +010050#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
51 DEVICE2_SIZE, \
Antonio Nino Diaz9d602fe2016-05-20 14:14:16 +010052 MT_DEVICE | MT_RW | MT_SECURE)
Juan Castillo31a68f02015-04-14 12:49:03 +010053
Jon Medhurstb1eb0932014-02-26 16:27:53 +000054/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010055 * Table of memory regions for various BL stages to map using the MMU.
Roberto Vargas344ff022018-10-19 16:44:18 +010056 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
57 * of mapping it.
Sandrine Bailleux889ca032016-06-14 17:01:00 +010058 *
59 * The flash needs to be mapped as writable in order to erase the FIP's Table of
60 * Contents in case of unrecoverable error (see plat_error_handler()).
Jon Medhurstb1eb0932014-02-26 16:27:53 +000061 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090062#ifdef IMAGE_BL1
Dan Handley2b6b5742015-03-19 19:17:53 +000063const mmap_region_t plat_arm_mmap[] = {
64 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010065 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000066 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010067 MAP_DEVICE0,
68 MAP_DEVICE1,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010069#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010070 /* To access the Root of Trust Public Key registers. */
71 MAP_DEVICE2,
72 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010073 ARM_MAP_NS_DRAM1,
74#endif
Soby Mathewb08bc042014-09-03 17:48:44 +010075 {0}
76};
77#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090078#ifdef IMAGE_BL2
Dan Handley2b6b5742015-03-19 19:17:53 +000079const mmap_region_t plat_arm_mmap[] = {
80 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010081 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000082 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010083 MAP_DEVICE0,
84 MAP_DEVICE1,
Dan Handley2b6b5742015-03-19 19:17:53 +000085 ARM_MAP_NS_DRAM1,
Julius Werner8e0ef0f2019-07-09 14:02:43 -070086#ifdef __aarch64__
Roberto Vargasf8fda102017-08-08 11:27:20 +010087 ARM_MAP_DRAM2,
88#endif
Achin Guptae97351d2019-10-11 15:15:19 +010089#if defined(SPD_spmd)
90 ARM_MAP_TRUSTED_DRAM,
91#endif
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010092#ifdef SPD_tspd
Dan Handley2b6b5742015-03-19 19:17:53 +000093 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010094#endif
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010095#if TRUSTED_BOARD_BOOT
96 /* To access the Root of Trust Public Key registers. */
97 MAP_DEVICE2,
Antonio Nino Diaz05f49572018-09-25 11:37:23 +010098#if !BL2_AT_EL3
John Tsichritzisc34341a2018-07-30 13:41:52 +010099 ARM_MAP_BL1_RW,
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100100#endif
John Tsichritzisc34341a2018-07-30 13:41:52 +0100101#endif /* TRUSTED_BOARD_BOOT */
Paul Beesleyfe975b42019-09-16 11:29:03 +0000102#if SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000103 ARM_SP_IMAGE_MMAP,
104#endif
David Wang0ba499f2016-03-07 11:02:57 +0800105#if ARM_BL31_IN_DRAM
106 ARM_MAP_BL31_SEC_DRAM,
107#endif
Jens Wiklander0814c6a2017-08-25 10:07:20 +0200108#ifdef SPD_opteed
Soby Mathew874fc9e2017-09-01 13:43:50 +0100109 ARM_MAP_OPTEE_CORE_MEM,
Jens Wiklander0814c6a2017-08-25 10:07:20 +0200110 ARM_OPTEE_PAGEABLE_LOAD_MEM,
111#endif
Soby Mathewb08bc042014-09-03 17:48:44 +0100112 {0}
113};
114#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900115#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100116const mmap_region_t plat_arm_mmap[] = {
117 MAP_DEVICE0,
118 V2M_MAP_IOFPGA,
119 {0}
120};
121#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900122#ifdef IMAGE_BL31
Dan Handley2b6b5742015-03-19 19:17:53 +0000123const mmap_region_t plat_arm_mmap[] = {
124 ARM_MAP_SHARED_RAM,
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100125#if USE_DEBUGFS
126 /* Required by devfip, can be removed if devfip is not used */
127 V2M_MAP_FLASH0_RW,
128#endif /* USE_DEBUGFS */
Soby Mathew9ca28062017-10-11 16:08:58 +0100129 ARM_MAP_EL3_TZC_DRAM,
Dan Handley2b6b5742015-03-19 19:17:53 +0000130 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100131 MAP_DEVICE0,
132 MAP_DEVICE1,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100133 ARM_V2M_MAP_MEM_PROTECT,
Paul Beesleyfe975b42019-09-16 11:29:03 +0000134#if SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000135 ARM_SPM_BUF_EL3_MMAP,
136#endif
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600137 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
Madhukar Pappireddyaa1121f2020-03-13 13:00:17 -0500138 ARM_DTB_DRAM_NS,
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000139 {0}
140};
141
Paul Beesleyfe975b42019-09-16 11:29:03 +0000142#if defined(IMAGE_BL31) && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000143const mmap_region_t plat_arm_secure_partition_mmap[] = {
144 V2M_MAP_IOFPGA_EL0, /* for the UART */
Sandrine Bailleux4808f8b2018-01-12 15:50:12 +0100145 MAP_REGION_FLAT(DEVICE0_BASE, \
146 DEVICE0_SIZE, \
147 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000148 ARM_SP_IMAGE_MMAP,
149 ARM_SP_IMAGE_NS_BUF_MMAP,
150 ARM_SP_IMAGE_RW_MMAP,
151 ARM_SPM_BUF_EL0_MMAP,
Soby Mathewb08bc042014-09-03 17:48:44 +0100152 {0}
153};
154#endif
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000155#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900156#ifdef IMAGE_BL32
Dan Handley2b6b5742015-03-19 19:17:53 +0000157const mmap_region_t plat_arm_mmap[] = {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700158#ifndef __aarch64__
Soby Mathew0d268dc2016-07-11 14:13:56 +0100159 ARM_MAP_SHARED_RAM,
Joel Hutton10503cc2018-03-15 11:33:44 +0000160 ARM_V2M_MAP_MEM_PROTECT,
Soby Mathew0d268dc2016-07-11 14:13:56 +0100161#endif
Dan Handley2b6b5742015-03-19 19:17:53 +0000162 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100163 MAP_DEVICE0,
164 MAP_DEVICE1,
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600165 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
Madhukar Pappireddyaa1121f2020-03-13 13:00:17 -0500166 ARM_DTB_DRAM_NS,
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000167 {0}
168};
Soby Mathewb08bc042014-09-03 17:48:44 +0100169#endif
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000170
Dan Handley2b6b5742015-03-19 19:17:53 +0000171ARM_CASSERT_MMAP
Soby Mathew13ee9682015-01-22 11:22:22 +0000172
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100173#if FVP_INTERCONNECT_DRIVER != FVP_CCN
174static const int fvp_cci400_map[] = {
175 PLAT_FVP_CCI400_CLUS0_SL_PORT,
176 PLAT_FVP_CCI400_CLUS1_SL_PORT,
177};
178
179static const int fvp_cci5xx_map[] = {
180 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
181 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
182};
183
184static unsigned int get_interconnect_master(void)
185{
186 unsigned int master;
187 u_register_t mpidr;
188
189 mpidr = read_mpidr_el1();
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000190 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100191 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
192
193 assert(master < FVP_CLUSTER_COUNT);
194 return master;
195}
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000196#endif
197
Paul Beesleyfe975b42019-09-16 11:29:03 +0000198#if defined(IMAGE_BL31) && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000199/*
200 * Boot information passed to a secure partition during initialisation. Linear
201 * indices in MP information will be filled at runtime.
202 */
Paul Beesley45f40282019-10-15 10:57:42 +0000203static spm_mm_mp_info_t sp_mp_info[] = {
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000204 [0] = {0x80000000, 0},
205 [1] = {0x80000001, 0},
206 [2] = {0x80000002, 0},
207 [3] = {0x80000003, 0},
208 [4] = {0x80000100, 0},
209 [5] = {0x80000101, 0},
210 [6] = {0x80000102, 0},
211 [7] = {0x80000103, 0},
212};
213
Paul Beesley45f40282019-10-15 10:57:42 +0000214const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000215 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
216 .h.version = VERSION_1,
Paul Beesley45f40282019-10-15 10:57:42 +0000217 .h.size = sizeof(spm_mm_boot_info_t),
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000218 .h.attr = 0,
219 .sp_mem_base = ARM_SP_IMAGE_BASE,
220 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
221 .sp_image_base = ARM_SP_IMAGE_BASE,
222 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
223 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100224 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000225 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
226 .sp_image_size = ARM_SP_IMAGE_SIZE,
227 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
228 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100229 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000230 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
231 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
232 .num_cpus = PLATFORM_CORE_COUNT,
233 .mp_info = &sp_mp_info[0],
234};
235
236const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
237{
238 return plat_arm_secure_partition_mmap;
239}
240
Paul Beesley45f40282019-10-15 10:57:42 +0000241const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000242 void *cookie)
243{
244 return &plat_arm_secure_partition_boot_info;
245}
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100246#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248/*******************************************************************************
249 * A single boot loader stack is expected to work on both the Foundation FVP
250 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
251 * SYS_ID register provides a mechanism for detecting the differences between
252 * these platforms. This information is stored in a per-BL array to allow the
253 * code to take the correct path.Per BL platform configuration.
254 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100255void __init fvp_config_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100256{
Soby Mathew8e2f2872014-08-14 12:49:05 +0100257 unsigned int rev, hbi, bld, arch, sys_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258
Dan Handley2b6b5742015-03-19 19:17:53 +0000259 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
260 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
261 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
262 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
263 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264
Andrew Thoelke960347d2014-06-26 14:27:26 +0100265 if (arch != ARCH_MODEL) {
266 ERROR("This firmware is for FVP models\n");
James Morrissey40a6f642014-02-10 14:24:36 +0000267 panic();
Andrew Thoelke960347d2014-06-26 14:27:26 +0100268 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100269
270 /*
271 * The build field in the SYS_ID tells which variant of the GIC
272 * memory is implemented by the model.
273 */
274 switch (bld) {
275 case BLD_GIC_VE_MMAP:
Soby Mathewcf022c52016-01-13 17:06:00 +0000276 ERROR("Legacy Versatile Express memory map for GIC peripheral"
277 " is not supported\n");
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000278 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279 break;
280 case BLD_GIC_A53A57_MMAP:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100281 break;
282 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100283 ERROR("Unsupported board build %x\n", bld);
284 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285 }
286
287 /*
288 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
289 * for the Foundation FVP.
290 */
291 switch (hbi) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000292 case HBI_FOUNDATION_FVP:
Dan Handley2b6b5742015-03-19 19:17:53 +0000293 arm_config.flags = 0;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100294
295 /*
296 * Check for supported revisions of Foundation FVP
297 * Allow future revisions to run but emit warning diagnostic
298 */
299 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000300 case REV_FOUNDATION_FVP_V2_0:
301 case REV_FOUNDATION_FVP_V2_1:
302 case REV_FOUNDATION_FVP_v9_1:
Sandrine Bailleux8b33d702016-09-22 09:46:50 +0100303 case REV_FOUNDATION_FVP_v9_6:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100304 break;
305 default:
306 WARN("Unrecognized Foundation FVP revision %x\n", rev);
307 break;
308 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309 break;
Dan Handley2b6b5742015-03-19 19:17:53 +0000310 case HBI_BASE_FVP:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100311 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100312
313 /*
314 * Check for supported revisions
315 * Allow future revisions to run but emit warning diagnostic
316 */
317 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000318 case REV_BASE_FVP_V0:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100319 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
320 break;
321 case REV_BASE_FVP_REVC:
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100322 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100323 ARM_CONFIG_FVP_HAS_CCI5XX);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100324 break;
325 default:
326 WARN("Unrecognized Base FVP revision %x\n", rev);
327 break;
328 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100329 break;
330 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100331 ERROR("Unsupported board HBI number 0x%x\n", hbi);
332 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100333 }
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100334
335 /*
336 * We assume that the presence of MT bit, and therefore shifted
337 * affinities, is uniform across the platform: either all CPUs, or no
338 * CPUs implement it.
339 */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000340 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100341 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100342}
Vikram Kanigiri96377452014-04-24 11:02:16 +0100343
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000344
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100345void __init fvp_interconnect_init(void)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100346{
Soby Mathew7356b1e2016-03-24 10:12:42 +0000347#if FVP_INTERCONNECT_DRIVER == FVP_CCN
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100348 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000349 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100350 panic();
351 }
352
353 plat_arm_interconnect_init();
354#else
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000355 uintptr_t cci_base = 0U;
356 const int *cci_map = NULL;
357 unsigned int map_size = 0U;
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100358
359 /* Initialize the right interconnect */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000360 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100361 cci_base = PLAT_FVP_CCI5XX_BASE;
362 cci_map = fvp_cci5xx_map;
363 map_size = ARRAY_SIZE(fvp_cci5xx_map);
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000364 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100365 cci_base = PLAT_FVP_CCI400_BASE;
366 cci_map = fvp_cci400_map;
367 map_size = ARRAY_SIZE(fvp_cci400_map);
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000368 } else {
369 return;
Soby Mathew7356b1e2016-03-24 10:12:42 +0000370 }
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100371
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000372 assert(cci_base != 0U);
373 assert(cci_map != NULL);
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100374 cci_init(cci_base, cci_map, map_size);
375#endif
Dan Handleybe234f92014-08-04 16:11:15 +0100376}
377
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000378void fvp_interconnect_enable(void)
Dan Handleybe234f92014-08-04 16:11:15 +0100379{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100380#if FVP_INTERCONNECT_DRIVER == FVP_CCN
381 plat_arm_interconnect_enter_coherency();
382#else
383 unsigned int master;
384
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000385 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
386 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100387 master = get_interconnect_master();
388 cci_enable_snoop_dvm_reqs(master);
389 }
390#endif
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000391}
392
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000393void fvp_interconnect_disable(void)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000394{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100395#if FVP_INTERCONNECT_DRIVER == FVP_CCN
396 plat_arm_interconnect_exit_coherency();
397#else
398 unsigned int master;
399
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000400 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
401 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100402 master = get_interconnect_master();
403 cci_disable_snoop_dvm_reqs(master);
404 }
405#endif
Vikram Kanigiri96377452014-04-24 11:02:16 +0100406}
John Tsichritzisc34341a2018-07-30 13:41:52 +0100407
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100408#if TRUSTED_BOARD_BOOT
John Tsichritzisc34341a2018-07-30 13:41:52 +0100409int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
410{
411 assert(heap_addr != NULL);
412 assert(heap_size != NULL);
413
414 return arm_get_mbedtls_heap(heap_addr, heap_size);
415}
416#endif
Alexei Fedorov7131d832019-08-16 14:15:59 +0100417
418void fvp_timer_init(void)
419{
420#if FVP_USE_SP804_TIMER
421 /* Enable the clock override for SP804 timer 0, which means that no
422 * clock dividers are applied and the raw (35MHz) clock will be used.
423 */
424 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
425
426 /* Initialize delay timer driver using SP804 dual timer 0 */
427 sp804_timer_init(V2M_SP804_TIMER0_BASE,
428 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
429#else
430 generic_delay_timer_init();
431
432 /* Enable System level generic timer */
433 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
434 CNTCR_FCREQ(0U) | CNTCR_EN);
435#endif /* FVP_USE_SP804_TIMER */
436}