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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Heyi Guo691b49d2020-05-19 16:45:17 +08002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef GICV3_PRIVATE_H
8#define GICV3_PRIVATE_H
Achin Gupta92712a52015-09-03 14:18:02 +01009
Soby Mathew327548c2017-07-13 15:19:51 +010010#include <assert.h>
Achin Gupta92712a52015-09-03 14:18:02 +010011#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012
13#include <drivers/arm/gic_common.h>
14#include <drivers/arm/gicv3.h>
15#include <lib/mmio.h>
16
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000017#include "../common/gic_common_private.h"
Achin Gupta92712a52015-09-03 14:18:02 +010018
19/*******************************************************************************
20 * GICv3 private macro definitions
21 ******************************************************************************/
22
23/* Constants to indicate the status of the RWP bit */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010024#define RWP_TRUE U(1)
25#define RWP_FALSE U(0)
Achin Gupta92712a52015-09-03 14:18:02 +010026
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000027/* Calculate GIC register bit number corresponding to its interrupt ID */
28#define BIT_NUM(REG, id) \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010029 ((id) & ((1U << REG##R_SHIFT) - 1U))
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000030
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010031/*
32 * Calculate 8, 32 and 64-bit GICD register offset
33 * corresponding to its interrupt ID
34 */
35#if GIC_EXT_INTID
36 /* GICv3.1 */
37#define GICD_OFFSET_8(REG, id) \
38 (((id) <= MAX_SPI_ID) ? \
39 GICD_##REG##R + (uintptr_t)(id) : \
40 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID)
41
42#define GICD_OFFSET(REG, id) \
43 (((id) <= MAX_SPI_ID) ? \
44 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
45 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
46 REG##R_SHIFT) << 2))
47
48#define GICD_OFFSET_64(REG, id) \
49 (((id) <= MAX_SPI_ID) ? \
50 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
Heyi Guo691b49d2020-05-19 16:45:17 +080051 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
52 REG##R_SHIFT) << 3))
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010053
54#else /* GICv3 */
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000055#define GICD_OFFSET_8(REG, id) \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010056 (GICD_##REG##R + (uintptr_t)(id))
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000057
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000058#define GICD_OFFSET(REG, id) \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010059 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000060
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000061#define GICD_OFFSET_64(REG, id) \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010062 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3))
63#endif /* GIC_EXT_INTID */
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000064
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010065/*
66 * Read/Write 8, 32 and 64-bit GIC Distributor register
67 * corresponding to its interrupt ID
68 */
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000069#define GICD_READ(REG, base, id) \
70 mmio_read_32((base) + GICD_OFFSET(REG, (id)))
71
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000072#define GICD_READ_64(REG, base, id) \
73 mmio_read_64((base) + GICD_OFFSET_64(REG, (id)))
74
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010075#define GICD_WRITE_8(REG, base, id, val) \
76 mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000077
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010078#define GICD_WRITE(REG, base, id, val) \
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000079 mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val))
80
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010081#define GICD_WRITE_64(REG, base, id, val) \
82 mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +000083
84/*
85 * Bit operations on GIC Distributor register corresponding
86 * to its interrupt ID
87 */
88/* Get bit in GIC Distributor register */
89#define GICD_GET_BIT(REG, base, id) \
90 ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \
91 BIT_NUM(REG, (id))) & 1U)
92
93/* Set bit in GIC Distributor register */
94#define GICD_SET_BIT(REG, base, id) \
95 mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \
96 ((uint32_t)1 << BIT_NUM(REG, (id))))
97
98/* Clear bit in GIC Distributor register */
99#define GICD_CLR_BIT(REG, base, id) \
100 mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \
101 ((uint32_t)1 << BIT_NUM(REG, (id))))
102
103/* Write bit in GIC Distributor register */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100104#define GICD_WRITE_BIT(REG, base, id) \
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000105 mmio_write_32((base) + GICD_OFFSET(REG, (id)), \
106 ((uint32_t)1 << BIT_NUM(REG, (id))))
107
108/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100109 * Calculate 8 and 32-bit GICR register offset
110 * corresponding to its interrupt ID
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000111 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100112#if GIC_EXT_INTID
113 /* GICv3.1 */
114#define GICR_OFFSET_8(REG, id) \
115 (((id) <= MAX_PPI_ID) ? \
116 GICR_##REG##R + (uintptr_t)(id) : \
117 GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))
118
119#define GICR_OFFSET(REG, id) \
120 (((id) <= MAX_PPI_ID) ? \
121 GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
122 GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\
123 >> REG##R_SHIFT) << 2))
124#else /* GICv3 */
125#define GICR_OFFSET_8(REG, id) \
126 (GICR_##REG##R + (uintptr_t)(id))
127
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000128#define GICR_OFFSET(REG, id) \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100129 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100130#endif /* GIC_EXT_INTID */
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000131
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100132/* Read/Write GIC Redistributor register corresponding to its interrupt ID */
133#define GICR_READ(REG, base, id) \
134 mmio_read_32((base) + GICR_OFFSET(REG, (id)))
135
136#define GICR_WRITE_8(REG, base, id, val) \
137 mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val))
138
139#define GICR_WRITE(REG, base, id, val) \
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100140 mmio_write_32((base) + GICR_OFFSET(REG, (id)), (val))
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000141
142/*
143 * Bit operations on GIC Redistributor register
144 * corresponding to its interrupt ID
145 */
146/* Get bit in GIC Redistributor register */
147#define GICR_GET_BIT(REG, base, id) \
148 ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \
149 BIT_NUM(REG, (id))) & 1U)
150
151/* Write bit in GIC Redistributor register */
152#define GICR_WRITE_BIT(REG, base, id) \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100153 mmio_write_32((base) + GICR_OFFSET(REG, (id)), \
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000154 ((uint32_t)1 << BIT_NUM(REG, (id))))
155
156/* Set bit in GIC Redistributor register */
157#define GICR_SET_BIT(REG, base, id) \
158 mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \
159 ((uint32_t)1 << BIT_NUM(REG, (id))))
160
161/* Clear bit in GIC Redistributor register */
162#define GICR_CLR_BIT(REG, base, id) \
163 mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \
164 ((uint32_t)1 << BIT_NUM(REG, (id))))
165
Achin Gupta92712a52015-09-03 14:18:02 +0100166/*
Achin Gupta92712a52015-09-03 14:18:02 +0100167 * Macro to convert an mpidr to a value suitable for programming into a
168 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
169 * to GICv3.
170 */
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100171static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr,
172 unsigned int irm)
173{
Ming Huangddb0b942021-10-27 11:41:04 +0800174 return (mpidr & MPIDR_AFFINITY_MASK) |
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100175 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT);
176}
Achin Gupta92712a52015-09-03 14:18:02 +0100177
178/*
Achin Gupta92712a52015-09-03 14:18:02 +0100179 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
180 * are zeroes.
181 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700182#ifdef __aarch64__
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100183static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
184{
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700185 return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
186 ((typer_val >> 32) & U(0xffffff));
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100187}
Soby Mathewd6452322016-05-05 13:59:07 +0100188#else
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100189static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
190{
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700191 return (((typer_val) >> 32) & U(0xffffff));
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100192}
Soby Mathewd6452322016-05-05 13:59:07 +0100193#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100194
195/*******************************************************************************
Soby Mathew327548c2017-07-13 15:19:51 +0100196 * GICv3 private global variables declarations
197 ******************************************************************************/
198extern const gicv3_driver_data_t *gicv3_driver_data;
199
200/*******************************************************************************
Soby Mathew50f6fe42016-02-01 17:59:22 +0000201 * Private GICv3 function prototypes for accessing entire registers.
202 * Note: The raw register values correspond to multiple interrupt IDs and
203 * the number of interrupt IDs involved depends on the register accessed.
Achin Gupta92712a52015-09-03 14:18:02 +0100204 ******************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100205unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100206unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100207void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100208void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
Soby Mathew50f6fe42016-02-01 17:59:22 +0000209
210/*******************************************************************************
211 * Private GICv3 function prototypes for accessing the GIC registers
212 * corresponding to a single interrupt ID. These functions use bitwise
213 * operations or appropriate register accesses to modify or return
214 * the bit-field corresponding the single interrupt ID.
215 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +0100216unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100217unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id);
218unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id);
219unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id);
Achin Gupta92712a52015-09-03 14:18:02 +0100220void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100221void gicr_set_igrpmodr(uintptr_t base, unsigned int id);
222void gicr_set_isenabler(uintptr_t base, unsigned int id);
223void gicr_set_icenabler(uintptr_t base, unsigned int id);
224void gicr_set_ispendr(uintptr_t base, unsigned int id);
225void gicr_set_icpendr(uintptr_t base, unsigned int id);
226void gicr_set_igroupr(uintptr_t base, unsigned int id);
Achin Gupta92712a52015-09-03 14:18:02 +0100227void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100228void gicr_clr_igrpmodr(uintptr_t base, unsigned int id);
229void gicr_clr_igroupr(uintptr_t base, unsigned int id);
Soby Mathew50f6fe42016-02-01 17:59:22 +0000230void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100231void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg);
Soby Mathew50f6fe42016-02-01 17:59:22 +0000232
233/*******************************************************************************
234 * Private GICv3 helper function prototypes
235 ******************************************************************************/
Heyi Guo06f85b42021-01-20 18:50:16 +0800236unsigned int gicv3_get_spi_limit(uintptr_t gicd_base);
Heyi Guo60ce8252021-01-20 18:50:16 +0800237unsigned int gicv3_get_espi_limit(uintptr_t gicd_base);
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100238void gicv3_spis_config_defaults(uintptr_t gicd_base);
239void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100240unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100241 const interrupt_prop_t *interrupt_props,
242 unsigned int interrupt_props_num);
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100243unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100244 const interrupt_prop_t *interrupt_props,
245 unsigned int interrupt_props_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100246void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
247 unsigned int rdistif_num,
248 uintptr_t gicr_base,
249 mpidr_hash_fn mpidr_to_core_pos);
250void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
251void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
252
253/*******************************************************************************
254 * GIC Distributor interface accessors
255 ******************************************************************************/
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100256/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100257 * Wait for updates to:
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100258 * GICD_CTLR[2:0] - the Group Enables
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100259 * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit
260 * GICD_ICENABLER<n> - the clearing of enable state for SPIs
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100261 */
262static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
263{
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000264 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) {
265 }
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100266}
267
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000268static inline uint32_t gicd_read_pidr2(uintptr_t base)
Achin Gupta92712a52015-09-03 14:18:02 +0100269{
270 return mmio_read_32(base + GICD_PIDR2_GICV3);
271}
272
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000273static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id)
Achin Gupta92712a52015-09-03 14:18:02 +0100274{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100275 assert(id >= MIN_SPI_ID);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100276 return GICD_READ_64(IROUTE, base, id);
Achin Gupta92712a52015-09-03 14:18:02 +0100277}
278
279static inline void gicd_write_irouter(uintptr_t base,
280 unsigned int id,
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000281 uint64_t affinity)
Achin Gupta92712a52015-09-03 14:18:02 +0100282{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100283 assert(id >= MIN_SPI_ID);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100284 GICD_WRITE_64(IROUTE, base, id, affinity);
Achin Gupta92712a52015-09-03 14:18:02 +0100285}
286
287static inline void gicd_clr_ctlr(uintptr_t base,
288 unsigned int bitmap,
289 unsigned int rwp)
290{
291 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000292 if (rwp != 0U) {
Achin Gupta92712a52015-09-03 14:18:02 +0100293 gicd_wait_for_pending_write(base);
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000294 }
Achin Gupta92712a52015-09-03 14:18:02 +0100295}
296
297static inline void gicd_set_ctlr(uintptr_t base,
298 unsigned int bitmap,
299 unsigned int rwp)
300{
301 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000302 if (rwp != 0U) {
Achin Gupta92712a52015-09-03 14:18:02 +0100303 gicd_wait_for_pending_write(base);
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000304 }
Achin Gupta92712a52015-09-03 14:18:02 +0100305}
306
307/*******************************************************************************
308 * GIC Redistributor interface accessors
309 ******************************************************************************/
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100310static inline uint32_t gicr_read_ctlr(uintptr_t base)
Achin Gupta92712a52015-09-03 14:18:02 +0100311{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100312 return mmio_read_32(base + GICR_CTLR);
Achin Gupta92712a52015-09-03 14:18:02 +0100313}
314
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100315static inline void gicr_write_ctlr(uintptr_t base, uint32_t val)
Soby Mathew327548c2017-07-13 15:19:51 +0100316{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100317 mmio_write_32(base + GICR_CTLR, val);
Soby Mathew327548c2017-07-13 15:19:51 +0100318}
319
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000320static inline uint64_t gicr_read_typer(uintptr_t base)
Achin Gupta92712a52015-09-03 14:18:02 +0100321{
322 return mmio_read_64(base + GICR_TYPER);
323}
324
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000325static inline uint32_t gicr_read_waker(uintptr_t base)
Achin Gupta92712a52015-09-03 14:18:02 +0100326{
327 return mmio_read_32(base + GICR_WAKER);
328}
329
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000330static inline void gicr_write_waker(uintptr_t base, uint32_t val)
Achin Gupta92712a52015-09-03 14:18:02 +0100331{
332 mmio_write_32(base + GICR_WAKER, val);
333}
334
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100335/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100336 * Wait for updates to:
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100337 * GICR_ICENABLER0
338 * GICR_CTLR.DPG1S
339 * GICR_CTLR.DPG1NS
340 * GICR_CTLR.DPG0
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100341 * GICR_CTLR, which clears EnableLPIs from 1 to 0
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100342 */
343static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
344{
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000345 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) {
346 }
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100347}
348
Soby Mathew327548c2017-07-13 15:19:51 +0100349static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
350{
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000351 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) {
352 }
Soby Mathew327548c2017-07-13 15:19:51 +0100353}
354
355/* Private implementation of Distributor power control hooks */
356void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num);
357void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num);
358
Soby Mathew50f6fe42016-02-01 17:59:22 +0000359/*******************************************************************************
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000360 * GIC Redistributor functions for accessing entire registers.
Soby Mathew50f6fe42016-02-01 17:59:22 +0000361 * Note: The raw register values correspond to multiple interrupt IDs and
362 * the number of interrupt IDs involved depends on the register accessed.
363 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +0100364
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100365/*
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100366 * Accessors to read/write GIC Redistributor ICENABLER0 register
367 */
368static inline unsigned int gicr_read_icenabler0(uintptr_t base)
369{
370 return mmio_read_32(base + GICR_ICENABLER0);
371}
372
373static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
374{
375 mmio_write_32(base + GICR_ICENABLER0, val);
376}
377
378/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100379 * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE
380 * register corresponding to its number
381 */
382static inline unsigned int gicr_read_icenabler(uintptr_t base,
383 unsigned int reg_num)
Achin Gupta92712a52015-09-03 14:18:02 +0100384{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100385 return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2));
Achin Gupta92712a52015-09-03 14:18:02 +0100386}
387
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100388static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num,
389 unsigned int val)
Achin Gupta92712a52015-09-03 14:18:02 +0100390{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100391 mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val);
Achin Gupta92712a52015-09-03 14:18:02 +0100392}
393
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100394/*
395 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 registers
396 */
397static inline unsigned int gicr_read_icfgr0(uintptr_t base)
398{
399 return mmio_read_32(base + GICR_ICFGR0);
400}
401
402static inline unsigned int gicr_read_icfgr1(uintptr_t base)
403{
404 return mmio_read_32(base + GICR_ICFGR1);
405}
406
407static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val)
408{
409 mmio_write_32(base + GICR_ICFGR0, val);
410}
411
412static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
413{
414 mmio_write_32(base + GICR_ICFGR1, val);
415}
416
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100417/*
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100418 * Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100419 * register corresponding to its number
420 */
421static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num)
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100422{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100423 return mmio_read_32(base + GICR_ICFGR + (reg_num << 2));
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100424}
425
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100426static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num,
427 unsigned int val)
Achin Gupta92712a52015-09-03 14:18:02 +0100428{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100429 mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val);
Achin Gupta92712a52015-09-03 14:18:02 +0100430}
431
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100432/*
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100433 * Accessor to write GIC Redistributor ICPENDR0 register
434 */
435static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val)
436{
437 mmio_write_32(base + GICR_ICPENDR0, val);
438}
439
440/*
441 * Accessor to write GIC Redistributor ICPENDR0 and ICPENDRE
442 * register corresponding to its number
443 */
444static inline void gicr_write_icpendr(uintptr_t base, unsigned int reg_num,
445 unsigned int val)
446{
447 mmio_write_32(base + GICR_ICPENDR + (reg_num << 2), val);
448}
449
450/*
451 * Accessors to read/write GIC Redistributor IGROUPR0 register
452 */
453static inline unsigned int gicr_read_igroupr0(uintptr_t base)
454{
455 return mmio_read_32(base + GICR_IGROUPR0);
456}
457
458static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
459{
460 mmio_write_32(base + GICR_IGROUPR0, val);
461}
462
463/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100464 * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE
465 * register corresponding to its number
466 */
467static inline unsigned int gicr_read_igroupr(uintptr_t base,
468 unsigned int reg_num)
Achin Gupta92712a52015-09-03 14:18:02 +0100469{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100470 return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2));
Achin Gupta92712a52015-09-03 14:18:02 +0100471}
472
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100473static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num,
474 unsigned int val)
Soby Mathew327548c2017-07-13 15:19:51 +0100475{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100476 mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val);
Soby Mathew327548c2017-07-13 15:19:51 +0100477}
478
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100479/*
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100480 * Accessors to read/write GIC Redistributor IGRPMODR0 register
481 */
482static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
483{
484 return mmio_read_32(base + GICR_IGRPMODR0);
485}
486
487static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
488{
489 mmio_write_32(base + GICR_IGRPMODR0, val);
490}
491
492/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100493 * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE
494 * register corresponding to its number
495 */
496static inline unsigned int gicr_read_igrpmodr(uintptr_t base,
497 unsigned int reg_num)
Soby Mathew327548c2017-07-13 15:19:51 +0100498{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100499 return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2));
Soby Mathew327548c2017-07-13 15:19:51 +0100500}
501
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100502static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num,
503 unsigned int val)
Achin Gupta92712a52015-09-03 14:18:02 +0100504{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100505 mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val);
Achin Gupta92712a52015-09-03 14:18:02 +0100506}
507
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100508/*
509 * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register
510 * corresponding to its number, 4 interrupts IDs at a time.
511 */
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100512static inline unsigned int gicr_ipriorityr_read(uintptr_t base,
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100513 unsigned int reg_num)
Achin Gupta92712a52015-09-03 14:18:02 +0100514{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100515 return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2));
Achin Gupta92712a52015-09-03 14:18:02 +0100516}
517
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100518static inline void gicr_ipriorityr_write(uintptr_t base, unsigned int reg_num,
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100519 unsigned int val)
Achin Gupta92712a52015-09-03 14:18:02 +0100520{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100521 mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val);
Achin Gupta92712a52015-09-03 14:18:02 +0100522}
523
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100524/*
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100525 * Accessors to read/write GIC Redistributor ISACTIVER0 register
526 */
527static inline unsigned int gicr_read_isactiver0(uintptr_t base)
528{
529 return mmio_read_32(base + GICR_ISACTIVER0);
530}
531
532static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val)
533{
534 mmio_write_32(base + GICR_ISACTIVER0, val);
535}
536
537/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100538 * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE
539 * register corresponding to its number
540 */
541static inline unsigned int gicr_read_isactiver(uintptr_t base,
542 unsigned int reg_num)
Soby Mathew327548c2017-07-13 15:19:51 +0100543{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100544 return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2));
Soby Mathew327548c2017-07-13 15:19:51 +0100545}
546
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100547static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num,
548 unsigned int val)
Soby Mathew327548c2017-07-13 15:19:51 +0100549{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100550 mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val);
Soby Mathew327548c2017-07-13 15:19:51 +0100551}
552
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100553/*
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100554 * Accessors to read/write GIC Redistributor ISENABLER0 register
555 */
556static inline unsigned int gicr_read_isenabler0(uintptr_t base)
557{
558 return mmio_read_32(base + GICR_ISENABLER0);
559}
560
561static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
562{
563 mmio_write_32(base + GICR_ISENABLER0, val);
564}
565
566/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100567 * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE
568 * register corresponding to its number
569 */
570static inline unsigned int gicr_read_isenabler(uintptr_t base,
571 unsigned int reg_num)
Soby Mathew327548c2017-07-13 15:19:51 +0100572{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100573 return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2));
Soby Mathew327548c2017-07-13 15:19:51 +0100574}
575
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100576static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num,
577 unsigned int val)
Soby Mathew327548c2017-07-13 15:19:51 +0100578{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100579 mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val);
Soby Mathew327548c2017-07-13 15:19:51 +0100580}
581
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100582/*
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100583 * Accessors to read/write GIC Redistributor ISPENDR0 register
584 */
585static inline unsigned int gicr_read_ispendr0(uintptr_t base)
586{
587 return mmio_read_32(base + GICR_ISPENDR0);
588}
589
590static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val)
591{
592 mmio_write_32(base + GICR_ISPENDR0, val);
593}
594
595/*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100596 * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE
597 * register corresponding to its number
598 */
599static inline unsigned int gicr_read_ispendr(uintptr_t base,
600 unsigned int reg_num)
Soby Mathew327548c2017-07-13 15:19:51 +0100601{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100602 return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2));
Soby Mathew327548c2017-07-13 15:19:51 +0100603}
604
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100605static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num,
606 unsigned int val)
Achin Gupta92712a52015-09-03 14:18:02 +0100607{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100608 mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val);
Achin Gupta92712a52015-09-03 14:18:02 +0100609}
610
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100611/*
612 * Accessors to read/write GIC Redistributor NSACR register
613 */
614static inline unsigned int gicr_read_nsacr(uintptr_t base)
Soby Mathew327548c2017-07-13 15:19:51 +0100615{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100616 return mmio_read_32(base + GICR_NSACR);
Soby Mathew327548c2017-07-13 15:19:51 +0100617}
618
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100619static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
Achin Gupta92712a52015-09-03 14:18:02 +0100620{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100621 mmio_write_32(base + GICR_NSACR, val);
Achin Gupta92712a52015-09-03 14:18:02 +0100622}
623
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100624/*
625 * Accessors to read/write GIC Redistributor PROPBASER register
626 */
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100627static inline uint64_t gicr_read_propbaser(uintptr_t base)
Soby Mathew327548c2017-07-13 15:19:51 +0100628{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100629 return mmio_read_64(base + GICR_PROPBASER);
Soby Mathew327548c2017-07-13 15:19:51 +0100630}
631
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100632static inline void gicr_write_propbaser(uintptr_t base, uint64_t val)
Soby Mathew327548c2017-07-13 15:19:51 +0100633{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100634 mmio_write_64(base + GICR_PROPBASER, val);
Soby Mathew327548c2017-07-13 15:19:51 +0100635}
636
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100637/*
638 * Accessors to read/write GIC Redistributor PENDBASER register
639 */
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100640static inline uint64_t gicr_read_pendbaser(uintptr_t base)
Soby Mathew327548c2017-07-13 15:19:51 +0100641{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100642 return mmio_read_64(base + GICR_PENDBASER);
Soby Mathew327548c2017-07-13 15:19:51 +0100643}
644
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100645static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val)
Soby Mathew327548c2017-07-13 15:19:51 +0100646{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100647 mmio_write_64(base + GICR_PENDBASER, val);
Soby Mathew327548c2017-07-13 15:19:51 +0100648}
649
Soby Mathewf6f1a322017-07-18 16:12:45 +0100650/*******************************************************************************
651 * GIC ITS functions to read and write entire ITS registers.
652 ******************************************************************************/
653static inline uint32_t gits_read_ctlr(uintptr_t base)
654{
655 return mmio_read_32(base + GITS_CTLR);
656}
657
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000658static inline void gits_write_ctlr(uintptr_t base, uint32_t val)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100659{
660 mmio_write_32(base + GITS_CTLR, val);
661}
662
663static inline uint64_t gits_read_cbaser(uintptr_t base)
664{
665 return mmio_read_64(base + GITS_CBASER);
666}
667
668static inline void gits_write_cbaser(uintptr_t base, uint64_t val)
669{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100670 mmio_write_64(base + GITS_CBASER, val);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100671}
672
673static inline uint64_t gits_read_cwriter(uintptr_t base)
674{
675 return mmio_read_64(base + GITS_CWRITER);
676}
677
678static inline void gits_write_cwriter(uintptr_t base, uint64_t val)
679{
Antonio Nino Diazbab39e82018-08-21 10:03:07 +0100680 mmio_write_64(base + GITS_CWRITER, val);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100681}
682
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000683static inline uint64_t gits_read_baser(uintptr_t base,
684 unsigned int its_table_id)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100685{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100686 assert(its_table_id < 8U);
687 return mmio_read_64(base + GITS_BASER + (8U * its_table_id));
Soby Mathewf6f1a322017-07-18 16:12:45 +0100688}
689
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000690static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id,
691 uint64_t val)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100692{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100693 assert(its_table_id < 8U);
694 mmio_write_64(base + GITS_BASER + (8U * its_table_id), val);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100695}
696
697/*
698 * Wait for Quiescent bit when GIC ITS is disabled
699 */
700static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
701{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100702 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000703 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) {
704 }
Soby Mathewf6f1a322017-07-18 16:12:45 +0100705}
706
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000707#endif /* GICV3_PRIVATE_H */