Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 1 | /* |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef GICV3_PRIVATE_H |
| 8 | #define GICV3_PRIVATE_H |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 9 | |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 10 | #include <assert.h> |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 11 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <drivers/arm/gic_common.h> |
| 14 | #include <drivers/arm/gicv3.h> |
| 15 | #include <lib/mmio.h> |
| 16 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 17 | #include "../common/gic_common_private.h" |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 18 | |
| 19 | /******************************************************************************* |
| 20 | * GICv3 private macro definitions |
| 21 | ******************************************************************************/ |
| 22 | |
| 23 | /* Constants to indicate the status of the RWP bit */ |
Antonio Nino Diaz | 2e59071 | 2018-08-24 11:46:33 +0100 | [diff] [blame] | 24 | #define RWP_TRUE U(1) |
| 25 | #define RWP_FALSE U(0) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 26 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 27 | /* Calculate GIC register bit number corresponding to its interrupt ID */ |
| 28 | #define BIT_NUM(REG, id) \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 29 | ((id) & ((1U << REG##R_SHIFT) - 1U)) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 30 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 31 | /* |
| 32 | * Calculate 8, 32 and 64-bit GICD register offset |
| 33 | * corresponding to its interrupt ID |
| 34 | */ |
| 35 | #if GIC_EXT_INTID |
| 36 | /* GICv3.1 */ |
| 37 | #define GICD_OFFSET_8(REG, id) \ |
| 38 | (((id) <= MAX_SPI_ID) ? \ |
| 39 | GICD_##REG##R + (uintptr_t)(id) : \ |
| 40 | GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID) |
| 41 | |
| 42 | #define GICD_OFFSET(REG, id) \ |
| 43 | (((id) <= MAX_SPI_ID) ? \ |
| 44 | GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ |
| 45 | GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \ |
| 46 | REG##R_SHIFT) << 2)) |
| 47 | |
| 48 | #define GICD_OFFSET_64(REG, id) \ |
| 49 | (((id) <= MAX_SPI_ID) ? \ |
| 50 | GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \ |
| 51 | GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3)) |
| 52 | |
| 53 | #else /* GICv3 */ |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 54 | #define GICD_OFFSET_8(REG, id) \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 55 | (GICD_##REG##R + (uintptr_t)(id)) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 56 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 57 | #define GICD_OFFSET(REG, id) \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 58 | (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 59 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 60 | #define GICD_OFFSET_64(REG, id) \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 61 | (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3)) |
| 62 | #endif /* GIC_EXT_INTID */ |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 63 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 64 | /* |
| 65 | * Read/Write 8, 32 and 64-bit GIC Distributor register |
| 66 | * corresponding to its interrupt ID |
| 67 | */ |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 68 | #define GICD_READ(REG, base, id) \ |
| 69 | mmio_read_32((base) + GICD_OFFSET(REG, (id))) |
| 70 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 71 | #define GICD_READ_64(REG, base, id) \ |
| 72 | mmio_read_64((base) + GICD_OFFSET_64(REG, (id))) |
| 73 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 74 | #define GICD_WRITE_8(REG, base, id, val) \ |
| 75 | mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val)) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 76 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 77 | #define GICD_WRITE(REG, base, id, val) \ |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 78 | mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val)) |
| 79 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 80 | #define GICD_WRITE_64(REG, base, id, val) \ |
| 81 | mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val)) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 82 | |
| 83 | /* |
| 84 | * Bit operations on GIC Distributor register corresponding |
| 85 | * to its interrupt ID |
| 86 | */ |
| 87 | /* Get bit in GIC Distributor register */ |
| 88 | #define GICD_GET_BIT(REG, base, id) \ |
| 89 | ((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \ |
| 90 | BIT_NUM(REG, (id))) & 1U) |
| 91 | |
| 92 | /* Set bit in GIC Distributor register */ |
| 93 | #define GICD_SET_BIT(REG, base, id) \ |
| 94 | mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \ |
| 95 | ((uint32_t)1 << BIT_NUM(REG, (id)))) |
| 96 | |
| 97 | /* Clear bit in GIC Distributor register */ |
| 98 | #define GICD_CLR_BIT(REG, base, id) \ |
| 99 | mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \ |
| 100 | ((uint32_t)1 << BIT_NUM(REG, (id)))) |
| 101 | |
| 102 | /* Write bit in GIC Distributor register */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 103 | #define GICD_WRITE_BIT(REG, base, id) \ |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 104 | mmio_write_32((base) + GICD_OFFSET(REG, (id)), \ |
| 105 | ((uint32_t)1 << BIT_NUM(REG, (id)))) |
| 106 | |
| 107 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 108 | * Calculate 8 and 32-bit GICR register offset |
| 109 | * corresponding to its interrupt ID |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 110 | */ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 111 | #if GIC_EXT_INTID |
| 112 | /* GICv3.1 */ |
| 113 | #define GICR_OFFSET_8(REG, id) \ |
| 114 | (((id) <= MAX_PPI_ID) ? \ |
| 115 | GICR_##REG##R + (uintptr_t)(id) : \ |
| 116 | GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID)) |
| 117 | |
| 118 | #define GICR_OFFSET(REG, id) \ |
| 119 | (((id) <= MAX_PPI_ID) ? \ |
| 120 | GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \ |
| 121 | GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\ |
| 122 | >> REG##R_SHIFT) << 2)) |
| 123 | #else /* GICv3 */ |
| 124 | #define GICR_OFFSET_8(REG, id) \ |
| 125 | (GICR_##REG##R + (uintptr_t)(id)) |
| 126 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 127 | #define GICR_OFFSET(REG, id) \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 128 | (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2)) |
| 129 | #endif |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 130 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 131 | /* Read/Write GIC Redistributor register corresponding to its interrupt ID */ |
| 132 | #define GICR_READ(REG, base, id) \ |
| 133 | mmio_read_32((base) + GICR_OFFSET(REG, (id))) |
| 134 | |
| 135 | #define GICR_WRITE_8(REG, base, id, val) \ |
| 136 | mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val)) |
| 137 | |
| 138 | #define GICR_WRITE(REG, base, id, val) \ |
| 139 | mmio_write((base) + GICR_OFFSET(REG, (id)), (val)) |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 140 | |
| 141 | /* |
| 142 | * Bit operations on GIC Redistributor register |
| 143 | * corresponding to its interrupt ID |
| 144 | */ |
| 145 | /* Get bit in GIC Redistributor register */ |
| 146 | #define GICR_GET_BIT(REG, base, id) \ |
| 147 | ((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \ |
| 148 | BIT_NUM(REG, (id))) & 1U) |
| 149 | |
| 150 | /* Write bit in GIC Redistributor register */ |
| 151 | #define GICR_WRITE_BIT(REG, base, id) \ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 152 | mmio_write_32((base) + GICR_OFFSET(REG, (id)), \ |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 153 | ((uint32_t)1 << BIT_NUM(REG, (id)))) |
| 154 | |
| 155 | /* Set bit in GIC Redistributor register */ |
| 156 | #define GICR_SET_BIT(REG, base, id) \ |
| 157 | mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \ |
| 158 | ((uint32_t)1 << BIT_NUM(REG, (id)))) |
| 159 | |
| 160 | /* Clear bit in GIC Redistributor register */ |
| 161 | #define GICR_CLR_BIT(REG, base, id) \ |
| 162 | mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \ |
| 163 | ((uint32_t)1 << BIT_NUM(REG, (id)))) |
| 164 | |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 165 | /* |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 166 | * Macro to convert an mpidr to a value suitable for programming into a |
| 167 | * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant |
| 168 | * to GICv3. |
| 169 | */ |
Antonio Nino Diaz | dd4e59e | 2018-08-13 15:29:29 +0100 | [diff] [blame] | 170 | static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, |
| 171 | unsigned int irm) |
| 172 | { |
| 173 | return (mpidr & ~(U(0xff) << 24)) | |
| 174 | ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); |
| 175 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 176 | |
| 177 | /* |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 178 | * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] |
| 179 | * are zeroes. |
| 180 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 181 | #ifdef __aarch64__ |
Antonio Nino Diaz | dd4e59e | 2018-08-13 15:29:29 +0100 | [diff] [blame] | 182 | static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) |
| 183 | { |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 184 | return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | |
| 185 | ((typer_val >> 32) & U(0xffffff)); |
Antonio Nino Diaz | dd4e59e | 2018-08-13 15:29:29 +0100 | [diff] [blame] | 186 | } |
Soby Mathew | d645232 | 2016-05-05 13:59:07 +0100 | [diff] [blame] | 187 | #else |
Antonio Nino Diaz | dd4e59e | 2018-08-13 15:29:29 +0100 | [diff] [blame] | 188 | static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val) |
| 189 | { |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 190 | return (((typer_val) >> 32) & U(0xffffff)); |
Antonio Nino Diaz | dd4e59e | 2018-08-13 15:29:29 +0100 | [diff] [blame] | 191 | } |
Soby Mathew | d645232 | 2016-05-05 13:59:07 +0100 | [diff] [blame] | 192 | #endif |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 193 | |
| 194 | /******************************************************************************* |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 195 | * GICv3 private global variables declarations |
| 196 | ******************************************************************************/ |
| 197 | extern const gicv3_driver_data_t *gicv3_driver_data; |
| 198 | |
| 199 | /******************************************************************************* |
Soby Mathew | 50f6fe4 | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 200 | * Private GICv3 function prototypes for accessing entire registers. |
| 201 | * Note: The raw register values correspond to multiple interrupt IDs and |
| 202 | * the number of interrupt IDs involved depends on the register accessed. |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 203 | ******************************************************************************/ |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 204 | unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); |
| 205 | void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); |
Soby Mathew | 50f6fe4 | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 206 | |
| 207 | /******************************************************************************* |
| 208 | * Private GICv3 function prototypes for accessing the GIC registers |
| 209 | * corresponding to a single interrupt ID. These functions use bitwise |
| 210 | * operations or appropriate register accesses to modify or return |
| 211 | * the bit-field corresponding the single interrupt ID. |
| 212 | ******************************************************************************/ |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 213 | unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 214 | unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id); |
| 215 | unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id); |
| 216 | unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 217 | void gicd_set_igrpmodr(uintptr_t base, unsigned int id); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 218 | void gicr_set_igrpmodr(uintptr_t base, unsigned int id); |
| 219 | void gicr_set_isenabler(uintptr_t base, unsigned int id); |
| 220 | void gicr_set_icenabler(uintptr_t base, unsigned int id); |
| 221 | void gicr_set_ispendr(uintptr_t base, unsigned int id); |
| 222 | void gicr_set_icpendr(uintptr_t base, unsigned int id); |
| 223 | void gicr_set_igroupr(uintptr_t base, unsigned int id); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 224 | void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 225 | void gicr_clr_igrpmodr(uintptr_t base, unsigned int id); |
| 226 | void gicr_clr_igroupr(uintptr_t base, unsigned int id); |
Soby Mathew | 50f6fe4 | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 227 | void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 228 | void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg); |
Soby Mathew | 50f6fe4 | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 229 | |
| 230 | /******************************************************************************* |
| 231 | * Private GICv3 helper function prototypes |
| 232 | ******************************************************************************/ |
Daniel Boulby | 4e83abb | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 233 | void gicv3_spis_config_defaults(uintptr_t gicd_base); |
| 234 | void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base); |
Daniel Boulby | 4e83abb | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 235 | unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, |
Jeenu Viswambharan | aeb267c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 236 | const interrupt_prop_t *interrupt_props, |
| 237 | unsigned int interrupt_props_num); |
Daniel Boulby | 4e83abb | 2018-05-01 15:15:34 +0100 | [diff] [blame] | 238 | unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, |
Jeenu Viswambharan | aeb267c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 239 | const interrupt_prop_t *interrupt_props, |
| 240 | unsigned int interrupt_props_num); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 241 | void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, |
| 242 | unsigned int rdistif_num, |
| 243 | uintptr_t gicr_base, |
| 244 | mpidr_hash_fn mpidr_to_core_pos); |
| 245 | void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); |
| 246 | void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); |
| 247 | |
| 248 | /******************************************************************************* |
| 249 | * GIC Distributor interface accessors |
| 250 | ******************************************************************************/ |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 251 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 252 | * Wait for updates to: |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 253 | * GICD_CTLR[2:0] - the Group Enables |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 254 | * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit |
| 255 | * GICD_ICENABLER<n> - the clearing of enable state for SPIs |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 256 | */ |
| 257 | static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) |
| 258 | { |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 259 | while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) { |
| 260 | } |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 261 | } |
| 262 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 263 | static inline uint32_t gicd_read_pidr2(uintptr_t base) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 264 | { |
| 265 | return mmio_read_32(base + GICD_PIDR2_GICV3); |
| 266 | } |
| 267 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 268 | static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 269 | { |
Soby Mathew | aaf71c8 | 2016-07-26 17:46:56 +0100 | [diff] [blame] | 270 | assert(id >= MIN_SPI_ID); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 271 | return GICD_READ_64(IROUTE, base, id); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | static inline void gicd_write_irouter(uintptr_t base, |
| 275 | unsigned int id, |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 276 | uint64_t affinity) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 277 | { |
Soby Mathew | aaf71c8 | 2016-07-26 17:46:56 +0100 | [diff] [blame] | 278 | assert(id >= MIN_SPI_ID); |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 279 | GICD_WRITE_64(IROUTE, base, id, affinity); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | static inline void gicd_clr_ctlr(uintptr_t base, |
| 283 | unsigned int bitmap, |
| 284 | unsigned int rwp) |
| 285 | { |
| 286 | gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 287 | if (rwp != 0U) { |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 288 | gicd_wait_for_pending_write(base); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 289 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | static inline void gicd_set_ctlr(uintptr_t base, |
| 293 | unsigned int bitmap, |
| 294 | unsigned int rwp) |
| 295 | { |
| 296 | gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 297 | if (rwp != 0U) { |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 298 | gicd_wait_for_pending_write(base); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 299 | } |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | /******************************************************************************* |
| 303 | * GIC Redistributor interface accessors |
| 304 | ******************************************************************************/ |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 305 | static inline uint32_t gicr_read_ctlr(uintptr_t base) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 306 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 307 | return mmio_read_32(base + GICR_CTLR); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 308 | } |
| 309 | |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 310 | static inline void gicr_write_ctlr(uintptr_t base, uint32_t val) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 311 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 312 | mmio_write_32(base + GICR_CTLR, val); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 313 | } |
| 314 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 315 | static inline uint64_t gicr_read_typer(uintptr_t base) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 316 | { |
| 317 | return mmio_read_64(base + GICR_TYPER); |
| 318 | } |
| 319 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 320 | static inline uint32_t gicr_read_waker(uintptr_t base) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 321 | { |
| 322 | return mmio_read_32(base + GICR_WAKER); |
| 323 | } |
| 324 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 325 | static inline void gicr_write_waker(uintptr_t base, uint32_t val) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 326 | { |
| 327 | mmio_write_32(base + GICR_WAKER, val); |
| 328 | } |
| 329 | |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 330 | /* |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 331 | * Wait for updates to: |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 332 | * GICR_ICENABLER0 |
| 333 | * GICR_CTLR.DPG1S |
| 334 | * GICR_CTLR.DPG1NS |
| 335 | * GICR_CTLR.DPG0 |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 336 | * GICR_CTLR, which clears EnableLPIs from 1 to 0 |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 337 | */ |
| 338 | static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) |
| 339 | { |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 340 | while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { |
| 341 | } |
Douglas Raillard | a1b1da8 | 2017-07-26 13:51:00 +0100 | [diff] [blame] | 342 | } |
| 343 | |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 344 | static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) |
| 345 | { |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 346 | while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { |
| 347 | } |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 348 | } |
| 349 | |
| 350 | /* Private implementation of Distributor power control hooks */ |
| 351 | void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); |
| 352 | void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); |
| 353 | |
Soby Mathew | 50f6fe4 | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 354 | /******************************************************************************* |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 355 | * GIC Redistributor functions for accessing entire registers. |
Soby Mathew | 50f6fe4 | 2016-02-01 17:59:22 +0000 | [diff] [blame] | 356 | * Note: The raw register values correspond to multiple interrupt IDs and |
| 357 | * the number of interrupt IDs involved depends on the register accessed. |
| 358 | ******************************************************************************/ |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 359 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 360 | /* |
| 361 | * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE |
| 362 | * register corresponding to its number |
| 363 | */ |
| 364 | static inline unsigned int gicr_read_icenabler(uintptr_t base, |
| 365 | unsigned int reg_num) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 366 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 367 | return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2)); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 368 | } |
| 369 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 370 | static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num, |
| 371 | unsigned int val) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 372 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 373 | mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 374 | } |
| 375 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 376 | /* |
| 377 | * Accessor to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE |
| 378 | * register corresponding to its number |
| 379 | */ |
| 380 | static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num) |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 381 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 382 | return mmio_read_32(base + GICR_ICFGR + (reg_num << 2)); |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 383 | } |
| 384 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 385 | static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num, |
| 386 | unsigned int val) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 387 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 388 | mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 389 | } |
| 390 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 391 | /* |
| 392 | * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE |
| 393 | * register corresponding to its number |
| 394 | */ |
| 395 | static inline unsigned int gicr_read_igroupr(uintptr_t base, |
| 396 | unsigned int reg_num) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 397 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 398 | return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2)); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 399 | } |
| 400 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 401 | static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num, |
| 402 | unsigned int val) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 403 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 404 | mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 405 | } |
| 406 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 407 | /* |
| 408 | * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE |
| 409 | * register corresponding to its number |
| 410 | */ |
| 411 | static inline unsigned int gicr_read_igrpmodr(uintptr_t base, |
| 412 | unsigned int reg_num) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 413 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 414 | return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2)); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 415 | } |
| 416 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 417 | static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num, |
| 418 | unsigned int val) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 419 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 420 | mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 421 | } |
| 422 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 423 | /* |
| 424 | * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register |
| 425 | * corresponding to its number, 4 interrupts IDs at a time. |
| 426 | */ |
| 427 | static inline unsigned int gicr_read_ipriorityr(uintptr_t base, |
| 428 | unsigned int reg_num) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 429 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 430 | return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2)); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 431 | } |
| 432 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 433 | static inline void gicr_write_ipriorityr(uintptr_t base, unsigned int reg_num, |
| 434 | unsigned int val) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 435 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 436 | mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 437 | } |
| 438 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 439 | /* |
| 440 | * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE |
| 441 | * register corresponding to its number |
| 442 | */ |
| 443 | static inline unsigned int gicr_read_isactiver(uintptr_t base, |
| 444 | unsigned int reg_num) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 445 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 446 | return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2)); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 447 | } |
| 448 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 449 | static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num, |
| 450 | unsigned int val) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 451 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 452 | mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 453 | } |
| 454 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 455 | /* |
| 456 | * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE |
| 457 | * register corresponding to its number |
| 458 | */ |
| 459 | static inline unsigned int gicr_read_isenabler(uintptr_t base, |
| 460 | unsigned int reg_num) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 461 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 462 | return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2)); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 463 | } |
| 464 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 465 | static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num, |
| 466 | unsigned int val) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 467 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 468 | mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 469 | } |
| 470 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 471 | /* |
| 472 | * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE |
| 473 | * register corresponding to its number |
| 474 | */ |
| 475 | static inline unsigned int gicr_read_ispendr(uintptr_t base, |
| 476 | unsigned int reg_num) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 477 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 478 | return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2)); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 479 | } |
| 480 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 481 | static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num, |
| 482 | unsigned int val) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 483 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 484 | mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 485 | } |
| 486 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 487 | /* |
| 488 | * Accessors to read/write GIC Redistributor NSACR register |
| 489 | */ |
| 490 | static inline unsigned int gicr_read_nsacr(uintptr_t base) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 491 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 492 | return mmio_read_32(base + GICR_NSACR); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 493 | } |
| 494 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 495 | static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 496 | { |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 497 | mmio_write_32(base + GICR_NSACR, val); |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 498 | } |
| 499 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 500 | /* |
| 501 | * Accessors to read/write GIC Redistributor PROPBASER register |
| 502 | */ |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 503 | static inline uint64_t gicr_read_propbaser(uintptr_t base) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 504 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 505 | return mmio_read_64(base + GICR_PROPBASER); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 506 | } |
| 507 | |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 508 | static inline void gicr_write_propbaser(uintptr_t base, uint64_t val) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 509 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 510 | mmio_write_64(base + GICR_PROPBASER, val); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 511 | } |
| 512 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame^] | 513 | /* |
| 514 | * Accessors to read/write GIC Redistributor PENDBASER register |
| 515 | */ |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 516 | static inline uint64_t gicr_read_pendbaser(uintptr_t base) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 517 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 518 | return mmio_read_64(base + GICR_PENDBASER); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 519 | } |
| 520 | |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 521 | static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val) |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 522 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 523 | mmio_write_64(base + GICR_PENDBASER, val); |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 524 | } |
| 525 | |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 526 | /******************************************************************************* |
| 527 | * GIC ITS functions to read and write entire ITS registers. |
| 528 | ******************************************************************************/ |
| 529 | static inline uint32_t gits_read_ctlr(uintptr_t base) |
| 530 | { |
| 531 | return mmio_read_32(base + GITS_CTLR); |
| 532 | } |
| 533 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 534 | static inline void gits_write_ctlr(uintptr_t base, uint32_t val) |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 535 | { |
| 536 | mmio_write_32(base + GITS_CTLR, val); |
| 537 | } |
| 538 | |
| 539 | static inline uint64_t gits_read_cbaser(uintptr_t base) |
| 540 | { |
| 541 | return mmio_read_64(base + GITS_CBASER); |
| 542 | } |
| 543 | |
| 544 | static inline void gits_write_cbaser(uintptr_t base, uint64_t val) |
| 545 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 546 | mmio_write_64(base + GITS_CBASER, val); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 547 | } |
| 548 | |
| 549 | static inline uint64_t gits_read_cwriter(uintptr_t base) |
| 550 | { |
| 551 | return mmio_read_64(base + GITS_CWRITER); |
| 552 | } |
| 553 | |
| 554 | static inline void gits_write_cwriter(uintptr_t base, uint64_t val) |
| 555 | { |
Antonio Nino Diaz | bab39e8 | 2018-08-21 10:03:07 +0100 | [diff] [blame] | 556 | mmio_write_64(base + GITS_CWRITER, val); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 557 | } |
| 558 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 559 | static inline uint64_t gits_read_baser(uintptr_t base, |
| 560 | unsigned int its_table_id) |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 561 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 562 | assert(its_table_id < 8U); |
| 563 | return mmio_read_64(base + GITS_BASER + (8U * its_table_id)); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 564 | } |
| 565 | |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 566 | static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, |
| 567 | uint64_t val) |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 568 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 569 | assert(its_table_id < 8U); |
| 570 | mmio_write_64(base + GITS_BASER + (8U * its_table_id), val); |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | /* |
| 574 | * Wait for Quiescent bit when GIC ITS is disabled |
| 575 | */ |
| 576 | static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) |
| 577 | { |
Antonio Nino Diaz | ca994e7 | 2018-08-21 10:02:33 +0100 | [diff] [blame] | 578 | assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); |
Alexei Fedorov | 2f13d6c | 2020-02-21 10:17:26 +0000 | [diff] [blame] | 579 | while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) { |
| 580 | } |
Soby Mathew | f6f1a32 | 2017-07-18 16:12:45 +0100 | [diff] [blame] | 581 | } |
| 582 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 583 | #endif /* GICV3_PRIVATE_H */ |