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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
7#ifndef __GICV3_PRIVATE_H__
8#define __GICV3_PRIVATE_H__
9
Soby Mathew327548c2017-07-13 15:19:51 +010010#include <assert.h>
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000011#include <gic_common.h>
Achin Gupta92712a52015-09-03 14:18:02 +010012#include <gicv3.h>
13#include <mmio.h>
14#include <stdint.h>
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000015#include "../common/gic_common_private.h"
Achin Gupta92712a52015-09-03 14:18:02 +010016
17/*******************************************************************************
18 * GICv3 private macro definitions
19 ******************************************************************************/
20
21/* Constants to indicate the status of the RWP bit */
22#define RWP_TRUE 1
23#define RWP_FALSE 0
24
25/*
Achin Gupta92712a52015-09-03 14:18:02 +010026 * Macro to convert an mpidr to a value suitable for programming into a
27 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
28 * to GICv3.
29 */
30#define gicd_irouter_val_from_mpidr(mpidr, irm) \
31 ((mpidr & ~(0xff << 24)) | \
32 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
33
34/*
Achin Gupta92712a52015-09-03 14:18:02 +010035 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
36 * are zeroes.
37 */
Soby Mathewd6452322016-05-05 13:59:07 +010038#ifdef AARCH32
39#define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff)
40#else
Achin Gupta92712a52015-09-03 14:18:02 +010041#define mpidr_from_gicr_typer(typer_val) \
Soby Mathewd6452322016-05-05 13:59:07 +010042 (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
43 (((typer_val) >> 32) & 0xffffff))
44#endif
Achin Gupta92712a52015-09-03 14:18:02 +010045
46/*******************************************************************************
Soby Mathew327548c2017-07-13 15:19:51 +010047 * GICv3 private global variables declarations
48 ******************************************************************************/
49extern const gicv3_driver_data_t *gicv3_driver_data;
50
51/*******************************************************************************
Soby Mathew50f6fe42016-02-01 17:59:22 +000052 * Private GICv3 function prototypes for accessing entire registers.
53 * Note: The raw register values correspond to multiple interrupt IDs and
54 * the number of interrupt IDs involved depends on the register accessed.
Achin Gupta92712a52015-09-03 14:18:02 +010055 ******************************************************************************/
56unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
57unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
Soby Mathew50f6fe42016-02-01 17:59:22 +000058void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
59void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
60
61/*******************************************************************************
62 * Private GICv3 function prototypes for accessing the GIC registers
63 * corresponding to a single interrupt ID. These functions use bitwise
64 * operations or appropriate register accesses to modify or return
65 * the bit-field corresponding the single interrupt ID.
66 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +010067unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
68unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id);
69unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id);
Achin Gupta92712a52015-09-03 14:18:02 +010070void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
71void gicr_set_igrpmodr0(uintptr_t base, unsigned int id);
72void gicr_set_isenabler0(uintptr_t base, unsigned int id);
73void gicr_set_igroupr0(uintptr_t base, unsigned int id);
74void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
75void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id);
76void gicr_clr_igroupr0(uintptr_t base, unsigned int id);
Soby Mathew50f6fe42016-02-01 17:59:22 +000077void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
78
79/*******************************************************************************
80 * Private GICv3 helper function prototypes
81 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +010082void gicv3_spis_configure_defaults(uintptr_t gicd_base);
83void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base);
84void gicv3_secure_spis_configure(uintptr_t gicd_base,
85 unsigned int num_ints,
86 const unsigned int *sec_intr_list,
87 unsigned int int_grp);
88void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
89 unsigned int num_ints,
90 const unsigned int *sec_intr_list,
91 unsigned int int_grp);
92void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
93 unsigned int rdistif_num,
94 uintptr_t gicr_base,
95 mpidr_hash_fn mpidr_to_core_pos);
96void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
97void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
98
99/*******************************************************************************
100 * GIC Distributor interface accessors
101 ******************************************************************************/
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100102/*
103 * Wait for updates to :
104 * GICD_CTLR[2:0] - the Group Enables
105 * GICD_CTLR[5:4] - the ARE bits
106 * GICD_ICENABLERn - the clearing of enable state for SPIs
107 */
108static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
109{
110 while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT)
111 ;
112}
113
Achin Gupta92712a52015-09-03 14:18:02 +0100114static inline unsigned int gicd_read_pidr2(uintptr_t base)
115{
116 return mmio_read_32(base + GICD_PIDR2_GICV3);
117}
118
119static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id)
120{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100121 assert(id >= MIN_SPI_ID);
Achin Gupta92712a52015-09-03 14:18:02 +0100122 return mmio_read_64(base + GICD_IROUTER + (id << 3));
123}
124
125static inline void gicd_write_irouter(uintptr_t base,
126 unsigned int id,
127 unsigned long long affinity)
128{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100129 assert(id >= MIN_SPI_ID);
Achin Gupta92712a52015-09-03 14:18:02 +0100130 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity);
131}
132
133static inline void gicd_clr_ctlr(uintptr_t base,
134 unsigned int bitmap,
135 unsigned int rwp)
136{
137 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
138 if (rwp)
139 gicd_wait_for_pending_write(base);
140}
141
142static inline void gicd_set_ctlr(uintptr_t base,
143 unsigned int bitmap,
144 unsigned int rwp)
145{
146 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
147 if (rwp)
148 gicd_wait_for_pending_write(base);
149}
150
151/*******************************************************************************
152 * GIC Redistributor interface accessors
153 ******************************************************************************/
154static inline unsigned long long gicr_read_ctlr(uintptr_t base)
155{
156 return mmio_read_64(base + GICR_CTLR);
157}
158
Soby Mathew327548c2017-07-13 15:19:51 +0100159static inline void gicr_write_ctlr(uintptr_t base, uint64_t val)
160{
161 mmio_write_64(base + GICR_CTLR, val);
162}
163
Achin Gupta92712a52015-09-03 14:18:02 +0100164static inline unsigned long long gicr_read_typer(uintptr_t base)
165{
166 return mmio_read_64(base + GICR_TYPER);
167}
168
169static inline unsigned int gicr_read_waker(uintptr_t base)
170{
171 return mmio_read_32(base + GICR_WAKER);
172}
173
174static inline void gicr_write_waker(uintptr_t base, unsigned int val)
175{
176 mmio_write_32(base + GICR_WAKER, val);
177}
178
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100179/*
180 * Wait for updates to :
181 * GICR_ICENABLER0
182 * GICR_CTLR.DPG1S
183 * GICR_CTLR.DPG1NS
184 * GICR_CTLR.DPG0
185 */
186static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
187{
188 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT)
189 ;
190}
191
Soby Mathew327548c2017-07-13 15:19:51 +0100192static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
193{
194 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT)
195 ;
196}
197
198/* Private implementation of Distributor power control hooks */
199void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num);
200void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num);
201
Soby Mathew50f6fe42016-02-01 17:59:22 +0000202/*******************************************************************************
203 * GIC Re-distributor functions for accessing entire registers.
204 * Note: The raw register values correspond to multiple interrupt IDs and
205 * the number of interrupt IDs involved depends on the register accessed.
206 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +0100207static inline unsigned int gicr_read_icenabler0(uintptr_t base)
208{
209 return mmio_read_32(base + GICR_ICENABLER0);
210}
211
212static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
213{
214 mmio_write_32(base + GICR_ICENABLER0, val);
215}
216
217static inline unsigned int gicr_read_isenabler0(uintptr_t base)
218{
219 return mmio_read_32(base + GICR_ISENABLER0);
220}
221
222static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
223{
224 mmio_write_32(base + GICR_ISENABLER0, val);
225}
226
227static inline unsigned int gicr_read_igroupr0(uintptr_t base)
228{
229 return mmio_read_32(base + GICR_IGROUPR0);
230}
231
Soby Mathew327548c2017-07-13 15:19:51 +0100232static inline unsigned int gicr_read_ispendr0(uintptr_t base)
233{
234 return mmio_read_32(base + GICR_ISPENDR0);
235}
236
237static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val)
238{
239 mmio_write_32(base + GICR_ISPENDR0, val);
240}
241
Achin Gupta92712a52015-09-03 14:18:02 +0100242static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
243{
244 mmio_write_32(base + GICR_IGROUPR0, val);
245}
246
247static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
248{
249 return mmio_read_32(base + GICR_IGRPMODR0);
250}
251
252static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
253{
254 mmio_write_32(base + GICR_IGRPMODR0, val);
255}
256
Soby Mathew327548c2017-07-13 15:19:51 +0100257static inline unsigned int gicr_read_nsacr(uintptr_t base)
258{
259 return mmio_read_32(base + GICR_NSACR);
260}
261
262static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
263{
264 mmio_write_32(base + GICR_NSACR, val);
265}
266
267static inline unsigned int gicr_read_isactiver0(uintptr_t base)
268{
269 return mmio_read_32(base + GICR_ISACTIVER0);
270}
271
272static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val)
273{
274 mmio_write_32(base + GICR_ISACTIVER0, val);
275}
276
277static inline unsigned int gicr_read_icfgr0(uintptr_t base)
278{
279 return mmio_read_32(base + GICR_ICFGR0);
280}
281
Achin Gupta92712a52015-09-03 14:18:02 +0100282static inline unsigned int gicr_read_icfgr1(uintptr_t base)
283{
284 return mmio_read_32(base + GICR_ICFGR1);
285}
286
Soby Mathew327548c2017-07-13 15:19:51 +0100287static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val)
288{
289 mmio_write_32(base + GICR_ICFGR0, val);
290}
291
Achin Gupta92712a52015-09-03 14:18:02 +0100292static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
293{
294 mmio_write_32(base + GICR_ICFGR1, val);
295}
296
Soby Mathew327548c2017-07-13 15:19:51 +0100297static inline unsigned int gicr_read_propbaser(uintptr_t base)
298{
299 return mmio_read_32(base + GICR_PROPBASER);
300}
301
302static inline void gicr_write_propbaser(uintptr_t base, unsigned int val)
303{
304 mmio_write_32(base + GICR_PROPBASER, val);
305}
306
307static inline unsigned int gicr_read_pendbaser(uintptr_t base)
308{
309 return mmio_read_32(base + GICR_PENDBASER);
310}
311
312static inline void gicr_write_pendbaser(uintptr_t base, unsigned int val)
313{
314 mmio_write_32(base + GICR_PENDBASER, val);
315}
316
Achin Gupta92712a52015-09-03 14:18:02 +0100317#endif /* __GICV3_PRIVATE_H__ */