GICv3: Fix the GICD_IROUTER offset
This patch fixes the offset of GICD_IROUTER register defined in gicv3.h.
Although the GICv3 documention mentions that the offset for this register
is 0x6100-0x7FD8, the offset calculation for an interrupt id `n` is :
0x6000 + 8n, where n >= 32
This requires the offset for GICD_IROUTER to be defined as 0x6000.
Fixes ARM-software/tf-issues#410
Change-Id: If9e91e30d946afe7f1f60fea4f065c7567093fa8
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 5e2409f..9aa8338 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -141,6 +141,7 @@
static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id)
{
+ assert(id >= MIN_SPI_ID);
return mmio_read_64(base + GICD_IROUTER + (id << 3));
}
@@ -148,6 +149,7 @@
unsigned int id,
unsigned long long affinity)
{
+ assert(id >= MIN_SPI_ID);
mmio_write_64(base + GICD_IROUTER + (id << 3), affinity);
}