AArch32: Enable GIC and TZC support
This patch modifies GICv3 and TZC drivers to add AArch32 support.
No modifications are required for the GICv2 driver for AArch32 support.
The TZC driver assumes that the secure world is running in Little-Endian
mode to do 64 bit manipulations. Assertions are present to validate the
assumption.
Note: The legacy GICv3 driver is not supported for AArch32.
Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 9aa8338..1344a88 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -79,9 +79,13 @@
* Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
* are zeroes.
*/
+#ifdef AARCH32
+#define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff)
+#else
#define mpidr_from_gicr_typer(typer_val) \
- ((((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
- ((typer_val >> 32) & 0xffffff))
+ (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
+ (((typer_val) >> 32) & 0xffffff))
+#endif
/*******************************************************************************
* Private GICv3 function prototypes for accessing entire registers.