TF-A GICv3 driver: Add extended PPI and SPI range
This patch provides support for GICv3.1 extended PPI and SPI
range. The option is enabled by setting to 1 and passing
`GIC_EXT_INTID` build flag to gicv3.mk makefile.
This option defaults to 0 with no extended range support.
Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index dae01cb..26c8de5 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -26,39 +26,59 @@
/* Calculate GIC register bit number corresponding to its interrupt ID */
#define BIT_NUM(REG, id) \
- ((id) & ((1U << REG##_SHIFT) - 1U))
+ ((id) & ((1U << REG##R_SHIFT) - 1U))
-/* Calculate 8-bit GICD register offset corresponding to its interrupt ID */
+/*
+ * Calculate 8, 32 and 64-bit GICD register offset
+ * corresponding to its interrupt ID
+ */
+#if GIC_EXT_INTID
+ /* GICv3.1 */
+#define GICD_OFFSET_8(REG, id) \
+ (((id) <= MAX_SPI_ID) ? \
+ GICD_##REG##R + (uintptr_t)(id) : \
+ GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID)
+
+#define GICD_OFFSET(REG, id) \
+ (((id) <= MAX_SPI_ID) ? \
+ GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
+ GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
+ REG##R_SHIFT) << 2))
+
+#define GICD_OFFSET_64(REG, id) \
+ (((id) <= MAX_SPI_ID) ? \
+ GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
+ GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3))
+
+#else /* GICv3 */
#define GICD_OFFSET_8(REG, id) \
- GICD_##REG + (id)
+ (GICD_##REG##R + (uintptr_t)(id))
-/* Calculate 32-bit GICD register offset corresponding to its interrupt ID */
#define GICD_OFFSET(REG, id) \
- GICD_##REG + (((id) >> REG##_SHIFT) << 2)
+ (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
-/* Calculate 64-bit GICD register offset corresponding to its interrupt ID */
#define GICD_OFFSET_64(REG, id) \
- GICD_##REG + (((id) >> REG##_SHIFT) << 3)
+ (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3))
+#endif /* GIC_EXT_INTID */
-/* Read 32-bit GIC Distributor register corresponding to its interrupt ID */
+/*
+ * Read/Write 8, 32 and 64-bit GIC Distributor register
+ * corresponding to its interrupt ID
+ */
#define GICD_READ(REG, base, id) \
mmio_read_32((base) + GICD_OFFSET(REG, (id)))
-/* Read 64-bit GIC Distributor register corresponding to its interrupt ID */
#define GICD_READ_64(REG, base, id) \
mmio_read_64((base) + GICD_OFFSET_64(REG, (id)))
-/* Write to 64-bit GIC Distributor register corresponding to its interrupt ID */
-#define GICD_WRITE_64(REG, base, id, val) \
- mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
+#define GICD_WRITE_8(REG, base, id, val) \
+ mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
-/* Write to 32-bit GIC Distributor register corresponding to its interrupt ID */
-#define GICD_WRITE(REG, base, id, val) \
+#define GICD_WRITE(REG, base, id, val) \
mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val))
-/* Write to 8-bit GIC Distributor register corresponding to its interrupt ID */
-#define GICD_WRITE_8(REG, base, id, val) \
- mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
+#define GICD_WRITE_64(REG, base, id, val) \
+ mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
/*
* Bit operations on GIC Distributor register corresponding
@@ -80,19 +100,43 @@
((uint32_t)1 << BIT_NUM(REG, (id))))
/* Write bit in GIC Distributor register */
-#define GICD_WRITE_BIT(REG, base, id) \
+#define GICD_WRITE_BIT(REG, base, id) \
mmio_write_32((base) + GICD_OFFSET(REG, (id)), \
((uint32_t)1 << BIT_NUM(REG, (id))))
/*
- * Calculate GICv3 GICR register offset
+ * Calculate 8 and 32-bit GICR register offset
+ * corresponding to its interrupt ID
*/
+#if GIC_EXT_INTID
+ /* GICv3.1 */
+#define GICR_OFFSET_8(REG, id) \
+ (((id) <= MAX_PPI_ID) ? \
+ GICR_##REG##R + (uintptr_t)(id) : \
+ GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))
+
+#define GICR_OFFSET(REG, id) \
+ (((id) <= MAX_PPI_ID) ? \
+ GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
+ GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\
+ >> REG##R_SHIFT) << 2))
+#else /* GICv3 */
+#define GICR_OFFSET_8(REG, id) \
+ (GICR_##REG##R + (uintptr_t)(id))
+
#define GICR_OFFSET(REG, id) \
- GICR_##REG + (((id) >> REG##_SHIFT) << 2)
+ (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
+#endif
-/* Write to GIC Redistributor register corresponding to its interrupt ID */
-#define GICR_WRITE_8(REG, base, id, val) \
- mmio_write_8((base) + GICR_##REG + (id), (val))
+/* Read/Write GIC Redistributor register corresponding to its interrupt ID */
+#define GICR_READ(REG, base, id) \
+ mmio_read_32((base) + GICR_OFFSET(REG, (id)))
+
+#define GICR_WRITE_8(REG, base, id, val) \
+ mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val))
+
+#define GICR_WRITE(REG, base, id, val) \
+ mmio_write((base) + GICR_OFFSET(REG, (id)), (val))
/*
* Bit operations on GIC Redistributor register
@@ -105,7 +149,7 @@
/* Write bit in GIC Redistributor register */
#define GICR_WRITE_BIT(REG, base, id) \
- mmio_write_32((base) + GICR_OFFSET(REG, (id)), \
+ mmio_write_32((base) + GICR_OFFSET(REG, (id)), \
((uint32_t)1 << BIT_NUM(REG, (id))))
/* Set bit in GIC Redistributor register */
@@ -157,10 +201,8 @@
* Note: The raw register values correspond to multiple interrupt IDs and
* the number of interrupt IDs involved depends on the register accessed.
******************************************************************************/
-uint32_t gicd_read_igrpmodr(uintptr_t base, unsigned int id);
-unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
-void gicd_write_igrpmodr(uintptr_t base, unsigned int id, uint32_t val);
-void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
+unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
+void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
/*******************************************************************************
* Private GICv3 function prototypes for accessing the GIC registers
@@ -169,22 +211,21 @@
* the bit-field corresponding the single interrupt ID.
******************************************************************************/
unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
-unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id);
-unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id);
-unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id);
+unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id);
+unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id);
+unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id);
void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
-void gicr_set_igrpmodr0(uintptr_t base, unsigned int id);
-void gicr_set_isenabler0(uintptr_t base, unsigned int id);
-void gicr_set_icenabler0(uintptr_t base, unsigned int id);
-void gicr_set_ispendr0(uintptr_t base, unsigned int id);
-void gicr_set_icpendr0(uintptr_t base, unsigned int id);
-void gicr_set_igroupr0(uintptr_t base, unsigned int id);
+void gicr_set_igrpmodr(uintptr_t base, unsigned int id);
+void gicr_set_isenabler(uintptr_t base, unsigned int id);
+void gicr_set_icenabler(uintptr_t base, unsigned int id);
+void gicr_set_ispendr(uintptr_t base, unsigned int id);
+void gicr_set_icpendr(uintptr_t base, unsigned int id);
+void gicr_set_igroupr(uintptr_t base, unsigned int id);
void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
-void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id);
-void gicr_clr_igroupr0(uintptr_t base, unsigned int id);
+void gicr_clr_igrpmodr(uintptr_t base, unsigned int id);
+void gicr_clr_igroupr(uintptr_t base, unsigned int id);
void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
-void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg);
-void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg);
+void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg);
/*******************************************************************************
* Private GICv3 helper function prototypes
@@ -208,10 +249,10 @@
* GIC Distributor interface accessors
******************************************************************************/
/*
- * Wait for updates to :
+ * Wait for updates to:
* GICD_CTLR[2:0] - the Group Enables
- * GICD_CTLR[5:4] - the ARE bits
- * GICD_ICENABLERn - the clearing of enable state for SPIs
+ * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit
+ * GICD_ICENABLER<n> - the clearing of enable state for SPIs
*/
static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
{
@@ -227,7 +268,7 @@
static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id)
{
assert(id >= MIN_SPI_ID);
- return GICD_READ_64(IROUTER, base, id);
+ return GICD_READ_64(IROUTE, base, id);
}
static inline void gicd_write_irouter(uintptr_t base,
@@ -235,7 +276,7 @@
uint64_t affinity)
{
assert(id >= MIN_SPI_ID);
- GICD_WRITE_64(IROUTER, base, id, affinity);
+ GICD_WRITE_64(IROUTE, base, id, affinity);
}
static inline void gicd_clr_ctlr(uintptr_t base,
@@ -287,11 +328,12 @@
}
/*
- * Wait for updates to :
+ * Wait for updates to:
* GICR_ICENABLER0
* GICR_CTLR.DPG1S
* GICR_CTLR.DPG1NS
* GICR_CTLR.DPG0
+ * GICR_CTLR, which clears EnableLPIs from 1 to 0
*/
static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
{
@@ -314,101 +356,150 @@
* Note: The raw register values correspond to multiple interrupt IDs and
* the number of interrupt IDs involved depends on the register accessed.
******************************************************************************/
-static inline unsigned int gicr_read_icenabler0(uintptr_t base)
-{
- return mmio_read_32(base + GICR_ICENABLER0);
-}
-static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
+/*
+ * Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE
+ * register corresponding to its number
+ */
+static inline unsigned int gicr_read_icenabler(uintptr_t base,
+ unsigned int reg_num)
{
- mmio_write_32(base + GICR_ICENABLER0, val);
+ return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2));
}
-static inline unsigned int gicr_read_isenabler0(uintptr_t base)
+static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- return mmio_read_32(base + GICR_ISENABLER0);
+ mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val);
}
-static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val)
+/*
+ * Accessor to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE
+ * register corresponding to its number
+ */
+static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num)
{
- mmio_write_32(base + GICR_ICPENDR0, val);
+ return mmio_read_32(base + GICR_ICFGR + (reg_num << 2));
}
-static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
+static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- mmio_write_32(base + GICR_ISENABLER0, val);
+ mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val);
}
-static inline unsigned int gicr_read_igroupr0(uintptr_t base)
+/*
+ * Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE
+ * register corresponding to its number
+ */
+static inline unsigned int gicr_read_igroupr(uintptr_t base,
+ unsigned int reg_num)
{
- return mmio_read_32(base + GICR_IGROUPR0);
+ return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2));
}
-static inline unsigned int gicr_read_ispendr0(uintptr_t base)
+static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- return mmio_read_32(base + GICR_ISPENDR0);
+ mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val);
}
-static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val)
+/*
+ * Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE
+ * register corresponding to its number
+ */
+static inline unsigned int gicr_read_igrpmodr(uintptr_t base,
+ unsigned int reg_num)
{
- mmio_write_32(base + GICR_ISPENDR0, val);
+ return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2));
}
-static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
+static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- mmio_write_32(base + GICR_IGROUPR0, val);
+ mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val);
}
-static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
+/*
+ * Accessors to read/write the GIC Redistributor IPRIORITYR(E) register
+ * corresponding to its number, 4 interrupts IDs at a time.
+ */
+static inline unsigned int gicr_read_ipriorityr(uintptr_t base,
+ unsigned int reg_num)
{
- return mmio_read_32(base + GICR_IGRPMODR0);
+ return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2));
}
-static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
+static inline void gicr_write_ipriorityr(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- mmio_write_32(base + GICR_IGRPMODR0, val);
+ mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val);
}
-static inline unsigned int gicr_read_nsacr(uintptr_t base)
+/*
+ * Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE
+ * register corresponding to its number
+ */
+static inline unsigned int gicr_read_isactiver(uintptr_t base,
+ unsigned int reg_num)
{
- return mmio_read_32(base + GICR_NSACR);
+ return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2));
}
-static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
+static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- mmio_write_32(base + GICR_NSACR, val);
+ mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val);
}
-static inline unsigned int gicr_read_isactiver0(uintptr_t base)
+/*
+ * Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE
+ * register corresponding to its number
+ */
+static inline unsigned int gicr_read_isenabler(uintptr_t base,
+ unsigned int reg_num)
{
- return mmio_read_32(base + GICR_ISACTIVER0);
+ return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2));
}
-static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val)
+static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- mmio_write_32(base + GICR_ISACTIVER0, val);
+ mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val);
}
-static inline unsigned int gicr_read_icfgr0(uintptr_t base)
+/*
+ * Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE
+ * register corresponding to its number
+ */
+static inline unsigned int gicr_read_ispendr(uintptr_t base,
+ unsigned int reg_num)
{
- return mmio_read_32(base + GICR_ICFGR0);
+ return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2));
}
-static inline unsigned int gicr_read_icfgr1(uintptr_t base)
+static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num,
+ unsigned int val)
{
- return mmio_read_32(base + GICR_ICFGR1);
+ mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val);
}
-static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val)
+/*
+ * Accessors to read/write GIC Redistributor NSACR register
+ */
+static inline unsigned int gicr_read_nsacr(uintptr_t base)
{
- mmio_write_32(base + GICR_ICFGR0, val);
+ return mmio_read_32(base + GICR_NSACR);
}
-static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
+static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
{
- mmio_write_32(base + GICR_ICFGR1, val);
+ mmio_write_32(base + GICR_NSACR, val);
}
+/*
+ * Accessors to read/write GIC Redistributor PROPBASER register
+ */
static inline uint64_t gicr_read_propbaser(uintptr_t base)
{
return mmio_read_64(base + GICR_PROPBASER);
@@ -419,6 +510,9 @@
mmio_write_64(base + GICR_PROPBASER, val);
}
+/*
+ * Accessors to read/write GIC Redistributor PENDBASER register
+ */
static inline uint64_t gicr_read_pendbaser(uintptr_t base)
{
return mmio_read_64(base + GICR_PENDBASER);