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Soby Mathew991d42c2015-06-29 16:30:12 +01001/*
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Soby Mathew991d42c2015-06-29 16:30:12 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew991d42c2015-06-29 16:30:12 +01005 */
6
Soby Mathew991d42c2015-06-29 16:30:12 +01007#include <assert.h>
Soby Mathew991d42c2015-06-29 16:30:12 +01008#include <stddef.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <lib/el3_runtime/context_mgmt.h>
15#include <lib/el3_runtime/pubsub_events.h>
16#include <plat/common/platform.h>
17
Soby Mathew991d42c2015-06-29 16:30:12 +010018#include "psci_private.h"
19
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010020/*
21 * Helper functions for the CPU level spinlocks
22 */
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060023static inline void psci_spin_lock_cpu(unsigned int idx)
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010024{
25 spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock);
26}
27
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060028static inline void psci_spin_unlock_cpu(unsigned int idx)
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010029{
30 spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock);
31}
32
Soby Mathew991d42c2015-06-29 16:30:12 +010033/*******************************************************************************
34 * This function checks whether a cpu which has been requested to be turned on
35 * is OFF to begin with.
36 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +010037static int cpu_on_validate_state(aff_info_state_t aff_state)
Soby Mathew991d42c2015-06-29 16:30:12 +010038{
Soby Mathew85dbf5a2015-04-07 12:16:56 +010039 if (aff_state == AFF_STATE_ON)
Soby Mathew991d42c2015-06-29 16:30:12 +010040 return PSCI_E_ALREADY_ON;
41
Soby Mathew85dbf5a2015-04-07 12:16:56 +010042 if (aff_state == AFF_STATE_ON_PENDING)
Soby Mathew991d42c2015-06-29 16:30:12 +010043 return PSCI_E_ON_PENDING;
44
Soby Mathew85dbf5a2015-04-07 12:16:56 +010045 assert(aff_state == AFF_STATE_OFF);
Soby Mathew991d42c2015-06-29 16:30:12 +010046 return PSCI_E_SUCCESS;
47}
48
49/*******************************************************************************
Soby Mathew991d42c2015-06-29 16:30:12 +010050 * Generic handler which is called to physically power on a cpu identified by
Soby Mathew6b8b3022015-06-30 11:00:24 +010051 * its mpidr. It performs the generic, architectural, platform setup and state
52 * management to power on the target cpu e.g. it will ensure that
53 * enough information is stashed for it to resume execution in the non-secure
54 * security state.
Soby Mathew991d42c2015-06-29 16:30:12 +010055 *
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010056 * The state of all the relevant power domains are changed after calling the
Soby Mathew6b8b3022015-06-30 11:00:24 +010057 * platform handler as it can return error.
Soby Mathew991d42c2015-06-29 16:30:12 +010058 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010059int psci_cpu_on_start(u_register_t target_cpu,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010060 const entry_point_info_t *ep)
Soby Mathew991d42c2015-06-29 16:30:12 +010061{
62 int rc;
Soby Mathewca370502016-01-26 11:47:53 +000063 aff_info_state_t target_aff_state;
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060064 int ret = plat_core_pos_by_mpidr(target_cpu);
65 unsigned int target_idx = (unsigned int)ret;
Soby Mathew991d42c2015-06-29 16:30:12 +010066
Sandrine Bailleux6181acb2016-04-22 13:00:19 +010067 /* Calling function must supply valid input arguments */
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060068 assert(ret >= 0);
Sandrine Bailleux6181acb2016-04-22 13:00:19 +010069 assert(ep != NULL);
70
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060071
Soby Mathew991d42c2015-06-29 16:30:12 +010072 /*
73 * This function must only be called on platforms where the
74 * CPU_ON platform hooks have been implemented.
75 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010076 assert((psci_plat_pm_ops->pwr_domain_on != NULL) &&
77 (psci_plat_pm_ops->pwr_domain_on_finish != NULL));
Soby Mathew991d42c2015-06-29 16:30:12 +010078
Soby Mathew9d754f62015-04-08 17:42:06 +010079 /* Protect against multiple CPUs trying to turn ON the same target CPU */
80 psci_spin_lock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010081
82 /*
Soby Mathew991d42c2015-06-29 16:30:12 +010083 * Generic management: Ensure that the cpu is off to be
84 * turned on.
David Cunado06adba22017-07-19 12:14:07 +010085 * Perform cache maintanence ahead of reading the target CPU state to
86 * ensure that the data is not stale.
87 * There is a theoretical edge case where the cache may contain stale
88 * data for the target CPU data - this can occur under the following
89 * conditions:
90 * - the target CPU is in another cluster from the current
91 * - the target CPU was the last CPU to shutdown on its cluster
92 * - the cluster was removed from coherency as part of the CPU shutdown
93 *
94 * In this case the cache maintenace that was performed as part of the
95 * target CPUs shutdown was not seen by the current CPU's cluster. And
96 * so the cache may contain stale data for the target CPU.
Soby Mathew991d42c2015-06-29 16:30:12 +010097 */
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060098 flush_cpu_data_by_index(target_idx,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010099 psci_svc_cpu_data.aff_info_state);
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100100 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
Soby Mathew991d42c2015-06-29 16:30:12 +0100101 if (rc != PSCI_E_SUCCESS)
102 goto exit;
103
104 /*
105 * Call the cpu on handler registered by the Secure Payload Dispatcher
106 * to let it do any bookeeping. If the handler encounters an error, it's
107 * expected to assert within
108 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100109 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL))
Soby Mathew991d42c2015-06-29 16:30:12 +0100110 psci_spd_pm->svc_on(target_cpu);
111
112 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100113 * Set the Affinity info state of the target cpu to ON_PENDING.
Soby Mathewca370502016-01-26 11:47:53 +0000114 * Flush aff_info_state as it will be accessed with caches
115 * turned OFF.
Soby Mathew991d42c2015-06-29 16:30:12 +0100116 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100117 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600118 flush_cpu_data_by_index(target_idx,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100119 psci_svc_cpu_data.aff_info_state);
Soby Mathewca370502016-01-26 11:47:53 +0000120
121 /*
122 * The cache line invalidation by the target CPU after setting the
123 * state to OFF (see psci_do_cpu_off()), could cause the update to
124 * aff_info_state to be invalidated. Retry the update if the target
125 * CPU aff_info_state is not ON_PENDING.
126 */
127 target_aff_state = psci_get_aff_info_state_by_idx(target_idx);
128 if (target_aff_state != AFF_STATE_ON_PENDING) {
129 assert(target_aff_state == AFF_STATE_OFF);
130 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600131 flush_cpu_data_by_index(target_idx,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100132 psci_svc_cpu_data.aff_info_state);
Soby Mathewca370502016-01-26 11:47:53 +0000133
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100134 assert(psci_get_aff_info_state_by_idx(target_idx) ==
135 AFF_STATE_ON_PENDING);
Soby Mathewca370502016-01-26 11:47:53 +0000136 }
Soby Mathew6b8b3022015-06-30 11:00:24 +0100137
138 /*
139 * Perform generic, architecture and platform specific handling.
140 */
Soby Mathew6b8b3022015-06-30 11:00:24 +0100141 /*
142 * Plat. management: Give the platform the current state
143 * of the target cpu to allow it to perform the necessary
144 * steps to power on.
145 */
Soby Mathew011ca182015-07-29 17:05:03 +0100146 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100147 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
Soby Mathew991d42c2015-06-29 16:30:12 +0100148
149 if (rc == PSCI_E_SUCCESS)
150 /* Store the re-entry information for the non-secure world. */
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600151 cm_init_context_by_index(target_idx, ep);
Soby Mathewca370502016-01-26 11:47:53 +0000152 else {
Soby Mathew991d42c2015-06-29 16:30:12 +0100153 /* Restore the state on error. */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100154 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600155 flush_cpu_data_by_index(target_idx,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100156 psci_svc_cpu_data.aff_info_state);
Soby Mathewca370502016-01-26 11:47:53 +0000157 }
Soby Mathewb0082d22015-04-09 13:40:55 +0100158
Soby Mathew991d42c2015-06-29 16:30:12 +0100159exit:
Soby Mathew9d754f62015-04-08 17:42:06 +0100160 psci_spin_unlock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +0100161 return rc;
162}
163
164/*******************************************************************************
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100165 * The following function finish an earlier power on request. They
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100166 * are called by the common finisher routine in psci_common.c. The `state_info`
167 * is the psci_power_state from which this CPU has woken up from.
Soby Mathew991d42c2015-06-29 16:30:12 +0100168 ******************************************************************************/
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600169void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +0100170{
Soby Mathew991d42c2015-06-29 16:30:12 +0100171 /*
172 * Plat. management: Perform the platform specific actions
173 * for this cpu e.g. enabling the gic or zeroing the mailbox
174 * register. The actual state of this cpu has already been
175 * changed.
176 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100177 psci_plat_pm_ops->pwr_domain_on_finish(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100178
Soby Mathew043fe9c2017-04-10 22:35:42 +0100179#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Soby Mathew991d42c2015-06-29 16:30:12 +0100180 /*
181 * Arch. management: Enable data cache and manage stack memory
182 */
183 psci_do_pwrup_cache_maintenance();
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000184#endif
Soby Mathew991d42c2015-06-29 16:30:12 +0100185
186 /*
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -0500187 * Plat. management: Perform any platform specific actions which
188 * can only be done with the cpu and the cluster guaranteed to
189 * be coherent.
190 */
191 if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL)
192 psci_plat_pm_ops->pwr_domain_on_finish_late(state_info);
193
194 /*
Soby Mathew991d42c2015-06-29 16:30:12 +0100195 * All the platform specific actions for turning this cpu
196 * on have completed. Perform enough arch.initialization
197 * to run in the non-secure address space.
198 */
Soby Mathewd0194872016-04-29 19:01:30 +0100199 psci_arch_setup();
Soby Mathew991d42c2015-06-29 16:30:12 +0100200
201 /*
Soby Mathew9d754f62015-04-08 17:42:06 +0100202 * Lock the CPU spin lock to make sure that the context initialization
203 * is done. Since the lock is only used in this function to create
204 * a synchronization point with cpu_on_start(), it can be released
205 * immediately.
206 */
207 psci_spin_lock_cpu(cpu_idx);
208 psci_spin_unlock_cpu(cpu_idx);
209
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100210 /* Ensure we have been explicitly woken up by another cpu */
211 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING);
212
Soby Mathew9d754f62015-04-08 17:42:06 +0100213 /*
Soby Mathew991d42c2015-06-29 16:30:12 +0100214 * Call the cpu on finish handler registered by the Secure Payload
215 * Dispatcher to let it do any bookeeping. If the handler encounters an
216 * error, it's expected to assert within
217 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100218 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL))
Soby Mathew991d42c2015-06-29 16:30:12 +0100219 psci_spd_pm->svc_on_finish(0);
220
Jeenu Viswambharan55e56a92017-09-22 08:32:10 +0100221 PUBLISH_EVENT(psci_cpu_on_finish);
222
Soby Mathew9d754f62015-04-08 17:42:06 +0100223 /* Populate the mpidr field within the cpu node array */
224 /* This needs to be done only once */
225 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
226
Soby Mathew991d42c2015-06-29 16:30:12 +0100227 /*
228 * Generic management: Now we just need to retrieve the
229 * information that we had stashed away during the cpu_on
230 * call to set this cpu on its way.
231 */
232 cm_prepare_el3_exit(NON_SECURE);
Soby Mathew991d42c2015-06-29 16:30:12 +0100233}