| commit | 346bfd856da0ab609b0bbf1886fb69898714e2bc | [log] [tgz] |
|---|---|---|
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | Thu Jan 05 11:01:02 2017 +0000 |
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | Thu Mar 02 11:00:20 2017 +0000 |
| tree | 8a51404d3455039208b4a73497ae13d06f60da0f | |
| parent | 0b56d6f867094a736d7a273d3d8bb402f8b0e081 [diff] |
PSCI: Optimize call paths if all participants are cache-coherent
The current PSCI implementation can apply certain optimizations upon the
assumption that all PSCI participants are cache-coherent.
- Skip performing cache maintenance during power-up.
- Skip performing cache maintenance during power-down:
At present, on the power-down path, CPU driver disables caches and
MMU, and performs cache maintenance in preparation for powering down
the CPU. This means that PSCI must perform additional cache
maintenance on the extant stack for correct functioning.
If all participating CPUs are cache-coherent, CPU driver would
neither disable MMU nor perform cache maintenance. The CPU being
powered down, therefore, remain cache-coherent throughout all PSCI
call paths. This in turn means that PSCI cache maintenance
operations are not required during power down.
- Choose spin locks instead of bakery locks:
The current PSCI implementation must synchronize both cache-coherent
and non-cache-coherent participants. Mutual exclusion primitives are
not guaranteed to function on non-coherent memory. For this reason,
the current PSCI implementation had to resort to bakery locks.
If all participants are cache-coherent, the implementation can
enable MMU and data caches early, and substitute bakery locks for
spin locks. Spin locks make use of architectural mutual exclusion
primitives, and are lighter and faster.
The optimizations are applied when HW_ASSISTED_COHERENCY build option is
enabled, as it's expected that all PSCI participants are cache-coherent
in those systems.
Change-Id: Iac51c3ed318ea7e2120f6b6a46fd2db2eae46ede
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
ARM Trusted Firmware provides a reference implementation of secure world software for ARMv8-A, including a [Secure Monitor] TEE-SMC executing at Exception Level 3 (EL3). It implements various ARM interface standards, such as the Power State Coordination Interface (PSCI), Trusted Board Boot Requirements (TBBR, ARM DEN0006C-1) and SMC Calling Convention. As far as possible the code is designed for reuse or porting to other ARMv8-A model and hardware platforms.
ARM will continue development in collaboration with interested parties to provide a full reference implementation of PSCI, TBBR and Secure Monitor code to the benefit of all developers working with ARMv8-A TrustZone technology.
The software is provided under a BSD-3-Clause license. Contributions to this project are accepted under the same license with developer sign-off as described in the Contributing Guidelines.
This project contains code from other projects as listed below. The original license text is included in those source files.
The stdlib source code is derived from FreeBSD code.
The libfdt source code is dual licensed. It is used by this project under the terms of the BSD-2-Clause license.
This release provides a suitable starting point for productization of secure world boot and runtime firmware, executing in either the AArch32 or AArch64 execution state.
Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from ARM Trusted Firmware.
Initialization of the secure world (for example, exception vectors, control registers, interrupt controller and interrupts for the platform), before transitioning into the normal world at the Exception Level and Register Width specified by the platform.
Library support for CPU specific reset and power down sequences. This includes support for errata workarounds.
Drivers for both versions 2.0 and 3.0 of the ARM Generic Interrupt Controller specifications (GICv2 and GICv3). The latter also enables GICv3 hardware systems that do not contain legacy GICv2 support.
Drivers to enable standard initialization of ARM System IP, for example Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone Controller (TZC).
SMC (Secure Monitor Call) handling, conforming to the SMC Calling Convention using an EL3 runtime services framework.
PSCI library support for the Secondary CPU Boot, CPU Hotplug, CPU Idle and System Shutdown/Reset/Suspend use-cases. This library is pre-integrated with the provided AArch64 EL3 Runtime Software, and is also suitable for integration into other EL3 Runtime Software.
A minimal AArch32 Secure Payload to demonstrate PSCI library integration on platforms with AArch32 EL3 Runtime Software.
Secure Monitor library code such as world switching, EL1 context management and interrupt routing. When using the provided AArch64 EL3 Runtime Software, this must be integrated with a Secure-EL1 Payload Dispatcher (SPD) component to customize the interaction with a Secure-EL1 Payload (SP), for example a Secure OS.
A Test Secure-EL1 Payload and Dispatcher to demonstrate AArch64 Secure Monitor functionality and Secure-EL1 interaction with PSCI.
AArch64 SPDs for the OP-TEE Secure OS and [NVidia Trusted Little Kernel] NVidia TLK.
A Trusted Board Boot implementation, conforming to all mandatory TBBR requirements. This includes image authentication using certificates, a Firmware Update (or recovery mode) boot flow, and packaging of the various firmware images into a Firmware Image Package (FIP) to be loaded from non-volatile storage. The TBBR implementation is currently only supported in the AArch64 build.
Support for alternative boot flows. Some platforms have their own boot firmware and only require the AArch64 EL3 Runtime Software provided by this project. Other platforms require minimal initialization before booting into an arbitrary EL3 payload.
For a full description of functionality and implementation details, please see the Firmware Design and supporting documentation. The Change Log provides details of changes made since the last release.
The AArch64 build of this release has been tested on variants r0, r1 and r2 of the [Juno ARM Development Platform] Juno with Linaro Release 16.06.
The AArch64 build of this release has been tested on the following ARM FVPs (64-bit host machine only, with Linaro Release 16.06):
Foundation_Platform (Version 10.1, Build 10.1.32)FVP_Base_AEMv8A-AEMv8A (Version 7.7, Build 0.8.7701)FVP_Base_Cortex-A57x4-A53x4 (Version 7.7, Build 0.8.7701)FVP_Base_Cortex-A57x1-A53x1 (Version 7.7, Build 0.8.7701)FVP_Base_Cortex-A57x2-A53x4 (Version 7.7, Build 0.8.7701)The AArch32 build of this release has been tested on the following ARM FVPs (64-bit host machine only, with Linaro Release 16.06):
FVP_Base_AEMv8A-AEMv8A (Version 7.7, Build 0.8.7701)FVP_Base_Cortex-A32x4 (Version 10.1, Build 10.1.32)The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM: see [www.arm.com/fvp] FVP.
This release also contains the following platform support:
AArch32 TBBR support and ongoing TBBR alignment.
More platform support.
Ongoing support for new architectural features, CPUs and System IP.
Ongoing PSCI alignment and feature support.
Ongoing security hardening, optimization and quality improvements.
For a full list of detailed issues in the current code, please see the Change Log and the GitHub issue tracker.
Get the Trusted Firmware source code from GitHub.
See the User Guide for instructions on how to install, build and use the Trusted Firmware with the ARM FVPs.
See the Firmware Design for information on how the ARM Trusted Firmware works.
See the Porting Guide as well for information about how to use this software on another ARMv8-A platform.
See the Contributing Guidelines for information on how to contribute to this project and the Acknowledgments file for a list of contributors to the project.
ARM welcomes any feedback on the Trusted Firmware. Please send feedback using the GitHub issue tracker.
ARM licensees may contact ARM directly via their partner managers.
Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.