PSCI: Add framework to handle composite power states

The state-id field in the power-state parameter of a CPU_SUSPEND call can be
used to describe composite power states specific to a platform. The current PSCI
implementation does not interpret the state-id field. It relies on the target
power level and the state type fields in the power-state parameter to perform
state coordination and power management operations. The framework introduced
in this patch allows the PSCI implementation to intepret generic global states
like RUN, RETENTION or OFF from the State-ID to make global state coordination
decisions and reduce the complexity of platform ports. It adds support to
involve the platform in state coordination which facilitates the use of
composite power states and improves the support for entering standby states
at multiple power domains.

The patch also includes support for extended state-id format for the power
state parameter as specified by PSCIv1.0.

The PSCI implementation now defines a generic representation of the power-state
parameter. It depends on the platform port to convert the power-state parameter
(possibly encoding a composite power state) passed in a CPU_SUSPEND call to this
representation via the `validate_power_state()` plat_psci_ops handler. It is an
array where each index corresponds to a power level. Each entry contains the
local power state the power domain at that power level could enter.

The meaning of the local power state values is platform defined, and may vary
between levels in a single platform. The PSCI implementation constrains the
values only so that it can classify the state as RUN, RETENTION or OFF as
required by the specification:
   * zero means RUN
   * all OFF state values at all levels must be higher than all RETENTION
     state values at all levels
   * the platform provides PLAT_MAX_RET_STATE and PLAT_MAX_OFF_STATE values
     to the framework

The platform also must define the macros PLAT_MAX_RET_STATE and
PLAT_MAX_OFF_STATE which lets the PSCI implementation find out which power
domains have been requested to enter a retention or power down state. The PSCI
implementation does not interpret the local power states defined by the
platform. The only constraint is that the PLAT_MAX_RET_STATE <
PLAT_MAX_OFF_STATE.

For a power domain tree, the generic implementation maintains an array of local
power states. These are the states requested for each power domain by all the
cores contained within the domain. During a request to place multiple power
domains in a low power state, the platform is passed an array of requested
power-states for each power domain through the plat_get_target_pwr_state()
API. It coordinates amongst these states to determine a target local power
state for the power domain. A default weak implementation of this API is
provided in the platform layer which returns the minimum of the requested
power-states back to the PSCI state coordination.

Finally, the plat_psci_ops power management handlers are passed the target
local power states for each affected power domain using the generic
representation described above. The platform executes operations specific to
these target states.

The platform power management handler for placing a power domain in a standby
state (plat_pm_ops_t.pwr_domain_standby()) is now only used as a fast path for
placing a core power domain into a standby or retention state should now be
used to only place the core power domain in a standby or retention state.

The extended state-id power state format can be enabled by setting the
build flag PSCI_EXTENDED_STATE_ID=1 and it is disabled by default.

Change-Id: I9d4123d97e179529802c1f589baaa4101759d80c
13 files changed
tree: 78afd367292487a476bdc65760859157eb5bbb13
  1. bl1/
  2. bl2/
  3. bl31/
  4. bl32/
  5. common/
  6. docs/
  7. drivers/
  8. fdts/
  9. include/
  10. lib/
  11. plat/
  12. services/
  13. tools/
  14. .gitignore
  15. acknowledgements.md
  16. contributing.md
  17. license.md
  18. Makefile
  19. readme.md
readme.md

ARM Trusted Firmware - version 1.1

ARM Trusted Firmware provides a reference implementation of secure world software for ARMv8-A, including Exception Level 3 (EL3) software. This release provides complete support for version 0.2 of the PSCI specification, initial support for the new version 1.0 of that specification, and prototype support for the Trusted Board Boot Requirements specification.

The intent is to provide a reference implementation of various ARM interface standards, such as the Power State Coordination Interface (PSCI), Trusted Board Boot Requirements (TBBR) and [Secure Monitor] TEE-SMC code. As far as possible the code is designed for reuse or porting to other ARMv8-A model and hardware platforms.

ARM will continue development in collaboration with interested parties to provide a full reference implementation of PSCI, TBBR and Secure Monitor code to the benefit of all developers working with ARMv8-A TrustZone technology.

License

The software is provided under a BSD 3-Clause license. Certain source files are derived from FreeBSD code: the original license is included in these source files.

This Release

This release is a limited functionality implementation of the Trusted Firmware. It provides a suitable starting point for productization. Future versions will contain new features, optimizations and quality improvements.

Functionality

  • Prototype implementation of a subset of the Trusted Board Boot Requirements Platform Design Document (PDD). This includes packaging the various firmware images into a Firmware Image Package (FIP) to be loaded from non-volatile storage, and a prototype of authenticated boot using key certificates stored in the FIP.

  • Initializes the secure world (for example, exception vectors, control registers, GIC and interrupts for the platform), before transitioning into the normal world.

  • Supports both GICv2 and GICv3 initialization for use by normal world software.

  • Starts the normal world at the Exception Level and Register Width specified by the platform port. Typically this is AArch64 EL2 if available.

  • Handles SMCs (Secure Monitor Calls) conforming to the [SMC Calling Convention PDD] SMCCC using an EL3 runtime services framework.

  • Handles SMCs relating to the [Power State Coordination Interface PDD] PSCI for the Secondary CPU Boot, CPU Hotplug, CPU Idle and System Shutdown/Reset use-cases.

  • A Test Secure-EL1 Payload and Dispatcher to demonstrate Secure Monitor functionality such as world switching, EL1 context management and interrupt routing. This also demonstrates Secure-EL1 interaction with PSCI. Some of this functionality is provided in library form for re-use by other Secure-EL1 Payload Dispatchers.

  • Support for alternative Trusted Boot Firmware. Some platforms have their own Trusted Boot implementation and only require the Secure Monitor functionality provided by ARM Trusted Firmware.

  • Isolation of memory accessible by the secure world from the normal world through programming of a TrustZone controller.

  • Support for CPU specific reset sequences, power down sequences and register dumping during crash reporting. The CPU specific reset sequences include support for errata workarounds.

For a full description of functionality and implementation details, please see the Firmware Design and supporting documentation. The Change Log provides details of changes made since the last release.

Platforms

This release of the Trusted Firmware has been tested on Revision B of the [Juno ARM Development Platform] Juno with Version r0p0-00rel7 of the [ARM SCP Firmware] SCP download.

The Trusted Firmware has also been tested on the 64-bit Linux versions of the following ARM FVPs:

  • Foundation_Platform (Version 9.1, Build 9.1.33)
  • FVP_Base_AEMv8A-AEMv8A (Version 6.2, Build 0.8.6202)
  • FVP_Base_Cortex-A57x4-A53x4 (Version 6.2, Build 0.8.6202)
  • FVP_Base_Cortex-A57x1-A53x1 (Version 6.2, Build 0.8.6202)
  • FVP_Base_Cortex-A57x2-A53x4 (Version 6.2, Build 0.8.6202)

The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM: see [www.arm.com/fvp] FVP.

Still to Come

  • Complete and more flexible Trusted Board Boot implementation.

  • Complete implementation of the PSCI v1.0 specification.

  • Support for alternative types of Secure-EL1 Payloads.

  • Extending the GICv3 support to the secure world.

  • Support for new System IP devices.

For a full list of detailed issues in the current code, please see the Change Log and the GitHub issue tracker.

Getting Started

Get the Trusted Firmware source code from GitHub.

See the User Guide for instructions on how to install, build and use the Trusted Firmware with the ARM FVPs.

See the Firmware Design for information on how the ARM Trusted Firmware works.

See the Porting Guide as well for information about how to use this software on another ARMv8-A platform.

See the Contributing Guidelines for information on how to contribute to this project and the Acknowledgments file for a list of contributors to the project.

Feedback and support

ARM welcomes any feedback on the Trusted Firmware. Please send feedback using the GitHub issue tracker.

ARM licensees may contact ARM directly via their partner managers.


Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.