Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <bl31.h> |
| 36 | #include <debug.h> |
| 37 | #include <context_mgmt.h> |
| 38 | #include <platform.h> |
| 39 | #include <runtime_svc.h> |
| 40 | #include <stddef.h> |
| 41 | #include "psci_private.h" |
| 42 | |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 43 | /******************************************************************************* |
| 44 | * This function checks whether a cpu which has been requested to be turned on |
| 45 | * is OFF to begin with. |
| 46 | ******************************************************************************/ |
| 47 | static int cpu_on_validate_state(unsigned int psci_state) |
| 48 | { |
| 49 | if (psci_state == PSCI_STATE_ON || psci_state == PSCI_STATE_SUSPEND) |
| 50 | return PSCI_E_ALREADY_ON; |
| 51 | |
| 52 | if (psci_state == PSCI_STATE_ON_PENDING) |
| 53 | return PSCI_E_ON_PENDING; |
| 54 | |
| 55 | assert(psci_state == PSCI_STATE_OFF); |
| 56 | return PSCI_E_SUCCESS; |
| 57 | } |
| 58 | |
| 59 | /******************************************************************************* |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 60 | * Generic handler which is called to physically power on a cpu identified by |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 61 | * its mpidr. It performs the generic, architectural, platform setup and state |
| 62 | * management to power on the target cpu e.g. it will ensure that |
| 63 | * enough information is stashed for it to resume execution in the non-secure |
| 64 | * security state. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 65 | * |
| 66 | * The state of all the relevant affinity levels is changed after calling the |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 67 | * platform handler as it can return error. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 68 | ******************************************************************************/ |
| 69 | int psci_afflvl_on(unsigned long target_cpu, |
| 70 | entry_point_info_t *ep, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 71 | int end_afflvl) |
| 72 | { |
| 73 | int rc; |
| 74 | mpidr_aff_map_nodes_t target_cpu_nodes; |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 75 | unsigned long psci_entrypoint; |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * This function must only be called on platforms where the |
| 79 | * CPU_ON platform hooks have been implemented. |
| 80 | */ |
| 81 | assert(psci_plat_pm_ops->affinst_on && |
| 82 | psci_plat_pm_ops->affinst_on_finish); |
| 83 | |
| 84 | /* |
| 85 | * Collect the pointers to the nodes in the topology tree for |
| 86 | * each affinity instance in the mpidr. If this function does |
| 87 | * not return successfully then either the mpidr or the affinity |
| 88 | * levels are incorrect. |
| 89 | */ |
| 90 | rc = psci_get_aff_map_nodes(target_cpu, |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 91 | MPIDR_AFFLVL0, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 92 | end_afflvl, |
| 93 | target_cpu_nodes); |
| 94 | assert(rc == PSCI_E_SUCCESS); |
| 95 | |
| 96 | /* |
| 97 | * This function acquires the lock corresponding to each affinity |
| 98 | * level so that by the time all locks are taken, the system topology |
| 99 | * is snapshot and state management can be done safely. |
| 100 | */ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 101 | psci_acquire_afflvl_locks(MPIDR_AFFLVL0, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 102 | end_afflvl, |
| 103 | target_cpu_nodes); |
| 104 | |
| 105 | /* |
| 106 | * Generic management: Ensure that the cpu is off to be |
| 107 | * turned on. |
| 108 | */ |
| 109 | rc = cpu_on_validate_state(psci_get_state( |
| 110 | target_cpu_nodes[MPIDR_AFFLVL0])); |
| 111 | if (rc != PSCI_E_SUCCESS) |
| 112 | goto exit; |
| 113 | |
| 114 | /* |
| 115 | * Call the cpu on handler registered by the Secure Payload Dispatcher |
| 116 | * to let it do any bookeeping. If the handler encounters an error, it's |
| 117 | * expected to assert within |
| 118 | */ |
| 119 | if (psci_spd_pm && psci_spd_pm->svc_on) |
| 120 | psci_spd_pm->svc_on(target_cpu); |
| 121 | |
| 122 | /* |
| 123 | * This function updates the state of each affinity instance |
| 124 | * corresponding to the mpidr in the range of affinity levels |
| 125 | * specified. |
| 126 | */ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 127 | psci_do_afflvl_state_mgmt(MPIDR_AFFLVL0, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 128 | end_afflvl, |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 129 | target_cpu_nodes, |
| 130 | PSCI_STATE_ON_PENDING); |
| 131 | |
| 132 | /* |
| 133 | * Perform generic, architecture and platform specific handling. |
| 134 | */ |
| 135 | /* Set the secure world (EL3) re-entry point after BL1 */ |
| 136 | psci_entrypoint = (unsigned long) psci_aff_on_finish_entry; |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 137 | |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 138 | /* |
| 139 | * Plat. management: Give the platform the current state |
| 140 | * of the target cpu to allow it to perform the necessary |
| 141 | * steps to power on. |
| 142 | */ |
| 143 | rc = psci_plat_pm_ops->affinst_on(target_cpu, |
| 144 | psci_entrypoint, |
| 145 | MPIDR_AFFLVL0); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 146 | assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); |
| 147 | |
| 148 | if (rc == PSCI_E_SUCCESS) |
| 149 | /* Store the re-entry information for the non-secure world. */ |
| 150 | cm_init_context(target_cpu, ep); |
| 151 | else |
| 152 | /* Restore the state on error. */ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 153 | psci_do_afflvl_state_mgmt(MPIDR_AFFLVL0, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 154 | end_afflvl, |
| 155 | target_cpu_nodes, |
| 156 | PSCI_STATE_OFF); |
| 157 | exit: |
| 158 | /* |
| 159 | * This loop releases the lock corresponding to each affinity level |
| 160 | * in the reverse order to which they were acquired. |
| 161 | */ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 162 | psci_release_afflvl_locks(MPIDR_AFFLVL0, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 163 | end_afflvl, |
| 164 | target_cpu_nodes); |
| 165 | |
| 166 | return rc; |
| 167 | } |
| 168 | |
| 169 | /******************************************************************************* |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 170 | * The following function finish an earlier affinity power on request. They |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 171 | * are called by the common finisher routine in psci_common.c. |
| 172 | ******************************************************************************/ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 173 | void psci_afflvl_on_finisher(aff_map_node_t *node[], int afflvl) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 174 | { |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 175 | assert(node[afflvl]->level == afflvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 176 | |
| 177 | /* Ensure we have been explicitly woken up by another cpu */ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 178 | assert(psci_get_state(node[MPIDR_AFFLVL0]) == PSCI_STATE_ON_PENDING); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 179 | |
| 180 | /* |
| 181 | * Plat. management: Perform the platform specific actions |
| 182 | * for this cpu e.g. enabling the gic or zeroing the mailbox |
| 183 | * register. The actual state of this cpu has already been |
| 184 | * changed. |
| 185 | */ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame^] | 186 | psci_plat_pm_ops->affinst_on_finish(afflvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 187 | |
| 188 | /* |
| 189 | * Arch. management: Enable data cache and manage stack memory |
| 190 | */ |
| 191 | psci_do_pwrup_cache_maintenance(); |
| 192 | |
| 193 | /* |
| 194 | * All the platform specific actions for turning this cpu |
| 195 | * on have completed. Perform enough arch.initialization |
| 196 | * to run in the non-secure address space. |
| 197 | */ |
| 198 | bl31_arch_setup(); |
| 199 | |
| 200 | /* |
| 201 | * Call the cpu on finish handler registered by the Secure Payload |
| 202 | * Dispatcher to let it do any bookeeping. If the handler encounters an |
| 203 | * error, it's expected to assert within |
| 204 | */ |
| 205 | if (psci_spd_pm && psci_spd_pm->svc_on_finish) |
| 206 | psci_spd_pm->svc_on_finish(0); |
| 207 | |
| 208 | /* |
| 209 | * Generic management: Now we just need to retrieve the |
| 210 | * information that we had stashed away during the cpu_on |
| 211 | * call to set this cpu on its way. |
| 212 | */ |
| 213 | cm_prepare_el3_exit(NON_SECURE); |
| 214 | |
| 215 | /* Clean caches before re-entering normal world */ |
| 216 | dcsw_op_louis(DCCSW); |
| 217 | } |
| 218 | |