blob: ea3f9548617a5b44a71a3f13bf85dfc7661fa591 [file] [log] [blame]
Ryan Harkin25cff832014-01-13 12:37:03 +00001#
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
Ryan Harkin25cff832014-01-13 12:37:03 +00003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Ryan Harkin25cff832014-01-13 12:37:03 +00005#
6
Chris Kaye9272152021-09-28 15:52:14 +01007include common/fdt_wrappers.mk
8
Soby Mathewb6f3b1f2016-04-07 17:40:04 +01009# Use the GICv3 driver on the FVP by default
10FVP_USE_GIC_DRIVER := FVP_GICV3
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000011
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000012# Default cluster count for FVP
13FVP_CLUSTER_COUNT := 2
14
Jeenu Viswambharan75421132018-01-31 14:52:08 +000015# Default number of CPUs per cluster on FVP
16FVP_MAX_CPUS_PER_CLUSTER := 4
17
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000018# Default number of threads per CPU on FVP
19FVP_MAX_PE_PER_CPU := 1
20
Manish V Badarkheb24c6372021-01-24 03:26:50 +000021# Disable redistributor frame of inactive/fused CPU cores by marking it as read
22# only; enable redistributor frames of all CPU cores by default.
23FVP_GICR_REGION_PROTECTION := 0
24
Soby Mathew5f6412a2018-02-08 11:39:38 +000025FVP_DT_PREFIX := fvp-base-gicv3-psci
26
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010027# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's
28# progbits limit. We need a way to build all useful configurations while waiting
29# on the fvp to increase its SRAM size. The problem is twofild:
30# 1. the cleanup that introduced these enables cleaned up tf-a a little too
31# well and things that previously (incorrectly) were enabled, no longer are.
32# A bunch of CI configs build subtly incorrectly and this combo makes it
33# necessary to forcefully and unconditionally enable them here.
34# 2. the progbits limit is exceeded only when the tsp is involved. However,
35# there are tsp CI configs that run on very high architecture revisions so
36# disabling everything isn't an option.
37# The fix is to enable everything, as before. When the tsp is included, though,
38# we need to slim the size down. In that case, disable all optional features,
39# that will not be present in CI when the tsp is.
Boyan Karatotev7b7bc132023-04-04 14:48:04 +010040# Similarly, DRTM support is only tested on v8.0 models. Disable everything just
41# for it.
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010042# TODO: make all of this unconditional (or only base the condition on
43# ARM_ARCH_* when the makefile supports it).
Boyan Karatotev7b7bc132023-04-04 14:48:04 +010044ifneq (${DRTM_SUPPORT}, 1)
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010045ifneq (${SPD}, tspd)
46 ENABLE_FEAT_AMU := 2
47 ENABLE_FEAT_AMUv1p1 := 2
48 ENABLE_FEAT_HCX := 2
49 ENABLE_MPAM_FOR_LOWER_ELS := 2
50 ENABLE_FEAT_RNG := 2
51 ENABLE_FEAT_TWED := 2
Mark Brown326f2952023-03-14 21:33:04 +000052 ENABLE_FEAT_GCS := 2
Jayanth Dodderi Chidanandc8395cf2023-04-28 15:14:27 +010053ifeq (${ARCH}, aarch64)
54ifneq (${SPD}, spmd)
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010055ifeq (${SPM_MM}, 0)
56ifeq (${ENABLE_RME}, 0)
57ifeq (${CTX_INCLUDE_FPREGS}, 0)
58 ENABLE_SME_FOR_NS := 2
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +000059 ENABLE_SME2_FOR_NS := 2
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010060endif
61endif
62endif
63endif
64endif
Jayanth Dodderi Chidanandc8395cf2023-04-28 15:14:27 +010065endif
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010066
67# enable unconditionally for all builds
68ifeq (${ARCH}, aarch64)
69ifeq (${ENABLE_RME},0)
70 ENABLE_BRBE_FOR_NS := 2
71endif
72endif
73ENABLE_TRBE_FOR_NS := 2
74ENABLE_SYS_REG_TRACE_FOR_NS := 2
75ENABLE_FEAT_CSV2_2 := 2
Andre Przywara1f55c412023-01-26 16:47:52 +000076ENABLE_FEAT_DIT := 2
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010077ENABLE_FEAT_PAN := 2
78ENABLE_FEAT_VHE := 2
79CTX_INCLUDE_NEVE_REGS := 2
80ENABLE_FEAT_SEL2 := 2
81ENABLE_TRF_FOR_NS := 2
82ENABLE_FEAT_ECV := 2
83ENABLE_FEAT_FGT := 2
84ENABLE_FEAT_TCR2 := 2
Mark Brown293a6612023-03-14 20:48:43 +000085ENABLE_FEAT_S2PIE := 2
86ENABLE_FEAT_S1PIE := 2
87ENABLE_FEAT_S2POE := 2
88ENABLE_FEAT_S1POE := 2
Boyan Karatotev7b7bc132023-04-04 14:48:04 +010089endif
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010090
Achin Gupta1fa7eb62015-11-03 14:18:34 +000091# The FVP platform depends on this macro to build with correct GIC driver.
92$(eval $(call add_define,FVP_USE_GIC_DRIVER))
93
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000094# Pass FVP_CLUSTER_COUNT to the build system.
Soby Mathew47e43f22016-02-01 14:04:34 +000095$(eval $(call add_define,FVP_CLUSTER_COUNT))
Soby Mathew7356b1e2016-03-24 10:12:42 +000096
Jeenu Viswambharan75421132018-01-31 14:52:08 +000097# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system.
98$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER))
99
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000100# Pass FVP_MAX_PE_PER_CPU to the build system.
101$(eval $(call add_define,FVP_MAX_PE_PER_CPU))
102
Manish V Badarkheb24c6372021-01-24 03:26:50 +0000103# Pass FVP_GICR_REGION_PROTECTION to the build system.
104$(eval $(call add_define,FVP_GICR_REGION_PROTECTION))
105
Soby Mathew7356b1e2016-03-24 10:12:42 +0000106# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2,
107# choose the CCI driver , else the CCN driver
108ifeq ($(FVP_CLUSTER_COUNT), 0)
109$(error "Incorrect cluster count specified for FVP port")
110else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2))
111FVP_INTERCONNECT_DRIVER := FVP_CCI
112else
113FVP_INTERCONNECT_DRIVER := FVP_CCN
Soby Mathew47e43f22016-02-01 14:04:34 +0000114endif
115
Soby Mathew7356b1e2016-03-24 10:12:42 +0000116$(eval $(call add_define,FVP_INTERCONNECT_DRIVER))
117
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000118# Choose the GIC sources depending upon the how the FVP will be invoked
Andre Przywarae1cc1302020-03-25 15:50:38 +0000119ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000120
Andre Przywarae1cc1302020-03-25 15:50:38 +0000121# The GIC model (GIC-600 or GIC-500) will be detected at runtime
122GICV3_SUPPORT_GIC600 := 1
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000123GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
124
125# Include GICv3 driver files
126include drivers/arm/gic/v3/gicv3.mk
127
128FVP_GIC_SOURCES := ${GICV3_SOURCES} \
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000129 plat/common/plat_gicv3.c \
130 plat/arm/common/arm_gicv3.c
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000131
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600132 ifeq ($(filter 1,${RESET_TO_BL2} \
133 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
laurenw-armdc5e9a22020-05-12 10:58:11 -0500134 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
135 endif
136
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000137else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +0100138
139# No GICv4 extension
140GIC_ENABLE_V4_EXTN := 0
141$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
142
Alexei Fedorovcaa18022020-07-14 10:47:25 +0100143# Include GICv2 driver files
144include drivers/arm/gic/v2/gicv2.mk
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +0100145
Alexei Fedorovcaa18022020-07-14 10:47:25 +0100146FVP_GIC_SOURCES := ${GICV2_SOURCES} \
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000147 plat/common/plat_gicv2.c \
148 plat/arm/common/arm_gicv2.c
Soby Mathew5f6412a2018-02-08 11:39:38 +0000149
150FVP_DT_PREFIX := fvp-base-gicv2-psci
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000151else
152$(error "Incorrect GIC driver chosen on FVP port")
153endif
154
Soby Mathew7356b1e2016-03-24 10:12:42 +0000155ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI)
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100156FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
Soby Mathew7356b1e2016-03-24 10:12:42 +0000157else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN)
158FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
159 plat/arm/common/arm_ccn.c
160else
161$(error "Incorrect CCN driver chosen on FVP port")
162endif
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000163
Soby Mathew9c708b52016-02-26 14:23:19 +0000164FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000165 plat/arm/board/fvp/fvp_security.c \
166 plat/arm/common/arm_tzc400.c
167
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000168
Manish V Badarkhe7ac59582023-03-24 08:22:33 +0000169PLAT_INCLUDES := -Iplat/arm/board/fvp/include \
170 -Iinclude/lib/psa
Sandrine Bailleuxe701e302014-05-20 17:28:25 +0100171
Ryan Harkin25cff832014-01-13 12:37:03 +0000172
Soby Mathewcc037c12016-04-08 16:42:58 +0100173PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
Ryan Harkin25cff832014-01-13 12:37:03 +0000174
Soby Mathew0d268dc2016-07-11 14:13:56 +0100175FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
176
177ifeq (${ARCH}, aarch64)
John Tsichritzisfe6df392019-03-19 17:20:52 +0000178
John Tsichritzis7557c662019-06-03 13:54:30 +0100179# select a different set of CPU files, depending on whether we compile for
180# hardware assisted coherency cores or not
John Tsichritzisfe6df392019-03-19 17:20:52 +0000181ifeq (${HW_ASSISTED_COHERENCY}, 0)
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100182# Cores used without DSU
John Tsichritzisfe6df392019-03-19 17:20:52 +0000183 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
Soby Mathewc704cbc2014-08-14 11:33:56 +0100184 lib/cpus/aarch64/cortex_a53.S \
185 lib/cpus/aarch64/cortex_a57.S \
Yatharth Kochar63af6872016-02-09 12:00:03 +0000186 lib/cpus/aarch64/cortex_a72.S \
John Tsichritzisfe6df392019-03-19 17:20:52 +0000187 lib/cpus/aarch64/cortex_a73.S
188else
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100189# Cores used with DSU only
John Tsichritzis7557c662019-06-03 13:54:30 +0100190 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100191 # AArch64-only cores
Boyan Karatotevf154cbd2023-04-06 10:31:09 +0100192 # TODO: add all cores to the appropriate lists
193 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \
194 lib/cpus/aarch64/cortex_a65ae.S \
195 lib/cpus/aarch64/cortex_a76.S \
John Tsichritzis7557c662019-06-03 13:54:30 +0100196 lib/cpus/aarch64/cortex_a76ae.S \
Balint Dobszaycc942642019-07-03 13:02:56 +0200197 lib/cpus/aarch64/cortex_a77.S \
Jimmy Brisson7ec175e2020-06-01 16:49:34 -0500198 lib/cpus/aarch64/cortex_a78.S \
Boyan Karatotevf154cbd2023-04-06 10:31:09 +0100199 lib/cpus/aarch64/cortex_a78c.S \
200 lib/cpus/aarch64/cortex_a710.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100201 lib/cpus/aarch64/neoverse_n_common.S \
John Tsichritzis7557c662019-06-03 13:54:30 +0100202 lib/cpus/aarch64/neoverse_n1.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100203 lib/cpus/aarch64/neoverse_n2.S \
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500204 lib/cpus/aarch64/neoverse_v1.S \
Boyan Karatotevf154cbd2023-04-06 10:31:09 +0100205 lib/cpus/aarch64/neoverse_e1.S \
206 lib/cpus/aarch64/cortex_x2.S
John Tsichritzis7557c662019-06-03 13:54:30 +0100207 endif
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100208 # AArch64/AArch32 cores
209 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
210 lib/cpus/aarch64/cortex_a75.S
John Tsichritzisfe6df392019-03-19 17:20:52 +0000211endif
John Tsichritzis6deaf9c2018-10-08 17:09:43 +0100212
Yatharth Kochara4c219a2016-07-12 15:47:03 +0100213else
Boyan Karatotevf3581342023-01-27 10:58:42 +0000214FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
215 lib/cpus/aarch32/cortex_a57.S
Soby Mathew0d268dc2016-07-11 14:13:56 +0100216endif
Sandrine Bailleuxdd505792016-01-13 09:04:26 +0000217
Alexei Fedorov896799a2019-05-09 12:14:40 +0100218BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
219 drivers/arm/sp805/sp805.c \
Alexei Fedorov7131d832019-08-16 14:15:59 +0100220 drivers/delay_timer/delay_timer.c \
Aditya Angadi20b48412019-04-16 11:29:14 +0530221 drivers/io/io_semihosting.c \
Dan Handley2b6b5742015-03-19 19:17:53 +0000222 lib/semihosting/semihosting.c \
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100223 lib/semihosting/${ARCH}/semihosting_call.S \
224 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
Dan Handleyd617f662015-04-27 19:17:18 +0100225 plat/arm/board/fvp/fvp_bl1_setup.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100226 plat/arm/board/fvp/fvp_err.c \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000227 plat/arm/board/fvp/fvp_io_storage.c \
228 ${FVP_CPU_LIBS} \
229 ${FVP_INTERCONNECT_SOURCES}
230
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500231ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100232BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
233else
234BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c
235endif
236
Ryan Harkin25cff832014-01-13 12:37:03 +0000237
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100238BL2_SOURCES += drivers/arm/sp805/sp805.c \
239 drivers/io/io_semihosting.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100240 lib/utils/mem_region.c \
Dan Handley2b6b5742015-03-19 19:17:53 +0000241 lib/semihosting/semihosting.c \
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100242 lib/semihosting/${ARCH}/semihosting_call.S \
Dan Handleyd617f662015-04-27 19:17:18 +0100243 plat/arm/board/fvp/fvp_bl2_setup.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100244 plat/arm/board/fvp/fvp_err.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100245 plat/arm/board/fvp/fvp_io_storage.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100246 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000247 ${FVP_SECURITY_SOURCES}
Ryan Harkin25cff832014-01-13 12:37:03 +0000248
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100249
Manish V Badarkhe09a192c2020-08-23 09:58:44 +0100250ifeq (${COT_DESC_IN_DTB},1)
251BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c
252endif
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100253
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500254ifeq (${ENABLE_RME},1)
255BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S
Manish V Badarkhe37f9ac22023-03-12 21:34:44 +0000256
Soby Mathewf05d93a2022-03-22 16:21:19 +0000257BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \
258 plat/arm/board/fvp/fvp_realm_attest_key.c
Manish V Badarkhe37f9ac22023-03-12 21:34:44 +0000259
260# FVP platform does not support RSS, but it can leverage RSS APIs to
261# provide hardcoded token/key on request.
262BL31_SOURCES += lib/psa/delegated_attestation.c
263
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500264endif
265
Andre Przywarabdc76f12022-11-21 17:07:25 +0000266ifeq (${ENABLE_FEAT_RNG_TRAP},1)
267BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c
268endif
269
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600270ifeq (${RESET_TO_BL2},1)
Roberto Vargas52207802017-11-17 13:22:18 +0000271BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
272 plat/arm/board/fvp/fvp_bl2_el3_setup.c \
273 ${FVP_CPU_LIBS} \
274 ${FVP_INTERCONNECT_SOURCES}
275endif
276
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500277ifeq (${USE_SP804_TIMER},1)
Antonio Nino Diaz664adb62016-05-17 09:48:10 +0100278BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
Antonio Nino Diaz664adb62016-05-17 09:48:10 +0100279endif
280
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100281BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000282 ${FVP_SECURITY_SOURCES}
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100283
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500284ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100285BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
286endif
287
Antonio Nino Diazf13d09a2019-01-23 21:50:09 +0000288BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
289 drivers/arm/smmu/smmu_v3.c \
Alexei Fedorov7131d832019-08-16 14:15:59 +0100290 drivers/delay_timer/delay_timer.c \
Antonio Nino Diazd7da2f82018-10-10 11:14:44 +0100291 drivers/cfi/v2m/v2m_flash.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100292 lib/utils/mem_region.c \
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100293 plat/arm/board/fvp/fvp_bl31_setup.c \
Madhukar Pappireddyd0cf0a92020-04-16 17:54:25 -0500294 plat/arm/board/fvp/fvp_console.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100295 plat/arm/board/fvp/fvp_pm.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100296 plat/arm/board/fvp/fvp_topology.c \
297 plat/arm/board/fvp/aarch64/fvp_helpers.S \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100298 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000299 ${FVP_CPU_LIBS} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000300 ${FVP_GIC_SOURCES} \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000301 ${FVP_INTERCONNECT_SOURCES} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000302 ${FVP_SECURITY_SOURCES}
Juan Castillo5e29c752015-01-07 10:39:25 +0000303
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600304# Support for fconf in BL31
305# Added separately from the above list for better readability
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600306ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
Chris Kaye9272152021-09-28 15:52:14 +0100307BL31_SOURCES += lib/fconf/fconf.c \
Manish V Badarkhe8717e032020-05-30 17:40:44 +0100308 lib/fconf/fconf_dyn_cfg_getter.c \
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600309 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500310
Chris Kaye9272152021-09-28 15:52:14 +0100311BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
312
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500313ifeq (${SEC_INT_DESC_IN_FCONF},1)
314BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c
315endif
316
Madhukar Pappireddyaa1121f2020-03-13 13:00:17 -0500317endif
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600318
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500319ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100320BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
321else
322BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c
323endif
324
Soby Mathewa684e582018-02-27 11:17:14 +0000325# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
326ifdef UNIX_MK
Soby Mathew5f6412a2018-02-08 11:39:38 +0000327FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts
Soby Mathewb6814842018-04-04 09:40:32 +0100328FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000329 ${PLAT}_fw_config.dts \
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100330 ${PLAT}_tb_fw_config.dts \
Soby Mathewb6814842018-04-04 09:40:32 +0100331 ${PLAT}_soc_fw_config.dts \
332 ${PLAT}_nt_fw_config.dts \
333 )
334
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100335FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
336FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Soby Mathewb6814842018-04-04 09:40:32 +0100337FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb
338FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
339
340ifeq (${SPD},tspd)
341FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts
342FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb
343
344# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100345$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100346endif
Soby Mathew5f6412a2018-02-08 11:39:38 +0000347
Achin Guptada6ef0e2019-10-11 14:54:48 +0100348ifeq (${SPD},spmd)
Olivier Deprezbcaa0682020-04-01 21:28:26 +0200349
350ifeq ($(ARM_SPMC_MANIFEST_DTS),)
351ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts
352endif
353
354FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
355FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
Achin Guptada6ef0e2019-10-11 14:54:48 +0100356
357# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100358$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Achin Guptada6ef0e2019-10-11 14:54:48 +0100359endif
360
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100361# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100362$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG}))
Soby Mathew5f6412a2018-02-08 11:39:38 +0000363# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100364$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100365# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100366$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100367# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100368$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG}))
Soby Mathew5f6412a2018-02-08 11:39:38 +0000369
370FDT_SOURCES += ${FVP_HW_CONFIG_DTS}
371$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
372
373# Add the HW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100374$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
Soby Mathewa684e582018-02-27 11:17:14 +0000375endif
Soby Mathew5f6412a2018-02-08 11:39:38 +0000376
Dimitris Papastamos756b8dc2018-05-31 14:10:06 +0100377# Enable dynamic mitigation support by default
378DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
379
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000380ifneq (${ENABLE_FEAT_AMU},0)
John Tsichritzisfe6df392019-03-19 17:20:52 +0000381BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
Dimitris Papastamos0b00f8a2018-02-14 10:00:06 +0000382 lib/cpus/aarch64/cpuamu_helpers.S
John Tsichritzisfe6df392019-03-19 17:20:52 +0000383
384ifeq (${HW_ASSISTED_COHERENCY}, 1)
385BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
386 lib/cpus/aarch64/neoverse_n1_pubsub.c
387endif
Dimitris Papastamosd7e2e9e2017-12-11 11:45:35 +0000388endif
389
Jeenu Viswambharana490fe02018-06-08 08:44:36 +0100390ifeq (${RAS_EXTENSION},1)
391BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
392endif
393
Douglas Raillard306593d2017-02-24 18:14:15 +0000394ifneq (${ENABLE_STACK_PROTECTOR},0)
395PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
396endif
397
dp-armcdd03cb2017-02-15 11:07:55 +0000398ifeq (${ARCH},aarch32)
399 NEED_BL32 := yes
400endif
401
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000402# Enable the dynamic translation tables library.
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600403ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),)
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000404 ifeq (${ARCH},aarch32)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900405 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000406 else # AArch64
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900407 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Antonio Nino Diaz60ef6752019-02-12 13:32:03 +0000408 endif
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000409endif
410
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000411ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
412 ifeq (${ARCH},aarch32)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900413 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000414 else # AArch64
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900415 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000416 ifeq (${SPD},tspd)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900417 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000418 endif
419 endif
420endif
421
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100422ifeq (${USE_DEBUGFS},1)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900423 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100424endif
425
Soby Mathew3b5156e2017-10-05 12:27:33 +0100426# Add support for platform supplied linker script for BL31 build
427$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
428
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600429ifneq (${RESET_TO_BL2}, 0)
Roberto Vargas9f412482018-01-16 10:35:23 +0000430 override BL1_SOURCES =
431endif
432
Manish V Badarkhe37f9ac22023-03-12 21:34:44 +0000433# RSS is not supported on FVP right now. Thus, we use the mocked version
434# of the provided PSA APIs. They return with success and hard-coded token/key.
435PLAT_RSS_NOT_SUPPORTED := 1
436
Tamas Banb0f83252022-02-11 09:49:36 +0100437# Include Measured Boot makefile before any Crypto library makefile.
438# Crypto library makefile may need default definitions of Measured Boot build
439# flags present in Measured Boot makefile.
440ifeq (${MEASURED_BOOT},1)
441 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk
442 $(info Including ${RSS_MEASURED_BOOT_MK})
443 include ${RSS_MEASURED_BOOT_MK}
444
laurenw-arm7834aa02022-05-31 16:39:09 -0500445 ifneq (${MBOOT_RSS_HASH_ALG}, sha256)
446 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512))
447 endif
448
Tamas Banb0f83252022-02-11 09:49:36 +0100449 BL1_SOURCES += ${MEASURED_BOOT_SOURCES}
450 BL2_SOURCES += ${MEASURED_BOOT_SOURCES}
451endif
452
Juan Castillo31a68f02015-04-14 12:49:03 +0100453include plat/arm/board/common/board_common.mk
Dan Handley2b6b5742015-03-19 19:17:53 +0000454include plat/arm/common/arm_common.mk
Soby Mathew45e39e22018-03-26 15:16:46 +0100455
Alexei Fedorov61369a22020-07-13 14:59:02 +0100456ifeq (${MEASURED_BOOT},1)
Manish V Badarkhea74d9632021-09-14 23:12:42 +0100457BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \
Tamas Banb0f83252022-02-11 09:49:36 +0100458 plat/arm/board/fvp/fvp_bl1_measured_boot.c \
459 lib/psa/measured_boot.c
460
Manish V Badarkhea74d9632021-09-14 23:12:42 +0100461BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \
Tamas Banb0f83252022-02-11 09:49:36 +0100462 plat/arm/board/fvp/fvp_bl2_measured_boot.c \
463 lib/psa/measured_boot.c
464
Sandrine Bailleuxe9e37cb2022-08-31 14:05:38 +0200465# Even though RSS is not supported on FVP (see above), we support overriding
466# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building
467# the code to detect any build regressions. The resulting firmware will not be
468# functional.
469ifneq (${PLAT_RSS_NOT_SUPPORTED},1)
470 $(warning "RSS is not supported on FVP. The firmware will not be functional.")
471 include drivers/arm/rss/rss_comms.mk
472 BL1_SOURCES += ${RSS_COMMS_SOURCES}
473 BL2_SOURCES += ${RSS_COMMS_SOURCES}
Manish V Badarkhe37f9ac22023-03-12 21:34:44 +0000474 BL31_SOURCES += ${RSS_COMMS_SOURCES}
Sandrine Bailleuxe9e37cb2022-08-31 14:05:38 +0200475
Tamas Ban9cc87142022-10-05 11:56:04 +0200476 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0
477 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0
Sandrine Bailleuxb204fe92022-10-12 14:46:56 +0200478 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0
Sandrine Bailleuxe9e37cb2022-08-31 14:05:38 +0200479endif
480
Alexei Fedorov61369a22020-07-13 14:59:02 +0100481endif
482
Lucian Paul-Trifu5ee4f4e2022-06-22 18:45:30 +0100483ifeq (${DRTM_SUPPORT}, 1)
Manish V Badarkhefcfe4312022-07-12 21:48:04 +0100484BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \
485 plat/arm/board/fvp/fvp_drtm_dma_prot.c \
486 plat/arm/board/fvp/fvp_drtm_err.c \
johpow01baa3e6c2022-03-11 17:50:58 -0600487 plat/arm/board/fvp/fvp_drtm_measurement.c \
488 plat/arm/board/fvp/fvp_drtm_stub.c \
Manish V Badarkhefcfe4312022-07-12 21:48:04 +0100489 plat/arm/common/arm_dyn_cfg.c \
490 plat/arm/board/fvp/fvp_err.c
Lucian Paul-Trifu5ee4f4e2022-06-22 18:45:30 +0100491endif
492
Manish V Badarkheeba13bd2022-01-08 23:08:02 +0000493ifeq (${TRUSTED_BOARD_BOOT}, 1)
494BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
495BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
496
Soby Mathew45e39e22018-03-26 15:16:46 +0100497# FVP being a development platform, enable capability to disable Authentication
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100498# dynamically if TRUSTED_BOARD_BOOT is set.
Max Shvetsov06dba292019-12-06 11:50:12 +0000499DYN_DISABLE_AUTH := 1
Soby Mathew45e39e22018-03-26 15:16:46 +0100500endif
Manish V Badarkhe2d49ef32021-08-24 14:42:35 +0100501
Marc Bonnicic66fc1b2021-12-16 18:31:02 +0000502ifeq (${SPMC_AT_EL3}, 1)
503PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c
504endif
Wing Li05364b92023-01-26 18:33:43 -0800505
506PSCI_OS_INIT_MODE := 1
Manish Pandey03d87492023-04-24 10:46:21 +0100507
508$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
509ifeq (${PLATFORM_TEST_EA_FFH}, 1)
510 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
511 $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1")
512 endif
513BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
514endif
Madhukar Pappireddy042043b2023-03-02 16:33:25 -0600515
516ifeq (${SPD},spmd)
517BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
518endif