blob: e3068b699a33c70c7a88c29e8f9a3c743c4d071a [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -06002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Kalyani Chidambaram Vaidyanathan456ea502023-04-24 13:32:05 -07003 * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9#include <errno.h>
Scott Brandene5dcf982020-08-25 13:49:32 -070010#include <inttypes.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <stddef.h>
12#include <string.h>
13
14#include <platform_def.h>
15
Varun Wadekarb316e242015-05-19 16:48:04 +053016#include <arch.h>
17#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <bl31/bl31.h>
19#include <common/bl_common.h>
20#include <common/debug.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010021#include <cortex_a57.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053022#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/console.h>
24#include <lib/mmio.h>
25#include <lib/utils.h>
26#include <lib/utils_def.h>
27#include <plat/common/platform.h>
28
Varun Wadekarb316e242015-05-19 16:48:04 +053029#include <memctrl.h>
Varun Wadekar4967c3d2017-07-21 13:34:16 -070030#include <profiler.h>
Varun Wadekar82b0b182019-09-26 08:26:41 -070031#include <smmu.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080032#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080033#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053034#include <tegra_private.h>
35
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080036/* length of Trusty's input parameters (in bytes) */
37#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
38
Varun Wadekarb316e242015-05-19 16:48:04 +053039/*******************************************************************************
40 * Declarations of linker defined symbols which will help us find the layout
41 * of trusted SRAM
42 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -080043IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
Madhukar Pappireddyfc9b4112019-12-23 14:49:52 -060044
Varun Wadekarb316e242015-05-19 16:48:04 +053045extern uint64_t tegra_bl31_phys_base;
46
Varun Wadekar52a15982015-06-05 12:57:27 +053047static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053048static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarfda095f2019-01-02 10:48:18 -080049 .tzdram_size = TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053050};
Varun Wadekar1c4d5e42019-12-17 21:23:24 -080051#ifdef SPD_trusty
52static aapcs64_params_t bl32_args;
53#endif
Varun Wadekarb316e242015-05-19 16:48:04 +053054
55/*******************************************************************************
56 * This variable holds the non-secure image entry address
57 ******************************************************************************/
58extern uint64_t ns_image_entrypoint;
59
60/*******************************************************************************
61 * Return a pointer to the 'entry_point_info' structure of the next image for
62 * security state specified. BL33 corresponds to the non-secure image type
63 * while BL32 corresponds to the secure image type.
64 ******************************************************************************/
65entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
66{
Varun Wadekarfda095f2019-01-02 10:48:18 -080067 entry_point_info_t *ep = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +053068
Varun Wadekar197a75f2016-06-06 10:46:28 -070069 /* return BL32 entry point info if it is valid */
Varun Wadekarfda095f2019-01-02 10:48:18 -080070 if (type == NON_SECURE) {
71 ep = &bl33_image_ep_info;
72 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
73 ep = &bl32_image_ep_info;
74 }
Varun Wadekar52a15982015-06-05 12:57:27 +053075
Varun Wadekarfda095f2019-01-02 10:48:18 -080076 return ep;
Varun Wadekarb316e242015-05-19 16:48:04 +053077}
78
79/*******************************************************************************
80 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
81 * passes this platform specific information.
82 ******************************************************************************/
83plat_params_from_bl2_t *bl31_get_plat_params(void)
84{
85 return &plat_bl31_params_from_bl2;
86}
87
88/*******************************************************************************
89 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
90 * info.
91 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010092void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
93 u_register_t arg2, u_register_t arg3)
Varun Wadekarb316e242015-05-19 16:48:04 +053094{
Kalyani Chidambaram Vaidyanathan456ea502023-04-24 13:32:05 -070095 struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
96 plat_params_from_bl2_t *plat_params = plat_get_bl31_plat_params();
Varun Wadekar4967c3d2017-07-21 13:34:16 -070097 int32_t ret;
Varun Wadekarbaf903e2015-09-22 15:00:06 +053098
Varun Wadekarb316e242015-05-19 16:48:04 +053099 /*
Kalyani Chidambaram Vaidyanathan456ea502023-04-24 13:32:05 -0700100 * Tegra platforms will receive boot parameters through custom
101 * mechanisms. So, we ignore the input parameters.
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700102 */
Kalyani Chidambaram Vaidyanathan456ea502023-04-24 13:32:05 -0700103 (void)arg0;
104 (void)arg1;
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700105
106 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530107 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530108 * They are stored in Secure RAM, in BL2's address space.
109 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800110 assert(arg_from_bl2 != NULL);
111 assert(arg_from_bl2->bl33_ep_info != NULL);
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100112 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530113
Varun Wadekarfda095f2019-01-02 10:48:18 -0800114 if (arg_from_bl2->bl32_ep_info != NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100115 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800116#ifdef SPD_trusty
117 /* save BL32 boot parameters */
118 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args));
119#endif
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800120 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530121
122 /*
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800123 * Parse platform specific parameters
Varun Wadekarb316e242015-05-19 16:48:04 +0530124 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800125 assert(plat_params != NULL);
Varun Wadekar6bb62462015-10-06 12:49:31 +0530126 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
127 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530128 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800129 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800130 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
131 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
Varun Wadekard2014c62015-10-29 10:37:28 +0530132
133 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700134 * It is very important that we run either from TZDRAM or TZSRAM base.
135 * Add an explicit check here.
136 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800137 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
138 (TEGRA_TZRAM_BASE != BL31_BASE)) {
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700139 panic();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800140 }
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700141
142 /*
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700143 * Enable console for the platform
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800144 */
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700145 plat_enable_console(plat_params->uart_id);
Varun Wadekard2014c62015-10-29 10:37:28 +0530146
Varun Wadekar5118b532016-06-04 22:08:50 -0700147 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700148 * The previous bootloader passes the base address of the shared memory
149 * location to store the boot profiler logs. Sanity check the
Andreas Färberd829cd42019-06-17 00:06:43 +0200150 * address and initialise the profiler library, if it looks ok.
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700151 */
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700152 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
153 PROFILER_SIZE_BYTES);
154 if (ret == (int32_t)0) {
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700155
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700156 /* store the membase for the profiler lib */
157 plat_bl31_params_from_bl2.boot_profiler_shmem_base =
158 plat_params->boot_profiler_shmem_base;
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700159
Varun Wadekar6e6ce612018-06-20 13:43:43 -0700160 /* initialise the profiler library */
161 boot_profiler_init(plat_params->boot_profiler_shmem_base,
162 TEGRA_TMRUS_BASE);
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700163 }
164
165 /*
166 * Add timestamp for platform early setup entry.
167 */
168 boot_profiler_add_record("[TF] early setup entry");
169
170 /*
Steven Kao27e64312016-10-21 14:16:59 +0800171 * Initialize delay timer
172 */
173 tegra_delay_timer_init();
174
Varun Wadekardbe67c72017-09-20 15:09:38 -0700175 /* Early platform setup for Tegra SoCs */
176 plat_early_platform_setup();
177
Steven Kao27e64312016-10-21 14:16:59 +0800178 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700179 * Add timestamp for platform early setup exit.
180 */
181 boot_profiler_add_record("[TF] early setup exit");
182
Sandrine Bailleuxfff61b62018-06-21 11:41:43 +0200183 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
184 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
185 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530186}
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800187
188#ifdef SPD_trusty
189void plat_trusty_set_boot_args(aapcs64_params_t *args)
190{
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800191 /*
192 * arg0 = TZDRAM aperture available for BL32
193 * arg1 = BL32 boot params
194 * arg2 = EKS Blob Length
195 * arg3 = Boot Profiler Carveout Base
196 */
197 args->arg0 = bl32_args.arg0;
198 args->arg1 = bl32_args.arg2;
Varun Wadekarc2099802018-12-28 13:50:20 -0800199
200 /* update EKS size */
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800201 args->arg2 = bl32_args.arg4;
Varun Wadekar7a1ba292019-01-02 16:30:01 -0800202
203 /* Profiler Carveout Base */
Varun Wadekar1c4d5e42019-12-17 21:23:24 -0800204 args->arg3 = bl32_args.arg5;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800205}
206#endif
Varun Wadekarb316e242015-05-19 16:48:04 +0530207
208/*******************************************************************************
209 * Initialize the gic, configure the SCR.
210 ******************************************************************************/
211void bl31_platform_setup(void)
212{
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700213 /*
214 * Add timestamp for platform setup entry.
215 */
216 boot_profiler_add_record("[TF] plat setup entry");
217
Varun Wadekarb7b45752015-12-28 14:55:41 -0800218 /* Initialize the gic cpu and distributor interfaces */
219 plat_gic_setup();
220
Varun Wadekarb316e242015-05-19 16:48:04 +0530221 /*
222 * Setup secondary CPU POR infrastructure.
223 */
224 plat_secondary_setup();
225
226 /*
227 * Initial Memory Controller configuration.
228 */
229 tegra_memctrl_setup();
230
231 /*
Dilan Lee1f66f3d2017-10-27 09:51:09 +0800232 * Late setup handler to allow platforms to performs additional
233 * functionality.
234 * This handler gets called with MMU enabled.
235 */
236 plat_late_platform_setup();
237
238 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700239 * Add timestamp for platform setup exit.
240 */
241 boot_profiler_add_record("[TF] plat setup exit");
242
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530243 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530244}
245
246/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800247 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
248 ******************************************************************************/
249void bl31_plat_runtime_setup(void)
250{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700251 /*
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -0700252 * Platform specific runtime setup
Varun Wadekar82b0b182019-09-26 08:26:41 -0700253 */
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -0700254 plat_runtime_setup();
Varun Wadekar82b0b182019-09-26 08:26:41 -0700255
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700256 /*
257 * Add final timestamp before exiting BL31.
258 */
259 boot_profiler_add_record("[TF] bl31 exit");
260 boot_profiler_deinit();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800261}
262
263/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530264 * Perform the very early platform specific architectural setup here. At the
Elyes Haouas2be03c02023-02-13 09:14:48 +0100265 * moment this only initializes the mmu in a quick and dirty way.
Varun Wadekarb316e242015-05-19 16:48:04 +0530266 ******************************************************************************/
267void bl31_plat_arch_setup(void)
268{
Varun Wadekarfda095f2019-01-02 10:48:18 -0800269 uint64_t rw_start = BL31_RW_START;
Kalyani Chidambaram425155a2018-12-19 11:06:14 -0800270 uint64_t rw_size = BL_END - BL31_RW_START;
271 uint64_t rodata_start = BL_RO_DATA_BASE;
272 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
273 uint64_t code_base = BL_CODE_BASE;
274 uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
Varun Wadekarb316e242015-05-19 16:48:04 +0530275 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarfda095f2019-01-02 10:48:18 -0800276 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530277
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700278 /*
279 * Add timestamp for arch setup entry.
280 */
281 boot_profiler_add_record("[TF] arch setup entry");
282
Varun Wadekar922550a2018-01-23 14:38:51 -0800283 /* add MMIO space */
284 plat_mmio_map = plat_get_mmio_map();
285 if (plat_mmio_map != NULL) {
286 mmap_add(plat_mmio_map);
287 } else {
288 WARN("MMIO map not available\n");
289 }
290
Varun Wadekarb316e242015-05-19 16:48:04 +0530291 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800292 mmap_add_region(rw_start, rw_start,
293 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530294 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800295 mmap_add_region(rodata_start, rodata_start,
296 rodata_size,
297 MT_RO_DATA | MT_SECURE);
298 mmap_add_region(code_base, code_base,
299 code_size,
300 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530301
Varun Wadekar922550a2018-01-23 14:38:51 -0800302 /* map TZDRAM used by BL31 as coherent memory */
303 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
304 mmap_add_region(params_from_bl2->tzdram_base,
305 params_from_bl2->tzdram_base,
306 BL31_SIZE,
307 MT_DEVICE | MT_RW | MT_SECURE);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800308 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530309
310 /* set up translation tables */
311 init_xlat_tables();
312
313 /* enable the MMU */
314 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530315
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700316 /*
317 * Add timestamp for arch setup exit.
318 */
319 boot_profiler_add_record("[TF] arch setup exit");
320
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530321 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530322}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530323
324/*******************************************************************************
325 * Check if the given NS DRAM range is valid
326 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -0800327int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
Varun Wadekar7a269e22015-06-10 14:04:32 +0530328{
Varun Wadekarc74343c2017-07-20 09:43:28 -0700329 uint64_t end = base + size_in_bytes - U(1);
Varun Wadekar7a269e22015-06-10 14:04:32 +0530330
331 /*
Varun Wadekar11f5db52020-06-02 21:16:00 -0700332 * Sanity check the input values
333 */
334 if ((base == 0U) || (size_in_bytes == 0U)) {
Scott Brandene5dcf982020-08-25 13:49:32 -0700335 ERROR("NS address 0x%" PRIx64 " (%" PRId64 " bytes) is invalid\n",
Varun Wadekar11f5db52020-06-02 21:16:00 -0700336 base, size_in_bytes);
337 return -EINVAL;
338 }
339
340 /*
Varun Wadekar7a269e22015-06-10 14:04:32 +0530341 * Check if the NS DRAM address is valid
342 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700343 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
344 (end > TEGRA_DRAM_END)) {
345
Scott Brandene5dcf982020-08-25 13:49:32 -0700346 ERROR("NS address 0x%" PRIx64 " is out-of-bounds!\n", base);
Varun Wadekar11f5db52020-06-02 21:16:00 -0700347 return -EFAULT;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530348 }
349
350 /*
351 * TZDRAM aperture contains the BL31 and BL32 images, so we need
352 * to check if the NS DRAM range overlaps the TZDRAM aperture.
353 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700354 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
Scott Brandene5dcf982020-08-25 13:49:32 -0700355 ERROR("NS address 0x%" PRIx64 " overlaps TZDRAM!\n", base);
Varun Wadekar11f5db52020-06-02 21:16:00 -0700356 return -ENOTSUP;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530357 }
358
359 /* valid NS address */
Varun Wadekar11f5db52020-06-02 21:16:00 -0700360 return 0;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530361}