blob: 3c6f48ad814b4a2bbdb08f8d70ec727fef4bd981 [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierdca61542021-02-10 18:19:23 +01002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Yann Gautier658775c2021-07-06 10:00:44 +02008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <string.h>
10
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/desc_image_load.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/generic_delay_timer.h>
Yann Gautiera3bd8d12021-06-18 11:33:26 +020016#include <drivers/mmc.h>
Yann Gautier3edc7c32019-05-20 19:17:08 +020017#include <drivers/st/bsec.h>
Pascal Pailletfc7b8052021-01-29 14:48:49 +010018#include <drivers/st/regulator_fixed.h>
Yann Gautier091eab52019-06-04 18:06:34 +020019#include <drivers/st/stm32_iwdg.h>
Yann Gautier3d8497c2021-10-18 16:06:22 +020020#include <drivers/st/stm32_uart.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/st/stm32mp1_pwr.h>
23#include <drivers/st/stm32mp1_ram.h>
Yann Gautier0c810882021-12-17 09:53:04 +010024#include <drivers/st/stm32mp_pmic.h>
Yann Gautier658775c2021-07-06 10:00:44 +020025#include <lib/fconf/fconf.h>
26#include <lib/fconf/fconf_dyn_cfg_getter.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <lib/mmio.h>
Yann Gautierb3386f72019-04-19 09:41:01 +020028#include <lib/optee_utils.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000029#include <lib/xlat_tables/xlat_tables_v2.h>
30#include <plat/common/platform.h>
31
Yann Gautier0c810882021-12-17 09:53:04 +010032#include <platform_def.h>
Yann Gautier091eab52019-06-04 18:06:34 +020033#include <stm32mp1_dbgmcu.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020034
Lionel Debieve7bd96f42019-09-03 12:22:23 +020035static struct stm32mp_auth_ops stm32mp1_auth_ops;
Yann Gautier8593e442018-11-14 18:46:15 +010036
Yann Gautierf9d40d52019-01-17 14:41:46 +010037static void print_reset_reason(void)
38{
Yann Gautier3d78a2e2019-02-14 11:01:20 +010039 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
Yann Gautierf9d40d52019-01-17 14:41:46 +010040
41 if (rstsr == 0U) {
42 WARN("Reset reason unknown\n");
43 return;
44 }
45
46 INFO("Reset reason (0x%x):\n", rstsr);
47
48 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
49 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
50 INFO("System exits from STANDBY\n");
51 return;
52 }
53
54 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
55 INFO("MPU exits from CSTANDBY\n");
56 return;
57 }
58 }
59
60 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
61 INFO(" Power-on Reset (rst_por)\n");
62 return;
63 }
64
65 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
66 INFO(" Brownout Reset (rst_bor)\n");
67 return;
68 }
69
70 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
71 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
72 INFO(" System reset generated by MCU (MCSYSRST)\n");
73 } else {
74 INFO(" Local reset generated by MCU (MCSYSRST)\n");
75 }
76 return;
77 }
78
79 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
80 INFO(" System reset generated by MPU (MPSYSRST)\n");
81 return;
82 }
83
84 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
85 INFO(" Reset due to a clock failure on HSE\n");
86 return;
87 }
88
89 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
90 INFO(" IWDG1 Reset (rst_iwdg1)\n");
91 return;
92 }
93
94 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
95 INFO(" IWDG2 Reset (rst_iwdg2)\n");
96 return;
97 }
98
99 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
100 INFO(" MPU Processor 0 Reset\n");
101 return;
102 }
103
104 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
105 INFO(" MPU Processor 1 Reset\n");
106 return;
107 }
108
109 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
110 INFO(" Pad Reset from NRST\n");
111 return;
112 }
113
114 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
115 INFO(" Reset due to a failure of VDD_CORE\n");
116 return;
117 }
118
119 ERROR(" Unidentified reset reason\n");
120}
121
122void bl2_el3_early_platform_setup(u_register_t arg0,
123 u_register_t arg1 __unused,
124 u_register_t arg2 __unused,
125 u_register_t arg3 __unused)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200126{
Yann Gautiera2e2a302019-02-14 11:13:39 +0100127 stm32mp_save_boot_ctx_address(arg0);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200128}
129
130void bl2_platform_setup(void)
131{
Yann Gautiercaf575b2018-07-24 17:18:19 +0200132 int ret;
133
Yann Gautiercaf575b2018-07-24 17:18:19 +0200134 ret = stm32mp1_ddr_probe();
135 if (ret < 0) {
136 ERROR("Invalid DDR init: error %d\n", ret);
137 panic();
138 }
139
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200140 /* Map DDR for binary load, now with cacheable attribute */
Yann Gautiera55169b2020-01-10 18:18:59 +0100141 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200142 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
143 if (ret < 0) {
144 ERROR("DDR mapping: error %d\n", ret);
145 panic();
146 }
Yann Gautiera55169b2020-01-10 18:18:59 +0100147
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200148#if STM32MP_USE_STM32IMAGE
Yann Gautierb3386f72019-04-19 09:41:01 +0200149#ifdef AARCH32_SP_OPTEE
150 INFO("BL2 runs OP-TEE setup\n");
Yann Gautierb3386f72019-04-19 09:41:01 +0200151#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200152 INFO("BL2 runs SP_MIN setup\n");
Yann Gautierb3386f72019-04-19 09:41:01 +0200153#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200154#endif /* STM32MP_USE_STM32IMAGE */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200155}
156
157void bl2_el3_plat_arch_setup(void)
158{
Yann Gautier69035a82018-07-05 16:48:16 +0200159 const char *board_model;
Yann Gautier41934662018-07-20 11:36:05 +0200160 boot_api_context_t *boot_context =
Yann Gautiera2e2a302019-02-14 11:13:39 +0100161 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100162 uintptr_t pwr_base;
163 uintptr_t rcc_base;
Yann Gautier41934662018-07-20 11:36:05 +0200164
Yann Gautierf9d40d52019-01-17 14:41:46 +0100165 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
166 BL_CODE_END - BL_CODE_BASE,
167 MT_CODE | MT_SECURE);
168
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200169#if STM32MP_USE_STM32IMAGE
Yann Gautierb3386f72019-04-19 09:41:01 +0200170#ifdef AARCH32_SP_OPTEE
Yann Gautierb3386f72019-04-19 09:41:01 +0200171 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
172 STM32MP_OPTEE_SIZE,
173 MT_MEMORY | MT_RW | MT_SECURE);
Yann Gautier90f84d72021-07-13 14:44:09 +0200174#else
175 /* Prevent corruption of preloaded BL32 */
176 mmap_add_region(BL32_BASE, BL32_BASE,
177 BL32_LIMIT - BL32_BASE,
178 MT_RO_DATA | MT_SECURE);
Yann Gautierb3386f72019-04-19 09:41:01 +0200179#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200180#endif /* STM32MP_USE_STM32IMAGE */
181
Yann Gautierf9d40d52019-01-17 14:41:46 +0100182 /* Prevent corruption of preloaded Device Tree */
183 mmap_add_region(DTB_BASE, DTB_BASE,
184 DTB_LIMIT - DTB_BASE,
Yann Gautier3d33df62019-12-17 17:11:10 +0100185 MT_RO_DATA | MT_SECURE);
Yann Gautierf9d40d52019-01-17 14:41:46 +0100186
187 configure_mmu();
188
Yann Gautier05773eb2020-08-24 11:51:50 +0200189 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100190 panic();
191 }
192
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100193 pwr_base = stm32mp_pwr_base();
194 rcc_base = stm32mp_rcc_base();
195
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200196 /*
197 * Disable the backup domain write protection.
198 * The protection is enable at each reset by hardware
199 * and must be disabled by software.
200 */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100201 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200202
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100203 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200204 ;
205 }
206
Yann Gautier3edc7c32019-05-20 19:17:08 +0200207 if (bsec_probe() != 0) {
208 panic();
209 }
210
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200211 /* Reset backup domain on cold boot cases */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100212 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
213 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200214
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100215 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200216 0U) {
217 ;
218 }
219
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100220 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200221 }
222
Yann Gautiered342322019-02-15 17:33:27 +0100223 /* Disable MCKPROT */
224 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
225
Yann Gautierc0882f42021-04-27 18:19:13 +0200226 /*
227 * Set minimum reset pulse duration to 31ms for discrete power
228 * supplied boards.
229 */
230 if (dt_pmic_status() <= 0) {
231 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR,
232 RCC_RDLSICR_MRD_MASK,
233 31U << RCC_RDLSICR_MRD_SHIFT);
234 }
235
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200236 generic_delay_timer_init();
237
Yann Gautier3d8497c2021-10-18 16:06:22 +0200238#if STM32MP_UART_PROGRAMMER
239 /* Disable programmer UART before changing clock tree */
240 if (boot_context->boot_interface_selected ==
241 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) {
242 uintptr_t uart_prog_addr =
243 get_uart_address(boot_context->boot_interface_instance);
244
245 stm32_uart_stop(uart_prog_addr);
246 }
247#endif
Yann Gautier9aea69e2018-07-24 17:13:36 +0200248 if (stm32mp1_clk_probe() < 0) {
249 panic();
250 }
251
252 if (stm32mp1_clk_init() < 0) {
253 panic();
254 }
255
Yann Gautier6eef5252021-12-10 17:04:40 +0100256 stm32_save_boot_interface(boot_context->boot_interface_selected,
257 boot_context->boot_interface_instance);
258
Yann Gautiercd16df32021-06-04 14:04:05 +0200259#if STM32MP_USB_PROGRAMMER
260 /* Deconfigure all UART RX pins configured by ROM code */
261 stm32mp1_deconfigure_uart_pins();
262#endif
263
Yann Gautier66baa962021-10-18 14:01:00 +0200264 if (stm32mp_uart_console_setup() != 0) {
Yann Gautier69035a82018-07-05 16:48:16 +0200265 goto skip_console_init;
266 }
267
Yann Gautierc7374052019-06-04 18:02:37 +0200268 stm32mp_print_cpuinfo();
269
Yann Gautier69035a82018-07-05 16:48:16 +0200270 board_model = dt_get_board_model();
271 if (board_model != NULL) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100272 NOTICE("Model: %s\n", board_model);
Yann Gautier69035a82018-07-05 16:48:16 +0200273 }
274
Yann Gautier35dc0772019-05-13 18:34:48 +0200275 stm32mp_print_boardinfo();
276
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200277 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
278 NOTICE("Bootrom authentication %s\n",
279 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
280 "failed" : "succeeded");
281 }
282
Yann Gautier69035a82018-07-05 16:48:16 +0200283skip_console_init:
Pascal Pailletfc7b8052021-01-29 14:48:49 +0100284 if (fixed_regulator_register() != 0) {
285 panic();
286 }
287
Yann Gautier45c1e582020-09-17 11:54:52 +0200288 if (dt_pmic_status() > 0) {
289 initialize_pmic();
Nicolas Le Bayon0b10b652019-11-18 13:13:36 +0100290 print_pmic_info_and_debug();
Yann Gautier45c1e582020-09-17 11:54:52 +0200291 }
292
293 stm32mp1_syscfg_init();
294
Yann Gautier091eab52019-06-04 18:06:34 +0200295 if (stm32_iwdg_init() < 0) {
296 panic();
297 }
298
299 stm32_iwdg_refresh();
300
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200301 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
302 stm32mp1_auth_ops.verify_signature =
303 boot_context->bootrom_ecdsa_verify_signature;
304
305 stm32mp_init_auth(&stm32mp1_auth_ops);
306
Yann Gautiercaf575b2018-07-24 17:18:19 +0200307 stm32mp1_arch_security_setup();
308
Yann Gautierf9d40d52019-01-17 14:41:46 +0100309 print_reset_reason();
310
Yann Gautier29f1f942021-07-13 18:07:41 +0200311#if !STM32MP_USE_STM32IMAGE
312 fconf_populate("TB_FW", STM32MP_DTB_BASE);
313#endif /* !STM32MP_USE_STM32IMAGE */
314
Yann Gautiera2e2a302019-02-14 11:13:39 +0100315 stm32mp_io_setup();
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200316}
Yann Gautierb3386f72019-04-19 09:41:01 +0200317
Yann Gautierb3386f72019-04-19 09:41:01 +0200318/*******************************************************************************
319 * This function can be used by the platforms to update/use image
320 * information for given `image_id`.
321 ******************************************************************************/
322int bl2_plat_handle_post_image_load(unsigned int image_id)
323{
324 int err = 0;
325 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
326 bl_mem_params_node_t *bl32_mem_params;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200327 bl_mem_params_node_t *pager_mem_params __unused;
328 bl_mem_params_node_t *paged_mem_params __unused;
Yann Gautier658775c2021-07-06 10:00:44 +0200329#if !STM32MP_USE_STM32IMAGE
330 const struct dyn_cfg_dtb_info_t *config_info;
331 bl_mem_params_node_t *tos_fw_mem_params;
332 unsigned int i;
Yann Gautierfd648352021-12-13 15:24:41 +0100333 unsigned int idx;
Yann Gautier658775c2021-07-06 10:00:44 +0200334 unsigned long long ddr_top __unused;
335 const unsigned int image_ids[] = {
336 BL32_IMAGE_ID,
337 BL33_IMAGE_ID,
338 HW_CONFIG_ID,
339 TOS_FW_CONFIG_ID,
340 };
341#endif /* !STM32MP_USE_STM32IMAGE */
Yann Gautierb3386f72019-04-19 09:41:01 +0200342
343 assert(bl_mem_params != NULL);
344
345 switch (image_id) {
Yann Gautier658775c2021-07-06 10:00:44 +0200346#if !STM32MP_USE_STM32IMAGE
347 case FW_CONFIG_ID:
348 /* Set global DTB info for fixed fw_config information */
349 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
350 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
351
Yann Gautierfd648352021-12-13 15:24:41 +0100352 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID);
353
Yann Gautier658775c2021-07-06 10:00:44 +0200354 /* Iterate through all the fw config IDs */
355 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
Yann Gautierfd648352021-12-13 15:24:41 +0100356 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) {
357 continue;
358 }
359
Yann Gautier658775c2021-07-06 10:00:44 +0200360 bl_mem_params = get_bl_mem_params_node(image_ids[i]);
361 assert(bl_mem_params != NULL);
362
363 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
364 if (config_info == NULL) {
365 continue;
366 }
367
368 bl_mem_params->image_info.image_base = config_info->config_addr;
369 bl_mem_params->image_info.image_max_size = config_info->config_max_size;
370
371 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
372
373 switch (image_ids[i]) {
374 case BL32_IMAGE_ID:
375 bl_mem_params->ep_info.pc = config_info->config_addr;
376
377 /* In case of OPTEE, initialize address space with tos_fw addr */
378 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
379 pager_mem_params->image_info.image_base = config_info->config_addr;
380 pager_mem_params->image_info.image_max_size =
381 config_info->config_max_size;
382
383 /* Init base and size for pager if exist */
384 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
385 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
386 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
387 STM32MP_DDR_SHMEM_SIZE);
388 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
389 break;
390
391 case BL33_IMAGE_ID:
392 bl_mem_params->ep_info.pc = config_info->config_addr;
393 break;
394
395 case HW_CONFIG_ID:
396 case TOS_FW_CONFIG_ID:
397 break;
398
399 default:
400 return -EINVAL;
401 }
402 }
403 break;
404#endif /* !STM32MP_USE_STM32IMAGE */
405
Yann Gautierb3386f72019-04-19 09:41:01 +0200406 case BL32_IMAGE_ID:
Yann Gautier90f84d72021-07-13 14:44:09 +0200407 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
408 /* BL32 is OP-TEE header */
409 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
410 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
411 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
412 assert((pager_mem_params != NULL) && (paged_mem_params != NULL));
Yann Gautierb3386f72019-04-19 09:41:01 +0200413
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200414#if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE)
Yann Gautier90f84d72021-07-13 14:44:09 +0200415 /* Set OP-TEE extra image load areas at run-time */
416 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
417 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE;
Yann Gautierb3386f72019-04-19 09:41:01 +0200418
Yann Gautier90f84d72021-07-13 14:44:09 +0200419 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
420 dt_get_ddr_size() -
421 STM32MP_DDR_S_SIZE -
422 STM32MP_DDR_SHMEM_SIZE;
423 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200424#endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */
Yann Gautierb3386f72019-04-19 09:41:01 +0200425
Yann Gautier90f84d72021-07-13 14:44:09 +0200426 err = parse_optee_header(&bl_mem_params->ep_info,
427 &pager_mem_params->image_info,
428 &paged_mem_params->image_info);
429 if (err) {
430 ERROR("OPTEE header parse error.\n");
431 panic();
432 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200433
Yann Gautier90f84d72021-07-13 14:44:09 +0200434 /* Set optee boot info from parsed header data */
435 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base;
436 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
437 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200438 } else {
439#if !STM32MP_USE_STM32IMAGE
440 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
Yann Gautier658775c2021-07-06 10:00:44 +0200441 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
442 bl_mem_params->image_info.image_max_size +=
443 tos_fw_mem_params->image_info.image_max_size;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200444#endif /* !STM32MP_USE_STM32IMAGE */
445 bl_mem_params->ep_info.args.arg0 = 0;
Yann Gautier90f84d72021-07-13 14:44:09 +0200446 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200447 break;
448
449 case BL33_IMAGE_ID:
450 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
451 assert(bl32_mem_params != NULL);
452 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
453 break;
454
455 default:
456 /* Do nothing in default case */
457 break;
458 }
459
Yann Gautiera3bd8d12021-06-18 11:33:26 +0200460#if STM32MP_SDMMC || STM32MP_EMMC
461 /*
462 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
463 * We take the worst case which is 2 MMC blocks.
464 */
465 if ((image_id != FW_CONFIG_ID) &&
466 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
467 inv_dcache_range(bl_mem_params->image_info.image_base +
468 bl_mem_params->image_info.image_size,
469 2U * MMC_BLOCK_SIZE);
470 }
471#endif /* STM32MP_SDMMC || STM32MP_EMMC */
472
Yann Gautierb3386f72019-04-19 09:41:01 +0200473 return err;
474}
Yann Gautierd2d9b962021-08-16 11:58:01 +0200475
476void bl2_el3_plat_prepare_exit(void)
477{
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200478 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
479
480 switch (boot_itf) {
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200481#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
482 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200483 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
484 /* Invalidate the downloaded buffer used with io_memmap */
485 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
486 break;
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200487#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200488 default:
489 /* Do nothing in default case */
490 break;
491 }
492
Yann Gautierd2d9b962021-08-16 11:58:01 +0200493 stm32mp1_security_setup();
494}