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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
Jit Loon Lim86f6fb32023-05-17 12:26:11 +08002 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/debug.h>
9#include <common/runtime_svc.h>
Hadi Asyrafi67942302019-10-22 13:28:51 +080010#include <lib/mmio.h>
Hadi Asyrafi616da772019-06-27 11:34:03 +080011#include <tools_share/uuid.h>
12
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080013#include "socfpga_fcs.h"
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080014#include "socfpga_mailbox.h"
Jit Loon Lim86f6fb32023-05-17 12:26:11 +080015#include "socfpga_plat_def.h"
Hadi Asyrafi36a9f302019-12-24 10:42:52 +080016#include "socfpga_reset_manager.h"
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080017#include "socfpga_sip_svc.h"
Jit Loon Lim86f6fb32023-05-17 12:26:11 +080018#include "socfpga_system_manager.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080019
20/* Total buffer the driver can hold */
21#define FPGA_CONFIG_BUFFER_SIZE 4
22
Sieu Mun Tangc3667602022-05-13 14:55:05 +080023static config_type request_type = NO_REQUEST;
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080024static int current_block, current_buffer;
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +080025static int read_block, max_blocks;
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080026static uint32_t send_id, rcv_id;
27static uint32_t bytes_per_block, blocks_submitted;
Sieu Mun Tang54064982022-04-28 22:40:58 +080028static bool bridge_disable;
Hadi Asyrafi616da772019-06-27 11:34:03 +080029
Sieu Mun Tange6d5de92022-04-28 22:21:01 +080030/* RSU static variables */
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +080031static uint32_t rsu_dcmf_ver[4] = {0};
Sieu Mun Tange6d5de92022-04-28 22:21:01 +080032static uint16_t rsu_dcmf_stat[4] = {0};
Sieu Mun Tangc3667602022-05-13 14:55:05 +080033static uint32_t rsu_max_retry;
Hadi Asyrafi616da772019-06-27 11:34:03 +080034
35/* SiP Service UUID */
36DEFINE_SVC_UUID2(intl_svc_uid,
37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
39
Hadi Asyraficee6aa92019-12-17 15:25:04 +080040static uint64_t socfpga_sip_handler(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +080041 uint64_t x1,
42 uint64_t x2,
43 uint64_t x3,
44 uint64_t x4,
45 void *cookie,
46 void *handle,
47 uint64_t flags)
48{
49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
50 SMC_RET1(handle, SMC_UNK);
51}
52
53struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
54
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080055static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
Hadi Asyrafi616da772019-06-27 11:34:03 +080056{
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +080057 uint32_t args[3];
Hadi Asyrafi616da772019-06-27 11:34:03 +080058
59 while (max_blocks > 0 && buffer->size > buffer->size_written) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080060 args[0] = (1<<8);
61 args[1] = buffer->addr + buffer->size_written;
62 if (buffer->size - buffer->size_written <= bytes_per_block) {
Hadi Asyrafi616da772019-06-27 11:34:03 +080063 args[2] = buffer->size - buffer->size_written;
Hadi Asyrafi616da772019-06-27 11:34:03 +080064 current_buffer++;
65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080066 } else {
Hadi Asyrafi616da772019-06-27 11:34:03 +080067 args[2] = bytes_per_block;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080068 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080069
70 buffer->size_written += args[2];
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080071 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +080072 3U, CMD_INDIRECT);
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080073
74 buffer->subblocks_sent++;
Hadi Asyrafi616da772019-06-27 11:34:03 +080075 max_blocks--;
76 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080077
78 return !max_blocks;
Hadi Asyrafi616da772019-06-27 11:34:03 +080079}
80
81static int intel_fpga_sdm_write_all(void)
82{
Sieu Mun Tang28af1652022-05-09 10:48:53 +080083 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080084 if (intel_fpga_sdm_write_buffer(
Sieu Mun Tang28af1652022-05-09 10:48:53 +080085 &fpga_config_buffers[current_buffer])) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080086 break;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080087 }
88 }
Hadi Asyrafi616da772019-06-27 11:34:03 +080089 return 0;
90}
91
Sieu Mun Tangc3667602022-05-13 14:55:05 +080092static uint32_t intel_mailbox_fpga_config_isdone(void)
Hadi Asyrafi616da772019-06-27 11:34:03 +080093{
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +080094 uint32_t ret;
95
Sieu Mun Tangc3667602022-05-13 14:55:05 +080096 switch (request_type) {
97 case RECONFIGURATION:
98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
99 true);
100 break;
101 case BITSTREAM_AUTH:
102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
103 false);
104 break;
105 default:
106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
107 false);
108 break;
Kris Chapline768dfa2021-06-25 11:31:52 +0100109 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800110
Abdul Halim, Muhammad Hadi Asyrafi959143d2020-12-29 16:49:23 +0800111 if (ret != 0U) {
Kris Chapline768dfa2021-06-25 11:31:52 +0100112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800113 return INTEL_SIP_SMC_STATUS_BUSY;
Kris Chapline768dfa2021-06-25 11:31:52 +0100114 } else {
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800115 request_type = NO_REQUEST;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800116 return INTEL_SIP_SMC_STATUS_ERROR;
Kris Chapline768dfa2021-06-25 11:31:52 +0100117 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800118 }
119
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800120 if (bridge_disable != 0U) {
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800121 socfpga_bridges_enable(~0); /* Enable bridge */
Sieu Mun Tang54064982022-04-28 22:40:58 +0800122 bridge_disable = false;
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800123 }
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800124 request_type = NO_REQUEST;
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800125
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800126 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800127}
128
129static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
130{
131 int i;
132
133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
134 if (fpga_config_buffers[i].block_number == current_block) {
135 fpga_config_buffers[i].subblocks_sent--;
136 if (fpga_config_buffers[i].subblocks_sent == 0
137 && fpga_config_buffers[i].size <=
138 fpga_config_buffers[i].size_written) {
139 fpga_config_buffers[i].write_requested = 0;
140 current_block++;
141 *buffer_addr_completed =
142 fpga_config_buffers[i].addr;
143 return 0;
144 }
145 }
146 }
147
148 return -1;
149}
150
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800151static int intel_fpga_config_completed_write(uint32_t *completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800152 uint32_t *count, uint32_t *job_id)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800153{
Hadi Asyrafi616da772019-06-27 11:34:03 +0800154 uint32_t resp[5];
Sieu Mun Tang24682662022-02-19 21:49:48 +0800155 unsigned int resp_len = ARRAY_SIZE(resp);
156 int status = INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800157 int all_completed = 1;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800158 *count = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800159
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800160 while (*count < 3) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800161
Sieu Mun Tang24682662022-02-19 21:49:48 +0800162 status = mailbox_read_response(job_id,
163 resp, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800164
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800165 if (status < 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800166 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800167 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800168
Hadi Asyrafi616da772019-06-27 11:34:03 +0800169 max_blocks++;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800170
Hadi Asyrafi616da772019-06-27 11:34:03 +0800171 if (mark_last_buffer_xfer_completed(
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800172 &completed_addr[*count]) == 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800173 *count = *count + 1;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800174 } else {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800175 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800176 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800177 }
178
179 if (*count <= 0) {
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800180 if (status != MBOX_NO_RESPONSE &&
181 status != MBOX_TIMEOUT && resp_len != 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800182 mailbox_clear_response();
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800183 request_type = NO_REQUEST;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800184 return INTEL_SIP_SMC_STATUS_ERROR;
185 }
186
187 *count = 0;
188 }
189
190 intel_fpga_sdm_write_all();
191
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800192 if (*count > 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800193 status = INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800194 } else if (*count == 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800195 status = INTEL_SIP_SMC_STATUS_BUSY;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800196 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800197
198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
199 if (fpga_config_buffers[i].write_requested != 0) {
200 all_completed = 0;
201 break;
202 }
203 }
204
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800205 if (all_completed == 1) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800206 return INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800207 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800208
209 return status;
210}
211
Sieu Mun Tang54064982022-04-28 22:40:58 +0800212static int intel_fpga_config_start(uint32_t flag)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800213{
Sieu Mun Tang24682662022-02-19 21:49:48 +0800214 uint32_t argument = 0x1;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800215 uint32_t response[3];
216 int status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800217 unsigned int size = 0;
218 unsigned int resp_len = ARRAY_SIZE(response);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800219
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800220 request_type = RECONFIGURATION;
221
Sieu Mun Tang54064982022-04-28 22:40:58 +0800222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
223 bridge_disable = true;
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +0800224 }
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800225
Sieu Mun Tang54064982022-04-28 22:40:58 +0800226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
227 size = 1;
228 bridge_disable = false;
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800229 request_type = BITSTREAM_AUTH;
Sieu Mun Tang54064982022-04-28 22:40:58 +0800230 }
231
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800232 mailbox_clear_response();
233
Sieu Mun Tang24682662022-02-19 21:49:48 +0800234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
235 CMD_CASUAL, NULL, NULL);
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800236
Sieu Mun Tang24682662022-02-19 21:49:48 +0800237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
238 CMD_CASUAL, response, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800239
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800240 if (status < 0) {
Sieu Mun Tang54064982022-04-28 22:40:58 +0800241 bridge_disable = false;
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800242 request_type = NO_REQUEST;
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800243 return INTEL_SIP_SMC_STATUS_ERROR;
244 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800245
246 max_blocks = response[0];
247 bytes_per_block = response[1];
248
249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
250 fpga_config_buffers[i].size = 0;
251 fpga_config_buffers[i].size_written = 0;
252 fpga_config_buffers[i].addr = 0;
253 fpga_config_buffers[i].write_requested = 0;
254 fpga_config_buffers[i].block_number = 0;
255 fpga_config_buffers[i].subblocks_sent = 0;
256 }
257
258 blocks_submitted = 0;
259 current_block = 0;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800260 read_block = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800261 current_buffer = 0;
262
Sieu Mun Tang54064982022-04-28 22:40:58 +0800263 /* Disable bridge on full reconfiguration */
264 if (bridge_disable) {
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800265 socfpga_bridges_disable(~0);
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800266 }
267
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800268 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800269}
270
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800271static bool is_fpga_config_buffer_full(void)
272{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
274 if (!fpga_config_buffers[i].write_requested) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800275 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800276 }
277 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800278 return true;
279}
280
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800281bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800282{
Abdul Halim, Muhammad Hadi Asyrafi461f5442020-07-03 13:22:09 +0800283 if (!addr && !size) {
284 return true;
285 }
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800286 if (size > (UINT64_MAX - addr)) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800287 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800288 }
289 if (addr < BL31_LIMIT) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800290 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800291 }
292 if (addr + size > DRAM_BASE + DRAM_SIZE) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800293 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800294 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800295
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800296 return true;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800297}
Hadi Asyrafi616da772019-06-27 11:34:03 +0800298
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800299static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800300{
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800301 int i;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800302
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800303 intel_fpga_sdm_write_all();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800304
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800305 if (!is_address_in_ddr_range(mem, size) ||
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800306 is_fpga_config_buffer_full()) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800307 return INTEL_SIP_SMC_STATUS_REJECTED;
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800308 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800309
310 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800311 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
312
313 if (!fpga_config_buffers[j].write_requested) {
314 fpga_config_buffers[j].addr = mem;
315 fpga_config_buffers[j].size = size;
316 fpga_config_buffers[j].size_written = 0;
317 fpga_config_buffers[j].write_requested = 1;
318 fpga_config_buffers[j].block_number =
Hadi Asyrafi616da772019-06-27 11:34:03 +0800319 blocks_submitted++;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800320 fpga_config_buffers[j].subblocks_sent = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800321 break;
322 }
323 }
324
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800325 if (is_fpga_config_buffer_full()) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800326 return INTEL_SIP_SMC_STATUS_BUSY;
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800327 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800328
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800329 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800330}
331
Hadi Asyrafi67942302019-10-22 13:28:51 +0800332static int is_out_of_sec_range(uint64_t reg_addr)
333{
Siew Chin Lim869d4f52021-05-11 21:12:22 +0800334#if DEBUG
335 return 0;
336#endif
337
Jit Loon Lim7787efe2023-05-17 12:26:11 +0800338#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
Hadi Asyrafi67942302019-10-22 13:28:51 +0800339 switch (reg_addr) {
340 case(0xF8011100): /* ECCCTRL1 */
341 case(0xF8011104): /* ECCCTRL2 */
342 case(0xF8011110): /* ERRINTEN */
343 case(0xF8011114): /* ERRINTENS */
344 case(0xF8011118): /* ERRINTENR */
345 case(0xF801111C): /* INTMODE */
346 case(0xF8011120): /* INTSTAT */
347 case(0xF8011124): /* DIAGINTTEST */
348 case(0xF801112C): /* DERRADDRA */
Sieu Mun Tangbd8da632022-09-28 15:58:28 +0800349 case(0xFA000000): /* SMMU SCR0 */
350 case(0xFA000004): /* SMMU SCR1 */
351 case(0xFA000400): /* SMMU NSCR0 */
352 case(0xFA004000): /* SMMU SSD0_REG */
353 case(0xFA000820): /* SMMU SMR8 */
354 case(0xFA000c20): /* SMMU SCR8 */
355 case(0xFA028000): /* SMMU CB8_SCTRL */
356 case(0xFA001020): /* SMMU CBAR8 */
357 case(0xFA028030): /* SMMU TCR_LPAE */
358 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */
359 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */
360 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */
361 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */
362 case(0xFA028010): /* SMMU_CB8)TCR2 */
363 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */
364 case(0xFA001820): /* SMMU_CBA2R8 */
365 case(0xFA000074): /* SMMU_STLBGSTATUS */
366 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */
367 case(0xFA000060): /* SMMU_STLBIALL */
368 case(0xFA000070): /* SMMU_STLBGSYNC */
369 case(0xFA028618): /* CB8_TLBALL */
370 case(0xFA0287F0): /* CB8_TLBSYNC */
Hadi Asyrafi67942302019-10-22 13:28:51 +0800371 case(0xFFD12028): /* SDMMCGRP_CTRL */
372 case(0xFFD12044): /* EMAC0 */
373 case(0xFFD12048): /* EMAC1 */
374 case(0xFFD1204C): /* EMAC2 */
375 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
376 case(0xFFD12094): /* ECC_INT_MASK_SET */
377 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
378 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
379 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
380 case(0xFFD120C0): /* NOC_TIMEOUT */
381 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
382 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
383 case(0xFFD120D0): /* NOC_IDLEACK */
384 case(0xFFD120D4): /* NOC_IDLESTATUS */
385 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
386 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
387 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
388 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
389 return 0;
Jit Loon Lim7787efe2023-05-17 12:26:11 +0800390#else
391 switch (reg_addr) {
392
393 case(0xF8011104): /* ECCCTRL2 */
394 case(0xFFD12028): /* SDMMCGRP_CTRL */
395 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
396 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
397 case(0xFFD120D0): /* NOC_IDLEACK */
398
Hadi Asyrafi67942302019-10-22 13:28:51 +0800399
Jit Loon Lim7787efe2023-05-17 12:26:11 +0800400 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */
401 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */
402 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */
403 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */
404 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */
405 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */
406 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */
407 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */
408
409 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
410 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
411 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */
412 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */
413 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */
414 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */
415 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */
416 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */
417 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */
418 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */
419 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */
420 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
421 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
422 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
423 return 0;
424#endif
Hadi Asyrafi67942302019-10-22 13:28:51 +0800425 default:
426 break;
427 }
428
429 return -1;
430}
431
432/* Secure register access */
433uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
434{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800435 if (is_out_of_sec_range(reg_addr)) {
Hadi Asyrafi67942302019-10-22 13:28:51 +0800436 return INTEL_SIP_SMC_STATUS_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800437 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800438
439 *retval = mmio_read_32(reg_addr);
440
441 return INTEL_SIP_SMC_STATUS_OK;
442}
443
444uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
445 uint32_t *retval)
446{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800447 if (is_out_of_sec_range(reg_addr)) {
Hadi Asyrafi67942302019-10-22 13:28:51 +0800448 return INTEL_SIP_SMC_STATUS_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800449 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800450
451 mmio_write_32(reg_addr, val);
452
453 return intel_secure_reg_read(reg_addr, retval);
454}
455
456uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
457 uint32_t val, uint32_t *retval)
458{
459 if (!intel_secure_reg_read(reg_addr, retval)) {
460 *retval &= ~mask;
Siew Chin Lima0763152021-07-10 00:55:35 +0800461 *retval |= val & mask;
Hadi Asyrafi67942302019-10-22 13:28:51 +0800462 return intel_secure_reg_write(reg_addr, *retval, retval);
463 }
464
465 return INTEL_SIP_SMC_STATUS_ERROR;
466}
467
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800468/* Intel Remote System Update (RSU) services */
469uint64_t intel_rsu_update_address;
470
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +0800471static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800472{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800473 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800474 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800475 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800476
477 return INTEL_SIP_SMC_STATUS_OK;
478}
479
Mahesh Rao1e1c8c42023-05-23 14:33:45 +0800480uint32_t intel_rsu_update(uint64_t update_address)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800481{
Jit Loon Lim581ad472023-05-17 12:26:11 +0800482 if (update_address > SIZE_MAX) {
483 return INTEL_SIP_SMC_STATUS_REJECTED;
484 }
485
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800486 intel_rsu_update_address = update_address;
487 return INTEL_SIP_SMC_STATUS_OK;
488}
489
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800490static uint32_t intel_rsu_notify(uint32_t execution_stage)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800491{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800492 if (mailbox_hps_stage_notify(execution_stage) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800493 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800494 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800495
496 return INTEL_SIP_SMC_STATUS_OK;
497}
498
499static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
500 uint32_t *ret_stat)
501{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800502 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800503 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800504 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800505
506 *ret_stat = respbuf[8];
507 return INTEL_SIP_SMC_STATUS_OK;
508}
509
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +0800510static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
511 uint64_t dcmf_ver_3_2)
512{
513 rsu_dcmf_ver[0] = dcmf_ver_1_0;
514 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
515 rsu_dcmf_ver[2] = dcmf_ver_3_2;
516 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
517
518 return INTEL_SIP_SMC_STATUS_OK;
519}
520
Sieu Mun Tange6d5de92022-04-28 22:21:01 +0800521static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
522{
523 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
524 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
525 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
526 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
527
528 return INTEL_SIP_SMC_STATUS_OK;
529}
530
Kris Chapline768dfa2021-06-25 11:31:52 +0100531/* Intel HWMON services */
532static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
533{
Kris Chapline768dfa2021-06-25 11:31:52 +0100534 if (mailbox_hwmon_readtemp(chan, retval) < 0) {
535 return INTEL_SIP_SMC_STATUS_ERROR;
536 }
537
538 return INTEL_SIP_SMC_STATUS_OK;
539}
540
541static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
542{
Kris Chapline768dfa2021-06-25 11:31:52 +0100543 if (mailbox_hwmon_readvolt(chan, retval) < 0) {
544 return INTEL_SIP_SMC_STATUS_ERROR;
545 }
546
547 return INTEL_SIP_SMC_STATUS_OK;
548}
549
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800550/* Mailbox services */
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800551static uint32_t intel_smc_fw_version(uint32_t *fw_version)
552{
Sieu Mun Tangbfda95a2022-04-27 18:54:10 +0800553 int status;
554 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
555 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
556
557 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
558 CMD_CASUAL, resp_data, &resp_len);
559
560 if (status < 0) {
561 return INTEL_SIP_SMC_STATUS_ERROR;
562 }
563
564 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
565 return INTEL_SIP_SMC_STATUS_ERROR;
566 }
567
568 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800569
570 return INTEL_SIP_SMC_STATUS_OK;
571}
572
Sieu Mun Tang24682662022-02-19 21:49:48 +0800573static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800574 unsigned int len, uint32_t urgent, uint64_t response,
Sieu Mun Tang24682662022-02-19 21:49:48 +0800575 unsigned int resp_len, int *mbox_status,
576 unsigned int *len_in_resp)
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800577{
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800578 *len_in_resp = 0;
Sieu Mun Tang96bbdca2022-04-12 15:00:13 +0800579 *mbox_status = GENERIC_RESPONSE_ERROR;
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800580
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800581 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800582 return INTEL_SIP_SMC_STATUS_REJECTED;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800583 }
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800584
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800585 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800586 (uint32_t *) response, &resp_len);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800587
588 if (status < 0) {
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800589 *mbox_status = -status;
590 return INTEL_SIP_SMC_STATUS_ERROR;
591 }
592
593 *mbox_status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800594 *len_in_resp = resp_len;
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800595
596 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE);
597
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800598 return INTEL_SIP_SMC_STATUS_OK;
599}
600
Sieu Mun Tang2b8e0052022-04-27 18:57:29 +0800601static int intel_smc_get_usercode(uint32_t *user_code)
602{
603 int status;
604 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
605
606 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
607 0U, CMD_CASUAL, user_code, &resp_len);
608
609 if (status < 0) {
610 return INTEL_SIP_SMC_STATUS_ERROR;
611 }
612
613 return INTEL_SIP_SMC_STATUS_OK;
614}
615
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800616uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size,
617 uint32_t mode, uint32_t *job_id,
618 uint32_t *ret_size, uint32_t *mbox_error)
619{
620 int status = 0;
621 uint32_t resp_len = size / MBOX_WORD_BYTE;
622
623 if (resp_len > MBOX_DATA_MAX_LEN) {
624 return INTEL_SIP_SMC_STATUS_REJECTED;
625 }
626
627 if (!is_address_in_ddr_range(addr, size)) {
628 return INTEL_SIP_SMC_STATUS_REJECTED;
629 }
630
631 if (mode == SERVICE_COMPLETED_MODE_ASYNC) {
632 status = mailbox_read_response_async(job_id,
633 NULL, (uint32_t *) addr, &resp_len, 0);
634 } else {
635 status = mailbox_read_response(job_id,
636 (uint32_t *) addr, &resp_len);
637
638 if (status == MBOX_NO_RESPONSE) {
639 status = MBOX_BUSY;
640 }
641 }
642
643 if (status == MBOX_NO_RESPONSE) {
644 return INTEL_SIP_SMC_STATUS_NO_RESPONSE;
645 }
646
647 if (status == MBOX_BUSY) {
648 return INTEL_SIP_SMC_STATUS_BUSY;
649 }
650
651 *ret_size = resp_len * MBOX_WORD_BYTE;
652 flush_dcache_range(addr, *ret_size);
653
Sieu Mun Tang6c7f0c72022-12-04 01:43:35 +0800654 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
655 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
656 *mbox_error = -status;
657 } else if (status != MBOX_RET_OK) {
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800658 *mbox_error = -status;
659 return INTEL_SIP_SMC_STATUS_ERROR;
660 }
661
662 return INTEL_SIP_SMC_STATUS_OK;
663}
664
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800665/* Miscellaneous HPS services */
666uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
667{
668 int status = 0;
669
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800670 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) {
671 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800672 status = socfpga_bridges_enable((uint32_t)mask);
673 } else {
674 status = socfpga_bridges_enable(~0);
675 }
676 } else {
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800677 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800678 status = socfpga_bridges_disable((uint32_t)mask);
679 } else {
680 status = socfpga_bridges_disable(~0);
681 }
682 }
683
684 if (status < 0) {
685 return INTEL_SIP_SMC_STATUS_ERROR;
686 }
687
688 return INTEL_SIP_SMC_STATUS_OK;
689}
690
Jit Loon Lim2bee1732023-05-17 12:26:11 +0800691/* SDM SEU Error services */
Jit Loon Limb46c8692023-09-20 14:00:41 +0800692static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz)
Jit Loon Lim2bee1732023-05-17 12:26:11 +0800693{
Jit Loon Limb46c8692023-09-20 14:00:41 +0800694 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) {
Jit Loon Lim2bee1732023-05-17 12:26:11 +0800695 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
696 }
697
698 return INTEL_SIP_SMC_STATUS_OK;
699}
700
Jit Loon Limb46c8692023-09-20 14:00:41 +0800701/* SDM SAFE SEU Error inject services */
702static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len)
703{
704 if (mailbox_safe_inject_seu_err(command, len) < 0) {
705 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
706 }
707
708 return INTEL_SIP_SMC_STATUS_OK;
709}
710
Hadi Asyrafi616da772019-06-27 11:34:03 +0800711/*
712 * This function is responsible for handling all SiP calls from the NS world
713 */
714
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800715uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800716 u_register_t x1,
717 u_register_t x2,
718 u_register_t x3,
719 u_register_t x4,
720 void *cookie,
721 void *handle,
722 u_register_t flags)
723{
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800724 uint32_t retval = 0, completed_addr[3];
725 uint32_t retval2 = 0;
Sieu Mun Tanga34b8812022-03-17 03:11:55 +0800726 uint32_t mbox_error = 0;
Jit Loon Limb46c8692023-09-20 14:00:41 +0800727 uint64_t retval64, rsu_respbuf[9];
728 uint32_t seu_respbuf[3];
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800729 int status = INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800730 int mbox_status;
731 unsigned int len_in_resp;
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800732 u_register_t x5, x6, x7;
Abdul Halim, Muhammad Hadi Asyrafib45f15e2020-05-14 15:32:43 +0800733
Hadi Asyrafi616da772019-06-27 11:34:03 +0800734 switch (smc_fid) {
735 case SIP_SVC_UID:
736 /* Return UID to the caller */
737 SMC_UUID_RET(handle, intl_svc_uid);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800738
Hadi Asyrafi616da772019-06-27 11:34:03 +0800739 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800740 status = intel_mailbox_fpga_config_isdone();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800741 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800742
Hadi Asyrafi616da772019-06-27 11:34:03 +0800743 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
744 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
745 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
746 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
747 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800748
Hadi Asyrafi616da772019-06-27 11:34:03 +0800749 case INTEL_SIP_SMC_FPGA_CONFIG_START:
750 status = intel_fpga_config_start(x1);
751 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800752
Hadi Asyrafi616da772019-06-27 11:34:03 +0800753 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
754 status = intel_fpga_config_write(x1, x2);
755 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800756
Hadi Asyrafi616da772019-06-27 11:34:03 +0800757 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
758 status = intel_fpga_config_completed_write(completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800759 &retval, &rcv_id);
760 switch (retval) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800761 case 1:
762 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
763 completed_addr[0], 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800764
Hadi Asyrafi616da772019-06-27 11:34:03 +0800765 case 2:
766 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
767 completed_addr[0],
768 completed_addr[1], 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800769
Hadi Asyrafi616da772019-06-27 11:34:03 +0800770 case 3:
771 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
772 completed_addr[0],
773 completed_addr[1],
774 completed_addr[2]);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800775
Hadi Asyrafi616da772019-06-27 11:34:03 +0800776 case 0:
777 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800778
Hadi Asyrafi616da772019-06-27 11:34:03 +0800779 default:
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800780 mailbox_clear_response();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800781 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
782 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800783
784 case INTEL_SIP_SMC_REG_READ:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800785 status = intel_secure_reg_read(x1, &retval);
786 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800787
788 case INTEL_SIP_SMC_REG_WRITE:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800789 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
790 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800791
792 case INTEL_SIP_SMC_REG_UPDATE:
793 status = intel_secure_reg_update(x1, (uint32_t)x2,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800794 (uint32_t)x3, &retval);
795 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800796
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800797 case INTEL_SIP_SMC_RSU_STATUS:
798 status = intel_rsu_status(rsu_respbuf,
799 ARRAY_SIZE(rsu_respbuf));
800 if (status) {
801 SMC_RET1(handle, status);
802 } else {
803 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
804 rsu_respbuf[2], rsu_respbuf[3]);
805 }
806
807 case INTEL_SIP_SMC_RSU_UPDATE:
808 status = intel_rsu_update(x1);
809 SMC_RET1(handle, status);
810
811 case INTEL_SIP_SMC_RSU_NOTIFY:
812 status = intel_rsu_notify(x1);
813 SMC_RET1(handle, status);
814
815 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
816 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800817 ARRAY_SIZE(rsu_respbuf), &retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800818 if (status) {
819 SMC_RET1(handle, status);
820 } else {
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800821 SMC_RET2(handle, status, retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800822 }
823
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +0800824 case INTEL_SIP_SMC_RSU_DCMF_VERSION:
825 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
826 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
827 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
828
829 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
830 status = intel_rsu_copy_dcmf_version(x1, x2);
831 SMC_RET1(handle, status);
832
Sieu Mun Tange6d5de92022-04-28 22:21:01 +0800833 case INTEL_SIP_SMC_RSU_DCMF_STATUS:
834 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
835 ((uint64_t)rsu_dcmf_stat[3] << 48) |
836 ((uint64_t)rsu_dcmf_stat[2] << 32) |
837 ((uint64_t)rsu_dcmf_stat[1] << 16) |
838 rsu_dcmf_stat[0]);
839
840 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
841 status = intel_rsu_copy_dcmf_status(x1);
842 SMC_RET1(handle, status);
843
Chee Hong Ang681631b2020-07-01 14:22:25 +0800844 case INTEL_SIP_SMC_RSU_MAX_RETRY:
845 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
846
847 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
848 rsu_max_retry = x1;
849 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
850
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800851 case INTEL_SIP_SMC_ECC_DBE:
852 status = intel_ecc_dbe_notification(x1);
853 SMC_RET1(handle, status);
854
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800855 case INTEL_SIP_SMC_SERVICE_COMPLETED:
856 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
857 &len_in_resp, &mbox_error);
858 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
859
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800860 case INTEL_SIP_SMC_FIRMWARE_VERSION:
861 status = intel_smc_fw_version(&retval);
Sieu Mun Tangbfda95a2022-04-27 18:54:10 +0800862 SMC_RET2(handle, status, retval);
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800863
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800864 case INTEL_SIP_SMC_MBOX_SEND_CMD:
865 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
866 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800867 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
868 &mbox_status, &len_in_resp);
Sieu Mun Tangf02f0cb2022-02-19 20:36:41 +0800869 SMC_RET3(handle, status, mbox_status, len_in_resp);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800870
Sieu Mun Tang2b8e0052022-04-27 18:57:29 +0800871 case INTEL_SIP_SMC_GET_USERCODE:
872 status = intel_smc_get_usercode(&retval);
873 SMC_RET2(handle, status, retval);
874
Sieu Mun Tang128d2a72022-05-11 09:49:25 +0800875 case INTEL_SIP_SMC_FCS_CRYPTION:
876 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
877
878 if (x1 == FCS_MODE_DECRYPT) {
879 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
880 } else if (x1 == FCS_MODE_ENCRYPT) {
881 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
882 } else {
883 status = INTEL_SIP_SMC_STATUS_REJECTED;
884 }
885
886 SMC_RET3(handle, status, x4, x5);
887
Sieu Mun Tang22322fb2022-05-09 16:05:58 +0800888 case INTEL_SIP_SMC_FCS_CRYPTION_EXT:
889 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
890 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
891 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
892
893 if (x3 == FCS_MODE_DECRYPT) {
894 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
895 (uint32_t *) &x7, &mbox_error);
896 } else if (x3 == FCS_MODE_ENCRYPT) {
897 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
898 (uint32_t *) &x7, &mbox_error);
899 } else {
900 status = INTEL_SIP_SMC_STATUS_REJECTED;
901 }
902
903 SMC_RET4(handle, status, mbox_error, x6, x7);
904
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800905 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER:
906 status = intel_fcs_random_number_gen(x1, &retval64,
907 &mbox_error);
908 SMC_RET4(handle, status, mbox_error, x1, retval64);
909
Sieu Mun Tange7a037f2022-05-10 17:18:19 +0800910 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT:
911 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
912 &send_id);
913 SMC_RET1(handle, status);
914
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800915 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
916 status = intel_fcs_send_cert(x1, x2, &send_id);
917 SMC_RET1(handle, status);
918
919 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
920 status = intel_fcs_get_provision_data(&send_id);
921 SMC_RET1(handle, status);
922
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +0800923 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
924 status = intel_fcs_cntr_set_preauth(x1, x2, x3,
925 &mbox_error);
926 SMC_RET2(handle, status, mbox_error);
927
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800928 case INTEL_SIP_SMC_HPS_SET_BRIDGES:
929 status = intel_hps_set_bridges(x1, x2);
930 SMC_RET1(handle, status);
931
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800932 case INTEL_SIP_SMC_HWMON_READTEMP:
933 status = intel_hwmon_readtemp(x1, &retval);
934 SMC_RET2(handle, status, retval);
935
936 case INTEL_SIP_SMC_HWMON_READVOLT:
937 status = intel_hwmon_readvolt(x1, &retval);
938 SMC_RET2(handle, status, retval);
939
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800940 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN:
941 status = intel_fcs_sigma_teardown(x1, &mbox_error);
942 SMC_RET2(handle, status, mbox_error);
943
944 case INTEL_SIP_SMC_FCS_CHIP_ID:
945 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
946 SMC_RET4(handle, status, mbox_error, retval, retval2);
947
948 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY:
949 status = intel_fcs_attestation_subkey(x1, x2, x3,
950 (uint32_t *) &x4, &mbox_error);
951 SMC_RET4(handle, status, mbox_error, x3, x4);
952
953 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS:
954 status = intel_fcs_get_measurement(x1, x2, x3,
955 (uint32_t *) &x4, &mbox_error);
956 SMC_RET4(handle, status, mbox_error, x3, x4);
957
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800958 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
959 status = intel_fcs_get_attestation_cert(x1, x2,
960 (uint32_t *) &x3, &mbox_error);
961 SMC_RET4(handle, status, mbox_error, x2, x3);
962
963 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
964 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
965 SMC_RET2(handle, status, mbox_error);
966
Sieu Mun Tang16754e12022-05-09 12:08:42 +0800967 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
968 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
969 SMC_RET3(handle, status, mbox_error, retval);
970
971 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION:
972 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
973 SMC_RET2(handle, status, mbox_error);
974
Sieu Mun Tangfb1f6e92022-05-09 14:16:14 +0800975 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY:
976 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
977 SMC_RET1(handle, status);
978
979 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY:
980 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
981 (uint32_t *) &x4, &mbox_error);
982 SMC_RET4(handle, status, mbox_error, x3, x4);
983
984 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY:
985 status = intel_fcs_remove_crypto_service_key(x1, x2,
986 &mbox_error);
987 SMC_RET2(handle, status, mbox_error);
988
989 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO:
990 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
991 (uint32_t *) &x4, &mbox_error);
992 SMC_RET4(handle, status, mbox_error, x3, x4);
993
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800994 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT:
995 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
996 status = intel_fcs_get_digest_init(x1, x2, x3,
997 x4, x5, &mbox_error);
998 SMC_RET2(handle, status, mbox_error);
999
Sieu Mun Tang527df9f2022-04-28 16:28:48 +08001000 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
1001 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1002 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1003 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1004 x4, x5, (uint32_t *) &x6, false,
1005 &mbox_error);
1006 SMC_RET4(handle, status, mbox_error, x5, x6);
1007
Sieu Mun Tangd907cc32022-05-10 17:24:05 +08001008 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
1009 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1010 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang527df9f2022-04-28 16:28:48 +08001011 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1012 x4, x5, (uint32_t *) &x6, true,
1013 &mbox_error);
Sieu Mun Tangd907cc32022-05-10 17:24:05 +08001014 SMC_RET4(handle, status, mbox_error, x5, x6);
1015
Sieu Mun Tangbd8da632022-09-28 15:58:28 +08001016 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
1017 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1018 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1019 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1020 x4, x5, (uint32_t *) &x6, false,
1021 &mbox_error, &send_id);
1022 SMC_RET4(handle, status, mbox_error, x5, x6);
1023
1024 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE:
1025 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1026 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1027 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1028 x4, x5, (uint32_t *) &x6, true,
1029 &mbox_error, &send_id);
1030 SMC_RET4(handle, status, mbox_error, x5, x6);
1031
Sieu Mun Tang583149a2022-05-10 17:27:12 +08001032 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
1033 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1034 status = intel_fcs_mac_verify_init(x1, x2, x3,
1035 x4, x5, &mbox_error);
1036 SMC_RET2(handle, status, mbox_error);
1037
Sieu Mun Tang527df9f2022-04-28 16:28:48 +08001038 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE:
1039 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1040 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1041 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1042 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1043 x4, x5, (uint32_t *) &x6, x7,
1044 false, &mbox_error);
1045 SMC_RET4(handle, status, mbox_error, x5, x6);
1046
Sieu Mun Tang583149a2022-05-10 17:27:12 +08001047 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
1048 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1049 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1050 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
Sieu Mun Tang527df9f2022-04-28 16:28:48 +08001051 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1052 x4, x5, (uint32_t *) &x6, x7,
1053 true, &mbox_error);
Sieu Mun Tang583149a2022-05-10 17:27:12 +08001054 SMC_RET4(handle, status, mbox_error, x5, x6);
1055
Sieu Mun Tangbd8da632022-09-28 15:58:28 +08001056 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
1057 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1058 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1059 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1060 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1061 x4, x5, (uint32_t *) &x6, x7,
1062 false, &mbox_error, &send_id);
1063 SMC_RET4(handle, status, mbox_error, x5, x6);
1064
1065 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE:
1066 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1067 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1068 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1069 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1070 x4, x5, (uint32_t *) &x6, x7,
1071 true, &mbox_error, &send_id);
1072 SMC_RET4(handle, status, mbox_error, x5, x6);
1073
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001074 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
1075 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1076 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
1077 x4, x5, &mbox_error);
1078 SMC_RET2(handle, status, mbox_error);
1079
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001080 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
1081 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1082 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1083 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1084 x3, x4, x5, (uint32_t *) &x6, false,
1085 &mbox_error);
1086 SMC_RET4(handle, status, mbox_error, x5, x6);
1087
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001088 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
1089 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1090 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001091 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1092 x3, x4, x5, (uint32_t *) &x6, true,
1093 &mbox_error);
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001094 SMC_RET4(handle, status, mbox_error, x5, x6);
1095
Sieu Mun Tangbd8da632022-09-28 15:58:28 +08001096 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
1097 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1098 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1099 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1100 x2, x3, x4, x5, (uint32_t *) &x6, false,
1101 &mbox_error, &send_id);
1102 SMC_RET4(handle, status, mbox_error, x5, x6);
1103
1104 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
1105 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1106 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1107 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1108 x2, x3, x4, x5, (uint32_t *) &x6, true,
1109 &mbox_error, &send_id);
1110 SMC_RET4(handle, status, mbox_error, x5, x6);
1111
Sieu Mun Tang8aa05ad2022-05-10 17:50:30 +08001112 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
1113 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1114 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
1115 x4, x5, &mbox_error);
1116 SMC_RET2(handle, status, mbox_error);
1117
1118 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
1119 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1120 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1121 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
1122 x4, x5, (uint32_t *) &x6, &mbox_error);
1123 SMC_RET4(handle, status, mbox_error, x5, x6);
1124
Sieu Mun Tang59357e82022-05-10 17:53:32 +08001125 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
1126 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1127 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1128 x4, x5, &mbox_error);
1129 SMC_RET2(handle, status, mbox_error);
1130
1131 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
1132 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1133 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1134 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1135 x4, x5, (uint32_t *) &x6, &mbox_error);
1136 SMC_RET4(handle, status, mbox_error, x5, x6);
1137
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001138 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
1139 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1140 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1141 x4, x5, &mbox_error);
1142 SMC_RET2(handle, status, mbox_error);
1143
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001144 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
1145 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1146 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1147 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1148 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1149 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1150 x7, false, &mbox_error);
1151 SMC_RET4(handle, status, mbox_error, x5, x6);
1152
Sieu Mun Tangbd8da632022-09-28 15:58:28 +08001153 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
1154 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1155 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1156 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1157 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1158 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1159 x7, false, &mbox_error, &send_id);
1160 SMC_RET4(handle, status, mbox_error, x5, x6);
1161
1162 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
1163 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1164 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1165 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1166 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1167 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1168 x7, true, &mbox_error, &send_id);
1169 SMC_RET4(handle, status, mbox_error, x5, x6);
1170
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001171 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
1172 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1173 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1174 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001175 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1176 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1177 x7, true, &mbox_error);
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001178 SMC_RET4(handle, status, mbox_error, x5, x6);
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001179
Sieu Mun Tange2f3ede2022-05-10 17:36:32 +08001180 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
1181 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1182 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1183 x4, x5, &mbox_error);
1184 SMC_RET2(handle, status, mbox_error);
1185
1186 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
1187 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1188 (uint32_t *) &x4, &mbox_error);
1189 SMC_RET4(handle, status, mbox_error, x3, x4);
1190
Sieu Mun Tang0675c222022-05-10 17:48:11 +08001191 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
1192 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1193 status = intel_fcs_ecdh_request_init(x1, x2, x3,
1194 x4, x5, &mbox_error);
1195 SMC_RET2(handle, status, mbox_error);
1196
1197 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
1198 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1199 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1200 status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1201 x4, x5, (uint32_t *) &x6, &mbox_error);
1202 SMC_RET4(handle, status, mbox_error, x5, x6);
1203
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001204 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT:
1205 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1206 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1207 &mbox_error);
1208 SMC_RET2(handle, status, mbox_error);
1209
Sieu Mun Tang9bea8152022-04-28 16:15:54 +08001210 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
1211 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1212 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1213 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1214 x5, x6, false, &send_id);
1215 SMC_RET1(handle, status);
1216
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001217 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
1218 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1219 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang9bea8152022-04-28 16:15:54 +08001220 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1221 x5, x6, true, &send_id);
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001222 SMC_RET1(handle, status);
1223
Sieu Mun Tanga34b8812022-03-17 03:11:55 +08001224 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
1225 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
1226 &mbox_error);
1227 SMC_RET4(handle, status, mbox_error, x1, retval64);
1228
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +08001229 case INTEL_SIP_SMC_SVC_VERSION:
1230 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
1231 SIP_SVC_VERSION_MAJOR,
1232 SIP_SVC_VERSION_MINOR);
1233
Jit Loon Lim2bee1732023-05-17 12:26:11 +08001234 case INTEL_SIP_SMC_SEU_ERR_STATUS:
1235 status = intel_sdm_seu_err_read(seu_respbuf,
1236 ARRAY_SIZE(seu_respbuf));
1237 if (status) {
1238 SMC_RET1(handle, status);
1239 } else {
1240 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
1241 }
1242
Jit Loon Limb46c8692023-09-20 14:00:41 +08001243 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR:
1244 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
1245 SMC_RET1(handle, status);
1246
Hadi Asyrafi616da772019-06-27 11:34:03 +08001247 default:
1248 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1249 cookie, handle, flags);
1250 }
1251}
1252
Sieu Mun Tang044ed482022-05-11 10:45:19 +08001253uintptr_t sip_smc_handler(uint32_t smc_fid,
1254 u_register_t x1,
1255 u_register_t x2,
1256 u_register_t x3,
1257 u_register_t x4,
1258 void *cookie,
1259 void *handle,
1260 u_register_t flags)
1261{
1262 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK;
1263
1264 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN &&
1265 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
1266 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
1267 cookie, handle, flags);
1268 } else {
1269 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
1270 cookie, handle, flags);
1271 }
1272}
1273
Hadi Asyrafi616da772019-06-27 11:34:03 +08001274DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +08001275 socfpga_sip_svc,
Hadi Asyrafi616da772019-06-27 11:34:03 +08001276 OEN_SIP_START,
1277 OEN_SIP_END,
1278 SMC_TYPE_FAST,
1279 NULL,
1280 sip_smc_handler
1281);
1282
1283DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +08001284 socfpga_sip_svc_std,
Hadi Asyrafi616da772019-06-27 11:34:03 +08001285 OEN_SIP_START,
1286 OEN_SIP_END,
1287 SMC_TYPE_YIELD,
1288 NULL,
1289 sip_smc_handler
1290);