feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 1a18ee1..c6530cf 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -335,6 +335,7 @@
return 0;
#endif
+#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
switch (reg_addr) {
case(0xF8011100): /* ECCCTRL1 */
case(0xF8011104): /* ECCCTRL2 */
@@ -386,7 +387,41 @@
case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
return 0;
+#else
+ switch (reg_addr) {
+
+ case(0xF8011104): /* ECCCTRL2 */
+ case(0xFFD12028): /* SDMMCGRP_CTRL */
+ case(0xFFD120C4): /* NOC_IDLEREQ_SET */
+ case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
+ case(0xFFD120D0): /* NOC_IDLEACK */
+
+ case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */
+ case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */
+ case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */
+ case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */
+ case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */
+ case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */
+ case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */
+ case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */
+
+ case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
+ case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
+ case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */
+ case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */
+ case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */
+ case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */
+ case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */
+ case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */
+ case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */
+ case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */
+ case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */
+ case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
+ case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
+ case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
+ return 0;
+#endif
default:
break;
}