Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <common/debug.h> |
| 9 | #include <common/runtime_svc.h> |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 10 | #include <lib/mmio.h> |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 11 | #include <tools_share/uuid.h> |
| 12 | |
Hadi Asyrafi | 6f8a2b2 | 2019-10-23 18:34:14 +0800 | [diff] [blame] | 13 | #include "socfpga_mailbox.h" |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 14 | #include "socfpga_reset_manager.h" |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 15 | #include "socfpga_sip_svc.h" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 16 | |
| 17 | /* Number of SiP Calls implemented */ |
| 18 | #define SIP_NUM_CALLS 0x3 |
| 19 | |
| 20 | /* Total buffer the driver can hold */ |
| 21 | #define FPGA_CONFIG_BUFFER_SIZE 4 |
| 22 | |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 23 | static int current_block; |
| 24 | static int read_block; |
| 25 | static int current_buffer; |
| 26 | static int send_id; |
| 27 | static int rcv_id; |
| 28 | static int max_blocks; |
| 29 | static uint32_t bytes_per_block; |
| 30 | static uint32_t blocks_submitted; |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 31 | static int is_partial_reconfig; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 32 | |
| 33 | struct fpga_config_info { |
| 34 | uint32_t addr; |
| 35 | int size; |
| 36 | int size_written; |
| 37 | uint32_t write_requested; |
| 38 | int subblocks_sent; |
| 39 | int block_number; |
| 40 | }; |
| 41 | |
| 42 | /* SiP Service UUID */ |
| 43 | DEFINE_SVC_UUID2(intl_svc_uid, |
| 44 | 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, |
| 45 | 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); |
| 46 | |
Hadi Asyrafi | cee6aa9 | 2019-12-17 15:25:04 +0800 | [diff] [blame] | 47 | static uint64_t socfpga_sip_handler(uint32_t smc_fid, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 48 | uint64_t x1, |
| 49 | uint64_t x2, |
| 50 | uint64_t x3, |
| 51 | uint64_t x4, |
| 52 | void *cookie, |
| 53 | void *handle, |
| 54 | uint64_t flags) |
| 55 | { |
| 56 | ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); |
| 57 | SMC_RET1(handle, SMC_UNK); |
| 58 | } |
| 59 | |
| 60 | struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; |
| 61 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 62 | static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 63 | { |
| 64 | uint32_t args[3]; |
| 65 | |
| 66 | while (max_blocks > 0 && buffer->size > buffer->size_written) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 67 | args[0] = (1<<8); |
| 68 | args[1] = buffer->addr + buffer->size_written; |
| 69 | if (buffer->size - buffer->size_written <= bytes_per_block) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 70 | args[2] = buffer->size - buffer->size_written; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 71 | current_buffer++; |
| 72 | current_buffer %= FPGA_CONFIG_BUFFER_SIZE; |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 73 | } else |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 74 | args[2] = bytes_per_block; |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 75 | |
| 76 | buffer->size_written += args[2]; |
| 77 | mailbox_send_cmd_async( |
| 78 | send_id++ % MBOX_MAX_JOB_ID, |
| 79 | MBOX_RECONFIG_DATA, |
| 80 | args, 3, 0); |
| 81 | |
| 82 | buffer->subblocks_sent++; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 83 | max_blocks--; |
| 84 | } |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 85 | |
| 86 | return !max_blocks; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | static int intel_fpga_sdm_write_all(void) |
| 90 | { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 91 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) |
| 92 | if (intel_fpga_sdm_write_buffer( |
| 93 | &fpga_config_buffers[current_buffer])) |
| 94 | break; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 95 | return 0; |
| 96 | } |
| 97 | |
Hadi Asyrafi | 0c6dae2 | 2019-12-17 23:33:39 +0800 | [diff] [blame] | 98 | static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 99 | { |
Hadi Asyrafi | 0c6dae2 | 2019-12-17 23:33:39 +0800 | [diff] [blame] | 100 | uint32_t ret; |
| 101 | |
| 102 | if (query_type == 1) |
| 103 | ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); |
| 104 | else |
| 105 | ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 106 | |
| 107 | if (ret) { |
| 108 | if (ret == MBOX_CFGSTAT_STATE_CONFIG) |
| 109 | return INTEL_SIP_SMC_STATUS_BUSY; |
| 110 | else |
| 111 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 112 | } |
| 113 | |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 114 | if (query_type != 1) { |
| 115 | /* full reconfiguration */ |
| 116 | if (!is_partial_reconfig) |
| 117 | socfpga_bridges_enable(); /* Enable bridge */ |
| 118 | } |
| 119 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 120 | return INTEL_SIP_SMC_STATUS_OK; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) |
| 124 | { |
| 125 | int i; |
| 126 | |
| 127 | for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
| 128 | if (fpga_config_buffers[i].block_number == current_block) { |
| 129 | fpga_config_buffers[i].subblocks_sent--; |
| 130 | if (fpga_config_buffers[i].subblocks_sent == 0 |
| 131 | && fpga_config_buffers[i].size <= |
| 132 | fpga_config_buffers[i].size_written) { |
| 133 | fpga_config_buffers[i].write_requested = 0; |
| 134 | current_block++; |
| 135 | *buffer_addr_completed = |
| 136 | fpga_config_buffers[i].addr; |
| 137 | return 0; |
| 138 | } |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | return -1; |
| 143 | } |
| 144 | |
Hadi Asyrafi | cee6aa9 | 2019-12-17 15:25:04 +0800 | [diff] [blame] | 145 | static int intel_fpga_config_completed_write(uint32_t *completed_addr, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 146 | uint32_t *count) |
| 147 | { |
| 148 | uint32_t status = INTEL_SIP_SMC_STATUS_OK; |
| 149 | *count = 0; |
| 150 | int resp_len = 0; |
| 151 | uint32_t resp[5]; |
| 152 | int all_completed = 1; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 153 | |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 154 | while (*count < 3) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 155 | |
Hadi Asyrafi | 9dfc047 | 2019-11-12 16:39:46 +0800 | [diff] [blame] | 156 | resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, |
| 157 | resp, sizeof(resp) / sizeof(resp[0])); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 158 | |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 159 | if (resp_len < 0) |
| 160 | break; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 161 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 162 | max_blocks++; |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 163 | rcv_id++; |
| 164 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 165 | if (mark_last_buffer_xfer_completed( |
| 166 | &completed_addr[*count]) == 0) |
| 167 | *count = *count + 1; |
| 168 | else |
| 169 | break; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | if (*count <= 0) { |
| 173 | if (resp_len != MBOX_NO_RESPONSE && |
| 174 | resp_len != MBOX_TIMEOUT && resp_len != 0) { |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 175 | mailbox_clear_response(); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 176 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 177 | } |
| 178 | |
| 179 | *count = 0; |
| 180 | } |
| 181 | |
| 182 | intel_fpga_sdm_write_all(); |
| 183 | |
| 184 | if (*count > 0) |
| 185 | status = INTEL_SIP_SMC_STATUS_OK; |
| 186 | else if (*count == 0) |
| 187 | status = INTEL_SIP_SMC_STATUS_BUSY; |
| 188 | |
| 189 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
| 190 | if (fpga_config_buffers[i].write_requested != 0) { |
| 191 | all_completed = 0; |
| 192 | break; |
| 193 | } |
| 194 | } |
| 195 | |
| 196 | if (all_completed == 1) |
| 197 | return INTEL_SIP_SMC_STATUS_OK; |
| 198 | |
| 199 | return status; |
| 200 | } |
| 201 | |
Hadi Asyrafi | cee6aa9 | 2019-12-17 15:25:04 +0800 | [diff] [blame] | 202 | static int intel_fpga_config_start(uint32_t config_type) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 203 | { |
| 204 | uint32_t response[3]; |
| 205 | int status = 0; |
| 206 | |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 207 | is_partial_reconfig = config_type; |
| 208 | |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 209 | mailbox_clear_response(); |
| 210 | |
Hadi Asyrafi | 9dfc047 | 2019-11-12 16:39:46 +0800 | [diff] [blame] | 211 | mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 212 | |
| 213 | status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, |
Hadi Asyrafi | 9dfc047 | 2019-11-12 16:39:46 +0800 | [diff] [blame] | 214 | response, sizeof(response) / sizeof(response[0])); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 215 | |
| 216 | if (status < 0) |
| 217 | return status; |
| 218 | |
| 219 | max_blocks = response[0]; |
| 220 | bytes_per_block = response[1]; |
| 221 | |
| 222 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
| 223 | fpga_config_buffers[i].size = 0; |
| 224 | fpga_config_buffers[i].size_written = 0; |
| 225 | fpga_config_buffers[i].addr = 0; |
| 226 | fpga_config_buffers[i].write_requested = 0; |
| 227 | fpga_config_buffers[i].block_number = 0; |
| 228 | fpga_config_buffers[i].subblocks_sent = 0; |
| 229 | } |
| 230 | |
| 231 | blocks_submitted = 0; |
| 232 | current_block = 0; |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 233 | read_block = 0; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 234 | current_buffer = 0; |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 235 | send_id = 0; |
| 236 | rcv_id = 0; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 237 | |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 238 | /* full reconfiguration */ |
| 239 | if (!is_partial_reconfig) { |
| 240 | /* Disable bridge */ |
| 241 | socfpga_bridges_disable(); |
| 242 | } |
| 243 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 244 | return 0; |
| 245 | } |
| 246 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 247 | static bool is_fpga_config_buffer_full(void) |
| 248 | { |
| 249 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) |
| 250 | if (!fpga_config_buffers[i].write_requested) |
| 251 | return false; |
| 252 | return true; |
| 253 | } |
| 254 | |
| 255 | static bool is_address_in_ddr_range(uint64_t addr) |
| 256 | { |
| 257 | if (addr >= DRAM_BASE && addr <= DRAM_BASE + DRAM_SIZE) |
| 258 | return true; |
| 259 | |
| 260 | return false; |
| 261 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 262 | |
Hadi Asyrafi | cee6aa9 | 2019-12-17 15:25:04 +0800 | [diff] [blame] | 263 | static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 264 | { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 265 | int i; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 266 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 267 | intel_fpga_sdm_write_all(); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 268 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 269 | if (!is_address_in_ddr_range(mem) || |
| 270 | !is_address_in_ddr_range(mem + size) || |
| 271 | is_fpga_config_buffer_full()) |
| 272 | return INTEL_SIP_SMC_STATUS_REJECTED; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 273 | |
| 274 | for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 275 | int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; |
| 276 | |
| 277 | if (!fpga_config_buffers[j].write_requested) { |
| 278 | fpga_config_buffers[j].addr = mem; |
| 279 | fpga_config_buffers[j].size = size; |
| 280 | fpga_config_buffers[j].size_written = 0; |
| 281 | fpga_config_buffers[j].write_requested = 1; |
| 282 | fpga_config_buffers[j].block_number = |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 283 | blocks_submitted++; |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 284 | fpga_config_buffers[j].subblocks_sent = 0; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 285 | break; |
| 286 | } |
| 287 | } |
| 288 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 289 | if (is_fpga_config_buffer_full()) |
| 290 | return INTEL_SIP_SMC_STATUS_BUSY; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 291 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 292 | return INTEL_SIP_SMC_STATUS_OK; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 293 | } |
| 294 | |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 295 | static int is_out_of_sec_range(uint64_t reg_addr) |
| 296 | { |
| 297 | switch (reg_addr) { |
| 298 | case(0xF8011100): /* ECCCTRL1 */ |
| 299 | case(0xF8011104): /* ECCCTRL2 */ |
| 300 | case(0xF8011110): /* ERRINTEN */ |
| 301 | case(0xF8011114): /* ERRINTENS */ |
| 302 | case(0xF8011118): /* ERRINTENR */ |
| 303 | case(0xF801111C): /* INTMODE */ |
| 304 | case(0xF8011120): /* INTSTAT */ |
| 305 | case(0xF8011124): /* DIAGINTTEST */ |
| 306 | case(0xF801112C): /* DERRADDRA */ |
| 307 | case(0xFFD12028): /* SDMMCGRP_CTRL */ |
| 308 | case(0xFFD12044): /* EMAC0 */ |
| 309 | case(0xFFD12048): /* EMAC1 */ |
| 310 | case(0xFFD1204C): /* EMAC2 */ |
| 311 | case(0xFFD12090): /* ECC_INT_MASK_VALUE */ |
| 312 | case(0xFFD12094): /* ECC_INT_MASK_SET */ |
| 313 | case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ |
| 314 | case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ |
| 315 | case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ |
| 316 | case(0xFFD120C0): /* NOC_TIMEOUT */ |
| 317 | case(0xFFD120C4): /* NOC_IDLEREQ_SET */ |
| 318 | case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ |
| 319 | case(0xFFD120D0): /* NOC_IDLEACK */ |
| 320 | case(0xFFD120D4): /* NOC_IDLESTATUS */ |
| 321 | case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ |
| 322 | case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ |
| 323 | case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ |
| 324 | case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ |
| 325 | return 0; |
| 326 | |
| 327 | default: |
| 328 | break; |
| 329 | } |
| 330 | |
| 331 | return -1; |
| 332 | } |
| 333 | |
| 334 | /* Secure register access */ |
| 335 | uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) |
| 336 | { |
| 337 | if (is_out_of_sec_range(reg_addr)) |
| 338 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 339 | |
| 340 | *retval = mmio_read_32(reg_addr); |
| 341 | |
| 342 | return INTEL_SIP_SMC_STATUS_OK; |
| 343 | } |
| 344 | |
| 345 | uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, |
| 346 | uint32_t *retval) |
| 347 | { |
| 348 | if (is_out_of_sec_range(reg_addr)) |
| 349 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 350 | |
| 351 | mmio_write_32(reg_addr, val); |
| 352 | |
| 353 | return intel_secure_reg_read(reg_addr, retval); |
| 354 | } |
| 355 | |
| 356 | uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, |
| 357 | uint32_t val, uint32_t *retval) |
| 358 | { |
| 359 | if (!intel_secure_reg_read(reg_addr, retval)) { |
| 360 | *retval &= ~mask; |
| 361 | *retval |= val; |
| 362 | return intel_secure_reg_write(reg_addr, *retval, retval); |
| 363 | } |
| 364 | |
| 365 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 366 | } |
| 367 | |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame^] | 368 | /* Intel Remote System Update (RSU) services */ |
| 369 | uint64_t intel_rsu_update_address; |
| 370 | |
| 371 | static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz) |
| 372 | { |
| 373 | if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) |
| 374 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 375 | |
| 376 | return INTEL_SIP_SMC_STATUS_OK; |
| 377 | } |
| 378 | |
| 379 | static uint32_t intel_rsu_update(uint64_t update_address) |
| 380 | { |
| 381 | intel_rsu_update_address = update_address; |
| 382 | return INTEL_SIP_SMC_STATUS_OK; |
| 383 | } |
| 384 | |
| 385 | static uint32_t intel_rsu_notify(uint64_t execution_stage) |
| 386 | { |
| 387 | if (mailbox_hps_stage_notify((uint32_t)execution_stage) < 0) |
| 388 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 389 | |
| 390 | return INTEL_SIP_SMC_STATUS_OK; |
| 391 | } |
| 392 | |
| 393 | static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, |
| 394 | uint32_t *ret_stat) |
| 395 | { |
| 396 | if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) |
| 397 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 398 | |
| 399 | *ret_stat = respbuf[8]; |
| 400 | return INTEL_SIP_SMC_STATUS_OK; |
| 401 | } |
| 402 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 403 | /* |
| 404 | * This function is responsible for handling all SiP calls from the NS world |
| 405 | */ |
| 406 | |
| 407 | uintptr_t sip_smc_handler(uint32_t smc_fid, |
| 408 | u_register_t x1, |
| 409 | u_register_t x2, |
| 410 | u_register_t x3, |
| 411 | u_register_t x4, |
| 412 | void *cookie, |
| 413 | void *handle, |
| 414 | u_register_t flags) |
| 415 | { |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 416 | uint32_t val = 0; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 417 | uint32_t status = INTEL_SIP_SMC_STATUS_OK; |
| 418 | uint32_t completed_addr[3]; |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame^] | 419 | uint64_t rsu_respbuf[9]; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 420 | uint32_t count = 0; |
| 421 | |
| 422 | switch (smc_fid) { |
| 423 | case SIP_SVC_UID: |
| 424 | /* Return UID to the caller */ |
| 425 | SMC_UUID_RET(handle, intl_svc_uid); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 426 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 427 | case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: |
Hadi Asyrafi | 0c6dae2 | 2019-12-17 23:33:39 +0800 | [diff] [blame] | 428 | status = intel_mailbox_fpga_config_isdone(x1); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 429 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 430 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 431 | case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: |
| 432 | SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, |
| 433 | INTEL_SIP_SMC_FPGA_CONFIG_ADDR, |
| 434 | INTEL_SIP_SMC_FPGA_CONFIG_SIZE - |
| 435 | INTEL_SIP_SMC_FPGA_CONFIG_ADDR); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 436 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 437 | case INTEL_SIP_SMC_FPGA_CONFIG_START: |
| 438 | status = intel_fpga_config_start(x1); |
| 439 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 440 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 441 | case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: |
| 442 | status = intel_fpga_config_write(x1, x2); |
| 443 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 444 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 445 | case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: |
| 446 | status = intel_fpga_config_completed_write(completed_addr, |
| 447 | &count); |
| 448 | switch (count) { |
| 449 | case 1: |
| 450 | SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, |
| 451 | completed_addr[0], 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 452 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 453 | case 2: |
| 454 | SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, |
| 455 | completed_addr[0], |
| 456 | completed_addr[1], 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 457 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 458 | case 3: |
| 459 | SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, |
| 460 | completed_addr[0], |
| 461 | completed_addr[1], |
| 462 | completed_addr[2]); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 463 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 464 | case 0: |
| 465 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 466 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 467 | default: |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 468 | mailbox_clear_response(); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 469 | SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); |
| 470 | } |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 471 | |
| 472 | case INTEL_SIP_SMC_REG_READ: |
| 473 | status = intel_secure_reg_read(x1, &val); |
| 474 | SMC_RET3(handle, status, val, x1); |
| 475 | |
| 476 | case INTEL_SIP_SMC_REG_WRITE: |
| 477 | status = intel_secure_reg_write(x1, (uint32_t)x2, &val); |
| 478 | SMC_RET3(handle, status, val, x1); |
| 479 | |
| 480 | case INTEL_SIP_SMC_REG_UPDATE: |
| 481 | status = intel_secure_reg_update(x1, (uint32_t)x2, |
| 482 | (uint32_t)x3, &val); |
| 483 | SMC_RET3(handle, status, val, x1); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 484 | |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame^] | 485 | case INTEL_SIP_SMC_RSU_STATUS: |
| 486 | status = intel_rsu_status(rsu_respbuf, |
| 487 | ARRAY_SIZE(rsu_respbuf)); |
| 488 | if (status) { |
| 489 | SMC_RET1(handle, status); |
| 490 | } else { |
| 491 | SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], |
| 492 | rsu_respbuf[2], rsu_respbuf[3]); |
| 493 | } |
| 494 | |
| 495 | case INTEL_SIP_SMC_RSU_UPDATE: |
| 496 | status = intel_rsu_update(x1); |
| 497 | SMC_RET1(handle, status); |
| 498 | |
| 499 | case INTEL_SIP_SMC_RSU_NOTIFY: |
| 500 | status = intel_rsu_notify(x1); |
| 501 | SMC_RET1(handle, status); |
| 502 | |
| 503 | case INTEL_SIP_SMC_RSU_RETRY_COUNTER: |
| 504 | status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, |
| 505 | ARRAY_SIZE(rsu_respbuf), &val); |
| 506 | if (status) { |
| 507 | SMC_RET1(handle, status); |
| 508 | } else { |
| 509 | SMC_RET2(handle, status, val); |
| 510 | } |
| 511 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 512 | default: |
| 513 | return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, |
| 514 | cookie, handle, flags); |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | DECLARE_RT_SVC( |
Hadi Asyrafi | 4d9f395 | 2019-10-23 17:35:32 +0800 | [diff] [blame] | 519 | socfpga_sip_svc, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 520 | OEN_SIP_START, |
| 521 | OEN_SIP_END, |
| 522 | SMC_TYPE_FAST, |
| 523 | NULL, |
| 524 | sip_smc_handler |
| 525 | ); |
| 526 | |
| 527 | DECLARE_RT_SVC( |
Hadi Asyrafi | 4d9f395 | 2019-10-23 17:35:32 +0800 | [diff] [blame] | 528 | socfpga_sip_svc_std, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 529 | OEN_SIP_START, |
| 530 | OEN_SIP_END, |
| 531 | SMC_TYPE_YIELD, |
| 532 | NULL, |
| 533 | sip_smc_handler |
| 534 | ); |