blob: f079349f3744b671844c8d03bd7f641fa76ddadf [file] [log] [blame]
Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
Abdul Halim, Muhammad Hadi Asyrafi461f5442020-07-03 13:22:09 +08002 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/debug.h>
9#include <common/runtime_svc.h>
Hadi Asyrafi67942302019-10-22 13:28:51 +080010#include <lib/mmio.h>
Hadi Asyrafi616da772019-06-27 11:34:03 +080011#include <tools_share/uuid.h>
12
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080013#include "socfpga_fcs.h"
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080014#include "socfpga_mailbox.h"
Hadi Asyrafi36a9f302019-12-24 10:42:52 +080015#include "socfpga_reset_manager.h"
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080016#include "socfpga_sip_svc.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080017
Hadi Asyrafi616da772019-06-27 11:34:03 +080018
19/* Total buffer the driver can hold */
20#define FPGA_CONFIG_BUFFER_SIZE 4
21
Sieu Mun Tangc3667602022-05-13 14:55:05 +080022static config_type request_type = NO_REQUEST;
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080023static int current_block, current_buffer;
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +080024static int read_block, max_blocks;
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080025static uint32_t send_id, rcv_id;
26static uint32_t bytes_per_block, blocks_submitted;
Sieu Mun Tang54064982022-04-28 22:40:58 +080027static bool bridge_disable;
Hadi Asyrafi616da772019-06-27 11:34:03 +080028
Sieu Mun Tange6d5de92022-04-28 22:21:01 +080029/* RSU static variables */
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +080030static uint32_t rsu_dcmf_ver[4] = {0};
Sieu Mun Tange6d5de92022-04-28 22:21:01 +080031static uint16_t rsu_dcmf_stat[4] = {0};
Sieu Mun Tangc3667602022-05-13 14:55:05 +080032static uint32_t rsu_max_retry;
Hadi Asyrafi616da772019-06-27 11:34:03 +080033
34/* SiP Service UUID */
35DEFINE_SVC_UUID2(intl_svc_uid,
36 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
37 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
38
Hadi Asyraficee6aa92019-12-17 15:25:04 +080039static uint64_t socfpga_sip_handler(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +080040 uint64_t x1,
41 uint64_t x2,
42 uint64_t x3,
43 uint64_t x4,
44 void *cookie,
45 void *handle,
46 uint64_t flags)
47{
48 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
49 SMC_RET1(handle, SMC_UNK);
50}
51
52struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
53
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080054static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
Hadi Asyrafi616da772019-06-27 11:34:03 +080055{
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +080056 uint32_t args[3];
Hadi Asyrafi616da772019-06-27 11:34:03 +080057
58 while (max_blocks > 0 && buffer->size > buffer->size_written) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080059 args[0] = (1<<8);
60 args[1] = buffer->addr + buffer->size_written;
61 if (buffer->size - buffer->size_written <= bytes_per_block) {
Hadi Asyrafi616da772019-06-27 11:34:03 +080062 args[2] = buffer->size - buffer->size_written;
Hadi Asyrafi616da772019-06-27 11:34:03 +080063 current_buffer++;
64 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080065 } else {
Hadi Asyrafi616da772019-06-27 11:34:03 +080066 args[2] = bytes_per_block;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080067 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080068
69 buffer->size_written += args[2];
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080070 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +080071 3U, CMD_INDIRECT);
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080072
73 buffer->subblocks_sent++;
Hadi Asyrafi616da772019-06-27 11:34:03 +080074 max_blocks--;
75 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080076
77 return !max_blocks;
Hadi Asyrafi616da772019-06-27 11:34:03 +080078}
79
80static int intel_fpga_sdm_write_all(void)
81{
Sieu Mun Tang28af1652022-05-09 10:48:53 +080082 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080083 if (intel_fpga_sdm_write_buffer(
Sieu Mun Tang28af1652022-05-09 10:48:53 +080084 &fpga_config_buffers[current_buffer])) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080085 break;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080086 }
87 }
Hadi Asyrafi616da772019-06-27 11:34:03 +080088 return 0;
89}
90
Sieu Mun Tangc3667602022-05-13 14:55:05 +080091static uint32_t intel_mailbox_fpga_config_isdone(void)
Hadi Asyrafi616da772019-06-27 11:34:03 +080092{
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +080093 uint32_t ret;
94
Sieu Mun Tangc3667602022-05-13 14:55:05 +080095 switch (request_type) {
96 case RECONFIGURATION:
97 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
98 true);
99 break;
100 case BITSTREAM_AUTH:
101 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
102 false);
103 break;
104 default:
105 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
106 false);
107 break;
Kris Chapline768dfa2021-06-25 11:31:52 +0100108 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800109
Abdul Halim, Muhammad Hadi Asyrafi959143d2020-12-29 16:49:23 +0800110 if (ret != 0U) {
Kris Chapline768dfa2021-06-25 11:31:52 +0100111 if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800112 return INTEL_SIP_SMC_STATUS_BUSY;
Kris Chapline768dfa2021-06-25 11:31:52 +0100113 } else {
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800114 request_type = NO_REQUEST;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800115 return INTEL_SIP_SMC_STATUS_ERROR;
Kris Chapline768dfa2021-06-25 11:31:52 +0100116 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800117 }
118
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800119 if (bridge_disable != 0U) {
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800120 socfpga_bridges_enable(~0); /* Enable bridge */
Sieu Mun Tang54064982022-04-28 22:40:58 +0800121 bridge_disable = false;
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800122 }
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800123 request_type = NO_REQUEST;
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800124
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800125 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800126}
127
128static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
129{
130 int i;
131
132 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
133 if (fpga_config_buffers[i].block_number == current_block) {
134 fpga_config_buffers[i].subblocks_sent--;
135 if (fpga_config_buffers[i].subblocks_sent == 0
136 && fpga_config_buffers[i].size <=
137 fpga_config_buffers[i].size_written) {
138 fpga_config_buffers[i].write_requested = 0;
139 current_block++;
140 *buffer_addr_completed =
141 fpga_config_buffers[i].addr;
142 return 0;
143 }
144 }
145 }
146
147 return -1;
148}
149
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800150static int intel_fpga_config_completed_write(uint32_t *completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800151 uint32_t *count, uint32_t *job_id)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800152{
Hadi Asyrafi616da772019-06-27 11:34:03 +0800153 uint32_t resp[5];
Sieu Mun Tang24682662022-02-19 21:49:48 +0800154 unsigned int resp_len = ARRAY_SIZE(resp);
155 int status = INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800156 int all_completed = 1;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800157 *count = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800158
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800159 while (*count < 3) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800160
Sieu Mun Tang24682662022-02-19 21:49:48 +0800161 status = mailbox_read_response(job_id,
162 resp, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800163
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800164 if (status < 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800165 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800166 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800167
Hadi Asyrafi616da772019-06-27 11:34:03 +0800168 max_blocks++;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800169
Hadi Asyrafi616da772019-06-27 11:34:03 +0800170 if (mark_last_buffer_xfer_completed(
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800171 &completed_addr[*count]) == 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800172 *count = *count + 1;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800173 } else {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800174 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800175 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800176 }
177
178 if (*count <= 0) {
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800179 if (status != MBOX_NO_RESPONSE &&
180 status != MBOX_TIMEOUT && resp_len != 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800181 mailbox_clear_response();
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800182 request_type = NO_REQUEST;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800183 return INTEL_SIP_SMC_STATUS_ERROR;
184 }
185
186 *count = 0;
187 }
188
189 intel_fpga_sdm_write_all();
190
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800191 if (*count > 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800192 status = INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800193 } else if (*count == 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800194 status = INTEL_SIP_SMC_STATUS_BUSY;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800195 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800196
197 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
198 if (fpga_config_buffers[i].write_requested != 0) {
199 all_completed = 0;
200 break;
201 }
202 }
203
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800204 if (all_completed == 1) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800205 return INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800206 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800207
208 return status;
209}
210
Sieu Mun Tang54064982022-04-28 22:40:58 +0800211static int intel_fpga_config_start(uint32_t flag)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800212{
Sieu Mun Tang24682662022-02-19 21:49:48 +0800213 uint32_t argument = 0x1;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800214 uint32_t response[3];
215 int status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800216 unsigned int size = 0;
217 unsigned int resp_len = ARRAY_SIZE(response);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800218
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800219 request_type = RECONFIGURATION;
220
Sieu Mun Tang54064982022-04-28 22:40:58 +0800221 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
222 bridge_disable = true;
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +0800223 }
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800224
Sieu Mun Tang54064982022-04-28 22:40:58 +0800225 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
226 size = 1;
227 bridge_disable = false;
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800228 request_type = BITSTREAM_AUTH;
Sieu Mun Tang54064982022-04-28 22:40:58 +0800229 }
230
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800231 mailbox_clear_response();
232
Sieu Mun Tang24682662022-02-19 21:49:48 +0800233 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
234 CMD_CASUAL, NULL, NULL);
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800235
Sieu Mun Tang24682662022-02-19 21:49:48 +0800236 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
237 CMD_CASUAL, response, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800238
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800239 if (status < 0) {
Sieu Mun Tang54064982022-04-28 22:40:58 +0800240 bridge_disable = false;
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800241 request_type = NO_REQUEST;
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800242 return INTEL_SIP_SMC_STATUS_ERROR;
243 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800244
245 max_blocks = response[0];
246 bytes_per_block = response[1];
247
248 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
249 fpga_config_buffers[i].size = 0;
250 fpga_config_buffers[i].size_written = 0;
251 fpga_config_buffers[i].addr = 0;
252 fpga_config_buffers[i].write_requested = 0;
253 fpga_config_buffers[i].block_number = 0;
254 fpga_config_buffers[i].subblocks_sent = 0;
255 }
256
257 blocks_submitted = 0;
258 current_block = 0;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800259 read_block = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800260 current_buffer = 0;
261
Sieu Mun Tang54064982022-04-28 22:40:58 +0800262 /* Disable bridge on full reconfiguration */
263 if (bridge_disable) {
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800264 socfpga_bridges_disable(~0);
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800265 }
266
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800267 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800268}
269
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800270static bool is_fpga_config_buffer_full(void)
271{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800272 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
273 if (!fpga_config_buffers[i].write_requested) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800274 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800275 }
276 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800277 return true;
278}
279
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800280bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800281{
Abdul Halim, Muhammad Hadi Asyrafi461f5442020-07-03 13:22:09 +0800282 if (!addr && !size) {
283 return true;
284 }
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800285 if (size > (UINT64_MAX - addr)) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800286 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800287 }
288 if (addr < BL31_LIMIT) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800289 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800290 }
291 if (addr + size > DRAM_BASE + DRAM_SIZE) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800292 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800293 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800294
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800295 return true;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800296}
Hadi Asyrafi616da772019-06-27 11:34:03 +0800297
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800298static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800299{
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800300 int i;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800301
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800302 intel_fpga_sdm_write_all();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800303
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800304 if (!is_address_in_ddr_range(mem, size) ||
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800305 is_fpga_config_buffer_full()) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800306 return INTEL_SIP_SMC_STATUS_REJECTED;
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800307 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800308
309 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800310 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
311
312 if (!fpga_config_buffers[j].write_requested) {
313 fpga_config_buffers[j].addr = mem;
314 fpga_config_buffers[j].size = size;
315 fpga_config_buffers[j].size_written = 0;
316 fpga_config_buffers[j].write_requested = 1;
317 fpga_config_buffers[j].block_number =
Hadi Asyrafi616da772019-06-27 11:34:03 +0800318 blocks_submitted++;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800319 fpga_config_buffers[j].subblocks_sent = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800320 break;
321 }
322 }
323
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800324 if (is_fpga_config_buffer_full()) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800325 return INTEL_SIP_SMC_STATUS_BUSY;
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800326 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800327
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800328 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800329}
330
Hadi Asyrafi67942302019-10-22 13:28:51 +0800331static int is_out_of_sec_range(uint64_t reg_addr)
332{
Siew Chin Lim869d4f52021-05-11 21:12:22 +0800333#if DEBUG
334 return 0;
335#endif
336
Hadi Asyrafi67942302019-10-22 13:28:51 +0800337 switch (reg_addr) {
338 case(0xF8011100): /* ECCCTRL1 */
339 case(0xF8011104): /* ECCCTRL2 */
340 case(0xF8011110): /* ERRINTEN */
341 case(0xF8011114): /* ERRINTENS */
342 case(0xF8011118): /* ERRINTENR */
343 case(0xF801111C): /* INTMODE */
344 case(0xF8011120): /* INTSTAT */
345 case(0xF8011124): /* DIAGINTTEST */
346 case(0xF801112C): /* DERRADDRA */
347 case(0xFFD12028): /* SDMMCGRP_CTRL */
348 case(0xFFD12044): /* EMAC0 */
349 case(0xFFD12048): /* EMAC1 */
350 case(0xFFD1204C): /* EMAC2 */
351 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
352 case(0xFFD12094): /* ECC_INT_MASK_SET */
353 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
354 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
355 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
356 case(0xFFD120C0): /* NOC_TIMEOUT */
357 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
358 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
359 case(0xFFD120D0): /* NOC_IDLEACK */
360 case(0xFFD120D4): /* NOC_IDLESTATUS */
361 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
362 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
363 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
364 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
365 return 0;
366
367 default:
368 break;
369 }
370
371 return -1;
372}
373
374/* Secure register access */
375uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
376{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800377 if (is_out_of_sec_range(reg_addr)) {
Hadi Asyrafi67942302019-10-22 13:28:51 +0800378 return INTEL_SIP_SMC_STATUS_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800379 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800380
381 *retval = mmio_read_32(reg_addr);
382
383 return INTEL_SIP_SMC_STATUS_OK;
384}
385
386uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
387 uint32_t *retval)
388{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800389 if (is_out_of_sec_range(reg_addr)) {
Hadi Asyrafi67942302019-10-22 13:28:51 +0800390 return INTEL_SIP_SMC_STATUS_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800391 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800392
393 mmio_write_32(reg_addr, val);
394
395 return intel_secure_reg_read(reg_addr, retval);
396}
397
398uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
399 uint32_t val, uint32_t *retval)
400{
401 if (!intel_secure_reg_read(reg_addr, retval)) {
402 *retval &= ~mask;
Siew Chin Lima0763152021-07-10 00:55:35 +0800403 *retval |= val & mask;
Hadi Asyrafi67942302019-10-22 13:28:51 +0800404 return intel_secure_reg_write(reg_addr, *retval, retval);
405 }
406
407 return INTEL_SIP_SMC_STATUS_ERROR;
408}
409
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800410/* Intel Remote System Update (RSU) services */
411uint64_t intel_rsu_update_address;
412
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +0800413static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800414{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800415 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800416 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800417 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800418
419 return INTEL_SIP_SMC_STATUS_OK;
420}
421
422static uint32_t intel_rsu_update(uint64_t update_address)
423{
424 intel_rsu_update_address = update_address;
425 return INTEL_SIP_SMC_STATUS_OK;
426}
427
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800428static uint32_t intel_rsu_notify(uint32_t execution_stage)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800429{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800430 if (mailbox_hps_stage_notify(execution_stage) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800431 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800432 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800433
434 return INTEL_SIP_SMC_STATUS_OK;
435}
436
437static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
438 uint32_t *ret_stat)
439{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800440 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800441 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800442 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800443
444 *ret_stat = respbuf[8];
445 return INTEL_SIP_SMC_STATUS_OK;
446}
447
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +0800448static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
449 uint64_t dcmf_ver_3_2)
450{
451 rsu_dcmf_ver[0] = dcmf_ver_1_0;
452 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
453 rsu_dcmf_ver[2] = dcmf_ver_3_2;
454 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
455
456 return INTEL_SIP_SMC_STATUS_OK;
457}
458
Sieu Mun Tange6d5de92022-04-28 22:21:01 +0800459static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
460{
461 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
462 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
463 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
464 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
465
466 return INTEL_SIP_SMC_STATUS_OK;
467}
468
Kris Chapline768dfa2021-06-25 11:31:52 +0100469/* Intel HWMON services */
470static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
471{
472 if (chan > TEMP_CHANNEL_MAX) {
473 return INTEL_SIP_SMC_STATUS_ERROR;
474 }
475
476 if (mailbox_hwmon_readtemp(chan, retval) < 0) {
477 return INTEL_SIP_SMC_STATUS_ERROR;
478 }
479
480 return INTEL_SIP_SMC_STATUS_OK;
481}
482
483static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
484{
485 if (chan > VOLT_CHANNEL_MAX) {
486 return INTEL_SIP_SMC_STATUS_ERROR;
487 }
488
489 if (mailbox_hwmon_readvolt(chan, retval) < 0) {
490 return INTEL_SIP_SMC_STATUS_ERROR;
491 }
492
493 return INTEL_SIP_SMC_STATUS_OK;
494}
495
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800496/* Mailbox services */
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800497static uint32_t intel_smc_fw_version(uint32_t *fw_version)
498{
Sieu Mun Tangbfda95a2022-04-27 18:54:10 +0800499 int status;
500 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
501 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
502
503 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
504 CMD_CASUAL, resp_data, &resp_len);
505
506 if (status < 0) {
507 return INTEL_SIP_SMC_STATUS_ERROR;
508 }
509
510 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
511 return INTEL_SIP_SMC_STATUS_ERROR;
512 }
513
514 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800515
516 return INTEL_SIP_SMC_STATUS_OK;
517}
518
Sieu Mun Tang24682662022-02-19 21:49:48 +0800519static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800520 unsigned int len, uint32_t urgent, uint64_t response,
Sieu Mun Tang24682662022-02-19 21:49:48 +0800521 unsigned int resp_len, int *mbox_status,
522 unsigned int *len_in_resp)
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800523{
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800524 *len_in_resp = 0;
Sieu Mun Tang96bbdca2022-04-12 15:00:13 +0800525 *mbox_status = GENERIC_RESPONSE_ERROR;
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800526
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800527 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800528 return INTEL_SIP_SMC_STATUS_REJECTED;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800529 }
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800530
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800531 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800532 (uint32_t *) response, &resp_len);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800533
534 if (status < 0) {
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800535 *mbox_status = -status;
536 return INTEL_SIP_SMC_STATUS_ERROR;
537 }
538
539 *mbox_status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800540 *len_in_resp = resp_len;
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800541
542 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE);
543
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800544 return INTEL_SIP_SMC_STATUS_OK;
545}
546
Sieu Mun Tang2b8e0052022-04-27 18:57:29 +0800547static int intel_smc_get_usercode(uint32_t *user_code)
548{
549 int status;
550 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
551
552 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
553 0U, CMD_CASUAL, user_code, &resp_len);
554
555 if (status < 0) {
556 return INTEL_SIP_SMC_STATUS_ERROR;
557 }
558
559 return INTEL_SIP_SMC_STATUS_OK;
560}
561
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800562uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size,
563 uint32_t mode, uint32_t *job_id,
564 uint32_t *ret_size, uint32_t *mbox_error)
565{
566 int status = 0;
567 uint32_t resp_len = size / MBOX_WORD_BYTE;
568
569 if (resp_len > MBOX_DATA_MAX_LEN) {
570 return INTEL_SIP_SMC_STATUS_REJECTED;
571 }
572
573 if (!is_address_in_ddr_range(addr, size)) {
574 return INTEL_SIP_SMC_STATUS_REJECTED;
575 }
576
577 if (mode == SERVICE_COMPLETED_MODE_ASYNC) {
578 status = mailbox_read_response_async(job_id,
579 NULL, (uint32_t *) addr, &resp_len, 0);
580 } else {
581 status = mailbox_read_response(job_id,
582 (uint32_t *) addr, &resp_len);
583
584 if (status == MBOX_NO_RESPONSE) {
585 status = MBOX_BUSY;
586 }
587 }
588
589 if (status == MBOX_NO_RESPONSE) {
590 return INTEL_SIP_SMC_STATUS_NO_RESPONSE;
591 }
592
593 if (status == MBOX_BUSY) {
594 return INTEL_SIP_SMC_STATUS_BUSY;
595 }
596
597 *ret_size = resp_len * MBOX_WORD_BYTE;
598 flush_dcache_range(addr, *ret_size);
599
600 if (status != MBOX_RET_OK) {
601 *mbox_error = -status;
602 return INTEL_SIP_SMC_STATUS_ERROR;
603 }
604
605 return INTEL_SIP_SMC_STATUS_OK;
606}
607
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800608/* Miscellaneous HPS services */
609uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
610{
611 int status = 0;
612
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800613 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) {
614 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800615 status = socfpga_bridges_enable((uint32_t)mask);
616 } else {
617 status = socfpga_bridges_enable(~0);
618 }
619 } else {
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800620 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800621 status = socfpga_bridges_disable((uint32_t)mask);
622 } else {
623 status = socfpga_bridges_disable(~0);
624 }
625 }
626
627 if (status < 0) {
628 return INTEL_SIP_SMC_STATUS_ERROR;
629 }
630
631 return INTEL_SIP_SMC_STATUS_OK;
632}
633
Hadi Asyrafi616da772019-06-27 11:34:03 +0800634/*
635 * This function is responsible for handling all SiP calls from the NS world
636 */
637
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800638uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800639 u_register_t x1,
640 u_register_t x2,
641 u_register_t x3,
642 u_register_t x4,
643 void *cookie,
644 void *handle,
645 u_register_t flags)
646{
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800647 uint32_t retval = 0, completed_addr[3];
648 uint32_t retval2 = 0;
Sieu Mun Tanga34b8812022-03-17 03:11:55 +0800649 uint32_t mbox_error = 0;
Sieu Mun Tanga34b8812022-03-17 03:11:55 +0800650 uint64_t retval64, rsu_respbuf[9];
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800651 int status = INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800652 int mbox_status;
653 unsigned int len_in_resp;
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800654 u_register_t x5, x6, x7;
Abdul Halim, Muhammad Hadi Asyrafib45f15e2020-05-14 15:32:43 +0800655
Hadi Asyrafi616da772019-06-27 11:34:03 +0800656 switch (smc_fid) {
657 case SIP_SVC_UID:
658 /* Return UID to the caller */
659 SMC_UUID_RET(handle, intl_svc_uid);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800660
Hadi Asyrafi616da772019-06-27 11:34:03 +0800661 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800662 status = intel_mailbox_fpga_config_isdone();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800663 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800664
Hadi Asyrafi616da772019-06-27 11:34:03 +0800665 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
666 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
667 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
668 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
669 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800670
Hadi Asyrafi616da772019-06-27 11:34:03 +0800671 case INTEL_SIP_SMC_FPGA_CONFIG_START:
672 status = intel_fpga_config_start(x1);
673 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800674
Hadi Asyrafi616da772019-06-27 11:34:03 +0800675 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
676 status = intel_fpga_config_write(x1, x2);
677 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800678
Hadi Asyrafi616da772019-06-27 11:34:03 +0800679 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
680 status = intel_fpga_config_completed_write(completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800681 &retval, &rcv_id);
682 switch (retval) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800683 case 1:
684 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
685 completed_addr[0], 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800686
Hadi Asyrafi616da772019-06-27 11:34:03 +0800687 case 2:
688 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
689 completed_addr[0],
690 completed_addr[1], 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800691
Hadi Asyrafi616da772019-06-27 11:34:03 +0800692 case 3:
693 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
694 completed_addr[0],
695 completed_addr[1],
696 completed_addr[2]);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800697
Hadi Asyrafi616da772019-06-27 11:34:03 +0800698 case 0:
699 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800700
Hadi Asyrafi616da772019-06-27 11:34:03 +0800701 default:
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800702 mailbox_clear_response();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800703 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
704 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800705
706 case INTEL_SIP_SMC_REG_READ:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800707 status = intel_secure_reg_read(x1, &retval);
708 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800709
710 case INTEL_SIP_SMC_REG_WRITE:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800711 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
712 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800713
714 case INTEL_SIP_SMC_REG_UPDATE:
715 status = intel_secure_reg_update(x1, (uint32_t)x2,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800716 (uint32_t)x3, &retval);
717 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800718
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800719 case INTEL_SIP_SMC_RSU_STATUS:
720 status = intel_rsu_status(rsu_respbuf,
721 ARRAY_SIZE(rsu_respbuf));
722 if (status) {
723 SMC_RET1(handle, status);
724 } else {
725 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
726 rsu_respbuf[2], rsu_respbuf[3]);
727 }
728
729 case INTEL_SIP_SMC_RSU_UPDATE:
730 status = intel_rsu_update(x1);
731 SMC_RET1(handle, status);
732
733 case INTEL_SIP_SMC_RSU_NOTIFY:
734 status = intel_rsu_notify(x1);
735 SMC_RET1(handle, status);
736
737 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
738 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800739 ARRAY_SIZE(rsu_respbuf), &retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800740 if (status) {
741 SMC_RET1(handle, status);
742 } else {
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800743 SMC_RET2(handle, status, retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800744 }
745
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +0800746 case INTEL_SIP_SMC_RSU_DCMF_VERSION:
747 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
748 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
749 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
750
751 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
752 status = intel_rsu_copy_dcmf_version(x1, x2);
753 SMC_RET1(handle, status);
754
Sieu Mun Tange6d5de92022-04-28 22:21:01 +0800755 case INTEL_SIP_SMC_RSU_DCMF_STATUS:
756 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
757 ((uint64_t)rsu_dcmf_stat[3] << 48) |
758 ((uint64_t)rsu_dcmf_stat[2] << 32) |
759 ((uint64_t)rsu_dcmf_stat[1] << 16) |
760 rsu_dcmf_stat[0]);
761
762 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
763 status = intel_rsu_copy_dcmf_status(x1);
764 SMC_RET1(handle, status);
765
Chee Hong Ang681631b2020-07-01 14:22:25 +0800766 case INTEL_SIP_SMC_RSU_MAX_RETRY:
767 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
768
769 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
770 rsu_max_retry = x1;
771 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
772
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800773 case INTEL_SIP_SMC_ECC_DBE:
774 status = intel_ecc_dbe_notification(x1);
775 SMC_RET1(handle, status);
776
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800777 case INTEL_SIP_SMC_SERVICE_COMPLETED:
778 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
779 &len_in_resp, &mbox_error);
780 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
781
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800782 case INTEL_SIP_SMC_FIRMWARE_VERSION:
783 status = intel_smc_fw_version(&retval);
Sieu Mun Tangbfda95a2022-04-27 18:54:10 +0800784 SMC_RET2(handle, status, retval);
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800785
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800786 case INTEL_SIP_SMC_MBOX_SEND_CMD:
787 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
788 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800789 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
790 &mbox_status, &len_in_resp);
Sieu Mun Tangf02f0cb2022-02-19 20:36:41 +0800791 SMC_RET3(handle, status, mbox_status, len_in_resp);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800792
Sieu Mun Tang2b8e0052022-04-27 18:57:29 +0800793 case INTEL_SIP_SMC_GET_USERCODE:
794 status = intel_smc_get_usercode(&retval);
795 SMC_RET2(handle, status, retval);
796
Sieu Mun Tang128d2a72022-05-11 09:49:25 +0800797 case INTEL_SIP_SMC_FCS_CRYPTION:
798 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
799
800 if (x1 == FCS_MODE_DECRYPT) {
801 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
802 } else if (x1 == FCS_MODE_ENCRYPT) {
803 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
804 } else {
805 status = INTEL_SIP_SMC_STATUS_REJECTED;
806 }
807
808 SMC_RET3(handle, status, x4, x5);
809
Sieu Mun Tang22322fb2022-05-09 16:05:58 +0800810 case INTEL_SIP_SMC_FCS_CRYPTION_EXT:
811 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
812 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
813 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
814
815 if (x3 == FCS_MODE_DECRYPT) {
816 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
817 (uint32_t *) &x7, &mbox_error);
818 } else if (x3 == FCS_MODE_ENCRYPT) {
819 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
820 (uint32_t *) &x7, &mbox_error);
821 } else {
822 status = INTEL_SIP_SMC_STATUS_REJECTED;
823 }
824
825 SMC_RET4(handle, status, mbox_error, x6, x7);
826
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800827 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER:
828 status = intel_fcs_random_number_gen(x1, &retval64,
829 &mbox_error);
830 SMC_RET4(handle, status, mbox_error, x1, retval64);
831
Sieu Mun Tange7a037f2022-05-10 17:18:19 +0800832 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT:
833 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
834 &send_id);
835 SMC_RET1(handle, status);
836
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800837 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
838 status = intel_fcs_send_cert(x1, x2, &send_id);
839 SMC_RET1(handle, status);
840
841 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
842 status = intel_fcs_get_provision_data(&send_id);
843 SMC_RET1(handle, status);
844
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +0800845 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
846 status = intel_fcs_cntr_set_preauth(x1, x2, x3,
847 &mbox_error);
848 SMC_RET2(handle, status, mbox_error);
849
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800850 case INTEL_SIP_SMC_HPS_SET_BRIDGES:
851 status = intel_hps_set_bridges(x1, x2);
852 SMC_RET1(handle, status);
853
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800854 case INTEL_SIP_SMC_HWMON_READTEMP:
855 status = intel_hwmon_readtemp(x1, &retval);
856 SMC_RET2(handle, status, retval);
857
858 case INTEL_SIP_SMC_HWMON_READVOLT:
859 status = intel_hwmon_readvolt(x1, &retval);
860 SMC_RET2(handle, status, retval);
861
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800862 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN:
863 status = intel_fcs_sigma_teardown(x1, &mbox_error);
864 SMC_RET2(handle, status, mbox_error);
865
866 case INTEL_SIP_SMC_FCS_CHIP_ID:
867 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
868 SMC_RET4(handle, status, mbox_error, retval, retval2);
869
870 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY:
871 status = intel_fcs_attestation_subkey(x1, x2, x3,
872 (uint32_t *) &x4, &mbox_error);
873 SMC_RET4(handle, status, mbox_error, x3, x4);
874
875 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS:
876 status = intel_fcs_get_measurement(x1, x2, x3,
877 (uint32_t *) &x4, &mbox_error);
878 SMC_RET4(handle, status, mbox_error, x3, x4);
879
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800880 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
881 status = intel_fcs_get_attestation_cert(x1, x2,
882 (uint32_t *) &x3, &mbox_error);
883 SMC_RET4(handle, status, mbox_error, x2, x3);
884
885 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
886 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
887 SMC_RET2(handle, status, mbox_error);
888
Sieu Mun Tang16754e12022-05-09 12:08:42 +0800889 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
890 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
891 SMC_RET3(handle, status, mbox_error, retval);
892
893 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION:
894 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
895 SMC_RET2(handle, status, mbox_error);
896
Sieu Mun Tangfb1f6e92022-05-09 14:16:14 +0800897 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY:
898 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
899 SMC_RET1(handle, status);
900
901 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY:
902 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
903 (uint32_t *) &x4, &mbox_error);
904 SMC_RET4(handle, status, mbox_error, x3, x4);
905
906 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY:
907 status = intel_fcs_remove_crypto_service_key(x1, x2,
908 &mbox_error);
909 SMC_RET2(handle, status, mbox_error);
910
911 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO:
912 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
913 (uint32_t *) &x4, &mbox_error);
914 SMC_RET4(handle, status, mbox_error, x3, x4);
915
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800916 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT:
917 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
918 status = intel_fcs_get_digest_init(x1, x2, x3,
919 x4, x5, &mbox_error);
920 SMC_RET2(handle, status, mbox_error);
921
Sieu Mun Tang527df9f2022-04-28 16:28:48 +0800922 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
923 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
924 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
925 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
926 x4, x5, (uint32_t *) &x6, false,
927 &mbox_error);
928 SMC_RET4(handle, status, mbox_error, x5, x6);
929
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800930 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
931 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
932 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang527df9f2022-04-28 16:28:48 +0800933 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
934 x4, x5, (uint32_t *) &x6, true,
935 &mbox_error);
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800936 SMC_RET4(handle, status, mbox_error, x5, x6);
937
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800938 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
939 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
940 status = intel_fcs_mac_verify_init(x1, x2, x3,
941 x4, x5, &mbox_error);
942 SMC_RET2(handle, status, mbox_error);
943
Sieu Mun Tang527df9f2022-04-28 16:28:48 +0800944 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE:
945 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
946 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
947 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
948 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
949 x4, x5, (uint32_t *) &x6, x7,
950 false, &mbox_error);
951 SMC_RET4(handle, status, mbox_error, x5, x6);
952
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800953 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
954 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
955 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
956 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
Sieu Mun Tang527df9f2022-04-28 16:28:48 +0800957 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
958 x4, x5, (uint32_t *) &x6, x7,
959 true, &mbox_error);
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800960 SMC_RET4(handle, status, mbox_error, x5, x6);
961
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +0800962 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
963 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
964 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
965 x4, x5, &mbox_error);
966 SMC_RET2(handle, status, mbox_error);
967
Sieu Mun Tange77d37d2022-04-28 16:23:20 +0800968 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
969 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
970 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
971 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
972 x3, x4, x5, (uint32_t *) &x6, false,
973 &mbox_error);
974 SMC_RET4(handle, status, mbox_error, x5, x6);
975
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +0800976 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
977 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
978 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tange77d37d2022-04-28 16:23:20 +0800979 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
980 x3, x4, x5, (uint32_t *) &x6, true,
981 &mbox_error);
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +0800982 SMC_RET4(handle, status, mbox_error, x5, x6);
983
Sieu Mun Tang8aa05ad2022-05-10 17:50:30 +0800984 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
985 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
986 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
987 x4, x5, &mbox_error);
988 SMC_RET2(handle, status, mbox_error);
989
990 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
991 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
992 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
993 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
994 x4, x5, (uint32_t *) &x6, &mbox_error);
995 SMC_RET4(handle, status, mbox_error, x5, x6);
996
Sieu Mun Tang59357e82022-05-10 17:53:32 +0800997 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
998 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
999 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1000 x4, x5, &mbox_error);
1001 SMC_RET2(handle, status, mbox_error);
1002
1003 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
1004 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1005 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1006 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1007 x4, x5, (uint32_t *) &x6, &mbox_error);
1008 SMC_RET4(handle, status, mbox_error, x5, x6);
1009
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001010 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
1011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1012 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1013 x4, x5, &mbox_error);
1014 SMC_RET2(handle, status, mbox_error);
1015
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001016 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
1017 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1018 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1019 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1020 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1021 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1022 x7, false, &mbox_error);
1023 SMC_RET4(handle, status, mbox_error, x5, x6);
1024
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001025 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
1026 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1027 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1028 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001029 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1030 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1031 x7, true, &mbox_error);
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001032 SMC_RET4(handle, status, mbox_error, x5, x6);
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001033
Sieu Mun Tange2f3ede2022-05-10 17:36:32 +08001034 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
1035 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1036 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1037 x4, x5, &mbox_error);
1038 SMC_RET2(handle, status, mbox_error);
1039
1040 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
1041 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1042 (uint32_t *) &x4, &mbox_error);
1043 SMC_RET4(handle, status, mbox_error, x3, x4);
1044
Sieu Mun Tang0675c222022-05-10 17:48:11 +08001045 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
1046 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1047 status = intel_fcs_ecdh_request_init(x1, x2, x3,
1048 x4, x5, &mbox_error);
1049 SMC_RET2(handle, status, mbox_error);
1050
1051 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
1052 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1053 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1054 status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1055 x4, x5, (uint32_t *) &x6, &mbox_error);
1056 SMC_RET4(handle, status, mbox_error, x5, x6);
1057
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001058 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT:
1059 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1060 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1061 &mbox_error);
1062 SMC_RET2(handle, status, mbox_error);
1063
Sieu Mun Tang9bea8152022-04-28 16:15:54 +08001064 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
1065 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1066 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1067 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1068 x5, x6, false, &send_id);
1069 SMC_RET1(handle, status);
1070
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001071 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
1072 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1073 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang9bea8152022-04-28 16:15:54 +08001074 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1075 x5, x6, true, &send_id);
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001076 SMC_RET1(handle, status);
1077
Sieu Mun Tanga34b8812022-03-17 03:11:55 +08001078 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
1079 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
1080 &mbox_error);
1081 SMC_RET4(handle, status, mbox_error, x1, retval64);
1082
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +08001083 case INTEL_SIP_SMC_SVC_VERSION:
1084 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
1085 SIP_SVC_VERSION_MAJOR,
1086 SIP_SVC_VERSION_MINOR);
1087
Hadi Asyrafi616da772019-06-27 11:34:03 +08001088 default:
1089 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1090 cookie, handle, flags);
1091 }
1092}
1093
Sieu Mun Tang044ed482022-05-11 10:45:19 +08001094uintptr_t sip_smc_handler(uint32_t smc_fid,
1095 u_register_t x1,
1096 u_register_t x2,
1097 u_register_t x3,
1098 u_register_t x4,
1099 void *cookie,
1100 void *handle,
1101 u_register_t flags)
1102{
1103 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK;
1104
1105 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN &&
1106 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
1107 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
1108 cookie, handle, flags);
1109 } else {
1110 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
1111 cookie, handle, flags);
1112 }
1113}
1114
Hadi Asyrafi616da772019-06-27 11:34:03 +08001115DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +08001116 socfpga_sip_svc,
Hadi Asyrafi616da772019-06-27 11:34:03 +08001117 OEN_SIP_START,
1118 OEN_SIP_END,
1119 SMC_TYPE_FAST,
1120 NULL,
1121 sip_smc_handler
1122);
1123
1124DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +08001125 socfpga_sip_svc_std,
Hadi Asyrafi616da772019-06-27 11:34:03 +08001126 OEN_SIP_START,
1127 OEN_SIP_END,
1128 SMC_TYPE_YIELD,
1129 NULL,
1130 sip_smc_handler
1131);