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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorov813c9f92020-03-03 13:31:58 +00002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Varun Wadekar787a1292018-06-18 16:15:51 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010078 * Definitions for CPU system register interface to GICv3
79 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
81#define ICC_SGI1R S3_0_C12_C11_5
82#define ICC_SRE_EL1 S3_0_C12_C12_5
83#define ICC_SRE_EL2 S3_4_C12_C9_5
84#define ICC_SRE_EL3 S3_6_C12_C12_5
85#define ICC_CTLR_EL1 S3_0_C12_C12_4
86#define ICC_CTLR_EL3 S3_6_C12_C12_4
87#define ICC_PMR_EL1 S3_0_C4_C6_0
88#define ICC_RPR_EL1 S3_0_C12_C11_3
89#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
90#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
91#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
92#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
93#define ICC_IAR0_EL1 S3_0_c12_c8_0
94#define ICC_IAR1_EL1 S3_0_c12_c12_0
95#define ICC_EOIR0_EL1 S3_0_c12_c8_1
96#define ICC_EOIR1_EL1 S3_0_c12_c12_1
97#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010098
99/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000100 * Definitions for EL2 system registers for save/restore routine
101 ******************************************************************************/
102
103#define CNTPOFF_EL2 S3_4_C14_C0_6
104#define HAFGRTR_EL2 S3_4_C3_C1_6
105#define HDFGRTR_EL2 S3_4_C3_C1_4
106#define HDFGWTR_EL2 S3_4_C3_C1_5
107#define HFGITR_EL2 S3_4_C1_C1_6
108#define HFGRTR_EL2 S3_4_C1_C1_4
109#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000111#define ICH_VMCR_EL2 S3_4_C12_C11_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000112#define MPAMVPM0_EL2 S3_4_C10_C5_0
113#define MPAMVPM1_EL2 S3_4_C10_C5_1
114#define MPAMVPM2_EL2 S3_4_C10_C5_2
115#define MPAMVPM3_EL2 S3_4_C10_C5_3
116#define MPAMVPM4_EL2 S3_4_C10_C5_4
117#define MPAMVPM5_EL2 S3_4_C10_C5_5
118#define MPAMVPM6_EL2 S3_4_C10_C5_6
119#define MPAMVPM7_EL2 S3_4_C10_C5_7
120#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000121#define TRFCR_EL2 S3_4_C1_C2_1
122#define PMSCR_EL2 S3_4_C9_C9_0
123#define TFSR_EL2 S3_4_C5_C6_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000124
125/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000126 * Generic timer memory mapped registers & offsets
127 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700128#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200129#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700130#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000131
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700132#define CNTCR_EN (U(1) << 0)
133#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100134#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000135
136/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 * System register bit definitions
138 ******************************************************************************/
139/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700140#define LOUIS_SHIFT U(21)
141#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100142#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
145/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100148/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700149#define DCISW U(0x0)
150#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000151#if ERRATA_A53_827319
152#define DCCSW DCCISW
153#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700154#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000155#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156
157/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700158#define ID_AA64PFR0_EL0_SHIFT U(0)
159#define ID_AA64PFR0_EL1_SHIFT U(4)
160#define ID_AA64PFR0_EL2_SHIFT U(8)
161#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100162#define ID_AA64PFR0_AMU_SHIFT U(44)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100163#define ID_AA64PFR0_AMU_MASK ULL(0xf)
164#define ID_AA64PFR0_ELX_MASK ULL(0xf)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100165#define ID_AA64PFR0_GIC_SHIFT U(24)
166#define ID_AA64PFR0_GIC_WIDTH U(4)
167#define ID_AA64PFR0_GIC_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100168#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100169#define ID_AA64PFR0_SVE_MASK ULL(0xf)
Achin Gupta023c1552019-10-11 14:44:05 +0100170#define ID_AA64PFR0_SEL2_SHIFT U(36)
Artsem Artsemenkaa5334472019-11-26 16:40:31 +0000171#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100172#define ID_AA64PFR0_MPAM_SHIFT U(40)
173#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Sathees Balya0911df12018-12-06 13:33:24 +0000174#define ID_AA64PFR0_DIT_SHIFT U(48)
175#define ID_AA64PFR0_DIT_MASK ULL(0xf)
176#define ID_AA64PFR0_DIT_LENGTH U(4)
177#define ID_AA64PFR0_DIT_SUPPORTED U(1)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000178#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100179#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000180#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100182/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100183#define EL_IMPL_NONE ULL(0)
184#define EL_IMPL_A64ONLY ULL(1)
185#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000186
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100187/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
188#define ID_AA64DFR0_PMS_SHIFT U(32)
189#define ID_AA64DFR0_PMS_MASK ULL(0xf)
Achin Gupta92712a52015-09-03 14:18:02 +0100190
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000191/* ID_AA64ISAR1_EL1 definitions */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000192#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000193#define ID_AA64ISAR1_GPI_SHIFT U(28)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000194#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000195#define ID_AA64ISAR1_GPA_SHIFT U(24)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000196#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000197#define ID_AA64ISAR1_API_SHIFT U(8)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000198#define ID_AA64ISAR1_API_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000199#define ID_AA64ISAR1_APA_SHIFT U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000200#define ID_AA64ISAR1_APA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000201
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000202/* ID_AA64MMFR0_EL1 definitions */
203#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
204#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
205
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700206#define PARANGE_0000 U(32)
207#define PARANGE_0001 U(36)
208#define PARANGE_0010 U(40)
209#define PARANGE_0011 U(42)
210#define PARANGE_0100 U(44)
211#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000212#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000213
Jimmy Brisson83573892020-04-16 10:48:02 -0500214#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
215#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
216#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
217#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
218#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
219
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500220#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
221#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
222#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
223#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
224
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100225#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100226#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
227#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
228#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100229
230#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100231#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
232#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
233#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100234
235#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100236#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
237#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
238#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100239
johpow013e24c162020-04-22 14:05:13 -0500240/* ID_AA64MMFR1_EL1 definitions */
241#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
242#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
243#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
244#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
245
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000246/* ID_AA64MMFR2_EL1 definitions */
247#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000248
249#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
250#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
251
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000252#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
253#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
254
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000255/* ID_AA64PFR1_EL1 definitions */
256#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
257#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
258
259#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
260
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100261#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
262#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
263
264#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
265
Soby Mathew830f0ad2019-07-12 09:23:38 +0100266#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
267#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
268
269#define MTE_UNIMPLEMENTED ULL(0)
270#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
271#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
272
Alexei Fedorov19933552020-05-26 13:16:41 +0100273#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
274#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
275
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700277#define ID_PFR1_VIRTEXT_SHIFT U(12)
278#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100279#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280 & ID_PFR1_VIRTEXT_MASK)
281
282/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100283#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700284 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
285 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286
John Powella5c66362020-03-20 14:21:05 -0500287#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
288 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200289#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700290 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
291 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200292
David Cunadofee86532017-04-13 22:38:29 +0100293#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
294 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
295 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
296
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000297#define SCTLR_M_BIT (ULL(1) << 0)
298#define SCTLR_A_BIT (ULL(1) << 1)
299#define SCTLR_C_BIT (ULL(1) << 2)
300#define SCTLR_SA_BIT (ULL(1) << 3)
301#define SCTLR_SA0_BIT (ULL(1) << 4)
302#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
303#define SCTLR_ITD_BIT (ULL(1) << 7)
304#define SCTLR_SED_BIT (ULL(1) << 8)
305#define SCTLR_UMA_BIT (ULL(1) << 9)
306#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100307#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000308#define SCTLR_DZE_BIT (ULL(1) << 14)
309#define SCTLR_UCT_BIT (ULL(1) << 15)
310#define SCTLR_NTWI_BIT (ULL(1) << 16)
311#define SCTLR_NTWE_BIT (ULL(1) << 18)
312#define SCTLR_WXN_BIT (ULL(1) << 19)
313#define SCTLR_UWXN_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000314#define SCTLR_IESB_BIT (ULL(1) << 21)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000315#define SCTLR_E0E_BIT (ULL(1) << 24)
316#define SCTLR_EE_BIT (ULL(1) << 25)
317#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100318#define SCTLR_EnDA_BIT (ULL(1) << 27)
319#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000320#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100321#define SCTLR_BT0_BIT (ULL(1) << 35)
322#define SCTLR_BT1_BIT (ULL(1) << 36)
323#define SCTLR_BT_BIT (ULL(1) << 36)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000324#define SCTLR_DSSBS_BIT (ULL(1) << 44)
David Cunadofee86532017-04-13 22:38:29 +0100325#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100326
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700328#define CPACR_EL1_FPEN(x) ((x) << 20)
329#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
330#define CPACR_EL1_FP_TRAP_ALL U(0x2)
331#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100332
333/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700334#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
johpow013e24c162020-04-22 14:05:13 -0500335#define SCR_TWEDEL_SHIFT U(30)
336#define SCR_TWEDEL_MASK ULL(0xf)
337#define SCR_TWEDEn_BIT (UL(1) << 29)
Jimmy Brisson83573892020-04-16 10:48:02 -0500338#define SCR_ECVEN_BIT (U(1) << 28)
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500339#define SCR_FGTEN_BIT (U(1) << 27)
Soby Mathew830f0ad2019-07-12 09:23:38 +0100340#define SCR_ATA_BIT (U(1) << 26)
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000341#define SCR_FIEN_BIT (U(1) << 21)
Achin Gupta023c1552019-10-11 14:44:05 +0100342#define SCR_EEL2_BIT (U(1) << 18)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100343#define SCR_API_BIT (U(1) << 17)
344#define SCR_APK_BIT (U(1) << 16)
Varun Wadekar92234852020-06-12 10:11:28 -0700345#define SCR_TERR_BIT (U(1) << 15)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700346#define SCR_TWE_BIT (U(1) << 13)
347#define SCR_TWI_BIT (U(1) << 12)
348#define SCR_ST_BIT (U(1) << 11)
349#define SCR_RW_BIT (U(1) << 10)
350#define SCR_SIF_BIT (U(1) << 9)
351#define SCR_HCE_BIT (U(1) << 8)
352#define SCR_SMD_BIT (U(1) << 7)
353#define SCR_EA_BIT (U(1) << 3)
354#define SCR_FIQ_BIT (U(1) << 2)
355#define SCR_IRQ_BIT (U(1) << 1)
356#define SCR_NS_BIT (U(1) << 0)
357#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100358#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100359
David Cunadofee86532017-04-13 22:38:29 +0100360/* MDCR_EL3 definitions */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100361#define MDCR_SCCD_BIT (ULL(1) << 23)
362#define MDCR_SPME_BIT (ULL(1) << 17)
363#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000364#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000365#define MDCR_SPD32_LEGACY ULL(0x0)
366#define MDCR_SPD32_DISABLE ULL(0x2)
367#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100368#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000369#define MDCR_NSPB_EL1 ULL(0x3)
370#define MDCR_TDOSA_BIT (ULL(1) << 10)
371#define MDCR_TDA_BIT (ULL(1) << 9)
372#define MDCR_TPM_BIT (ULL(1) << 6)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000373#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000374
David Cunadofee86532017-04-13 22:38:29 +0100375/* MDCR_EL2 definitions */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100376#define MDCR_EL2_HLP (U(1) << 26)
377#define MDCR_EL2_HCCD (U(1) << 23)
378#define MDCR_EL2_TTRF (U(1) << 19)
379#define MDCR_EL2_HPMD (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100380#define MDCR_EL2_TPMS (U(1) << 14)
381#define MDCR_EL2_E2PB(x) ((x) << 12)
382#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100383#define MDCR_EL2_TDRA_BIT (U(1) << 11)
384#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
385#define MDCR_EL2_TDA_BIT (U(1) << 9)
386#define MDCR_EL2_TDE_BIT (U(1) << 8)
387#define MDCR_EL2_HPME_BIT (U(1) << 7)
388#define MDCR_EL2_TPM_BIT (U(1) << 6)
389#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
390#define MDCR_EL2_RESET_VAL U(0x0)
391
392/* HSTR_EL2 definitions */
393#define HSTR_EL2_RESET_VAL U(0x0)
394#define HSTR_EL2_T_MASK U(0xff)
395
396/* CNTHP_CTL_EL2 definitions */
397#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
398#define CNTHP_CTL_RESET_VAL U(0x0)
399
400/* VTTBR_EL2 definitions */
401#define VTTBR_RESET_VAL ULL(0x0)
402#define VTTBR_VMID_MASK ULL(0xff)
403#define VTTBR_VMID_SHIFT U(48)
404#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
405#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000406
Achin Gupta4f6ad662013-10-25 09:08:21 +0100407/* HCR definitions */
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100408#define HCR_API_BIT (ULL(1) << 41)
409#define HCR_APK_BIT (ULL(1) << 40)
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100410#define HCR_E2H_BIT (ULL(1) << 34)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000411#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700412#define HCR_RW_SHIFT U(31)
413#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100414#define HCR_AMO_BIT (ULL(1) << 5)
415#define HCR_IMO_BIT (ULL(1) << 4)
416#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100417
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100418/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700419#define ISR_A_SHIFT U(8)
420#define ISR_I_SHIFT U(7)
421#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100422
Achin Gupta4f6ad662013-10-25 09:08:21 +0100423/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100424#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700425#define EVNTEN_BIT (U(1) << 2)
426#define EL1PCEN_BIT (U(1) << 1)
427#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100428
429/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700430#define EL0PTEN_BIT (U(1) << 9)
431#define EL0VTEN_BIT (U(1) << 8)
432#define EL0PCTEN_BIT (U(1) << 0)
433#define EL0VCTEN_BIT (U(1) << 1)
434#define EVNTEN_BIT (U(1) << 2)
435#define EVNTDIR_BIT (U(1) << 3)
436#define EVNTI_SHIFT U(4)
437#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100438
439/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700440#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100441#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700442#define TTA_BIT (U(1) << 20)
443#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100444#define CPTR_EZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100445#define CPTR_EL3_RESET_VAL U(0x0)
446
447/* CPTR_EL2 definitions */
448#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
449#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100450#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100451#define CPTR_EL2_TTA_BIT (U(1) << 20)
452#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100453#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100454#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100455
456/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700457#define DAIF_FIQ_BIT (U(1) << 0)
458#define DAIF_IRQ_BIT (U(1) << 1)
459#define DAIF_ABT_BIT (U(1) << 2)
460#define DAIF_DBG_BIT (U(1) << 3)
461#define SPSR_DAIF_SHIFT U(6)
462#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100463
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700464#define SPSR_AIF_SHIFT U(6)
465#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100466
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700467#define SPSR_E_SHIFT U(9)
468#define SPSR_E_MASK U(0x1)
469#define SPSR_E_LITTLE U(0x0)
470#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100471
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700472#define SPSR_T_SHIFT U(5)
473#define SPSR_T_MASK U(0x1)
474#define SPSR_T_ARM U(0x0)
475#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100476
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000477#define SPSR_M_SHIFT U(4)
478#define SPSR_M_MASK U(0x1)
479#define SPSR_M_AARCH64 U(0x0)
480#define SPSR_M_AARCH32 U(0x1)
481
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000482#define SPSR_EL_SHIFT U(2)
483#define SPSR_EL_WIDTH U(2)
484
John Tsichritzis55534172019-07-23 11:12:41 +0100485#define SPSR_SSBS_BIT_AARCH64 BIT_64(12)
486#define SPSR_SSBS_BIT_AARCH32 BIT_64(23)
487
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100488#define DISABLE_ALL_EXCEPTIONS \
489 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
490
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000491#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
492
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000493/*
494 * RMR_EL3 definitions
495 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700496#define RMR_EL3_RR_BIT (U(1) << 1)
497#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000498
499/*
500 * HI-VECTOR address for AArch32 state
501 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000502#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100503
504/*
505 * TCR defintions
506 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000507#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100508#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700509#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100510#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700511#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700512
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100513#define TCR_TxSZ_MIN ULL(16)
514#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000515#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100516
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000517#define TCR_T0SZ_SHIFT U(0)
518#define TCR_T1SZ_SHIFT U(16)
519
Lin Ma741a3822014-06-27 16:56:30 -0700520/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100521#define TCR_PS_BITS_4GB ULL(0x0)
522#define TCR_PS_BITS_64GB ULL(0x1)
523#define TCR_PS_BITS_1TB ULL(0x2)
524#define TCR_PS_BITS_4TB ULL(0x3)
525#define TCR_PS_BITS_16TB ULL(0x4)
526#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100527
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700528#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
529#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
530#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
531#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
532#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
533#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100534
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100535#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
536#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
537#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
538#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100539
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100540#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
541#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
542#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
543#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100544
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100545#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
546#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
547#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100548
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000549#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
550#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
551#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
552#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
553
554#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
555#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
556#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
557#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
558
559#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
560#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
561#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
562
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100563#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100564#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100565#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
566#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
567#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
568
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000569#define TCR_TG1_SHIFT U(30)
570#define TCR_TG1_MASK ULL(3)
571#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
572#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
573#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
574
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100575#define TCR_EPD0_BIT (ULL(1) << 7)
576#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100577
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700578#define MODE_SP_SHIFT U(0x0)
579#define MODE_SP_MASK U(0x1)
580#define MODE_SP_EL0 U(0x0)
581#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100582
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700583#define MODE_RW_SHIFT U(0x4)
584#define MODE_RW_MASK U(0x1)
585#define MODE_RW_64 U(0x0)
586#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100587
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700588#define MODE_EL_SHIFT U(0x2)
589#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000590#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700591#define MODE_EL3 U(0x3)
592#define MODE_EL2 U(0x2)
593#define MODE_EL1 U(0x1)
594#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100595
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700596#define MODE32_SHIFT U(0)
597#define MODE32_MASK U(0xf)
598#define MODE32_usr U(0x0)
599#define MODE32_fiq U(0x1)
600#define MODE32_irq U(0x2)
601#define MODE32_svc U(0x3)
602#define MODE32_mon U(0x6)
603#define MODE32_abt U(0x7)
604#define MODE32_hyp U(0xa)
605#define MODE32_und U(0xb)
606#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100607
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100608#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
609#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
610#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
611#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100612
John Tsichritzis55534172019-07-23 11:12:41 +0100613#define SPSR_64(el, sp, daif) \
614 (((MODE_RW_64 << MODE_RW_SHIFT) | \
615 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
616 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
617 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
618 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100619
620#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100621 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700622 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
623 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
624 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100625 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
626 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100627
Dan Handley0cdebbd2015-03-30 17:15:16 +0100628/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100629 * TTBR Definitions
630 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100631#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100632
633/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100634 * CTR_EL0 definitions
635 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700636#define CTR_CWG_SHIFT U(24)
637#define CTR_CWG_MASK U(0xf)
638#define CTR_ERG_SHIFT U(20)
639#define CTR_ERG_MASK U(0xf)
640#define CTR_DMINLINE_SHIFT U(16)
641#define CTR_DMINLINE_MASK U(0xf)
642#define CTR_L1IP_SHIFT U(14)
643#define CTR_L1IP_MASK U(0x3)
644#define CTR_IMINLINE_SHIFT U(0)
645#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100646
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700647#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100648
Achin Gupta405406d2014-05-09 12:00:17 +0100649/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700650#define CNTP_CTL_ENABLE_SHIFT U(0)
651#define CNTP_CTL_IMASK_SHIFT U(1)
652#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100653
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700654#define CNTP_CTL_ENABLE_MASK U(1)
655#define CNTP_CTL_IMASK_MASK U(1)
656#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100657
Varun Wadekar787a1292018-06-18 16:15:51 -0700658/* Physical timer control macros */
659#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
660#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
661
Achin Gupta4f6ad662013-10-25 09:08:21 +0100662/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700663#define ESR_EC_SHIFT U(26)
664#define ESR_EC_MASK U(0x3f)
665#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100666#define ESR_ISS_SHIFT U(0)
667#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700668#define EC_UNKNOWN U(0x0)
669#define EC_WFE_WFI U(0x1)
670#define EC_AARCH32_CP15_MRC_MCR U(0x3)
671#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
672#define EC_AARCH32_CP14_MRC_MCR U(0x5)
673#define EC_AARCH32_CP14_LDC_STC U(0x6)
674#define EC_FP_SIMD U(0x7)
675#define EC_AARCH32_CP10_MRC U(0x8)
676#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
677#define EC_ILLEGAL U(0xe)
678#define EC_AARCH32_SVC U(0x11)
679#define EC_AARCH32_HVC U(0x12)
680#define EC_AARCH32_SMC U(0x13)
681#define EC_AARCH64_SVC U(0x15)
682#define EC_AARCH64_HVC U(0x16)
683#define EC_AARCH64_SMC U(0x17)
684#define EC_AARCH64_SYS U(0x18)
685#define EC_IABORT_LOWER_EL U(0x20)
686#define EC_IABORT_CUR_EL U(0x21)
687#define EC_PC_ALIGN U(0x22)
688#define EC_DABORT_LOWER_EL U(0x24)
689#define EC_DABORT_CUR_EL U(0x25)
690#define EC_SP_ALIGN U(0x26)
691#define EC_AARCH32_FP U(0x28)
692#define EC_AARCH64_FP U(0x2c)
693#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100694#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100695
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000696/*
697 * External Abort bit in Instruction and Data Aborts synchronous exception
698 * syndromes.
699 */
700#define ESR_ISS_EABORT_EA_BIT U(9)
701
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700702#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100703
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800704/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700705#define RMR_RESET_REQUEST_SHIFT U(0x1)
706#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800707
Dan Handleyed6ff952014-05-14 17:44:19 +0100708/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000709 * Definitions of register offsets, fields and macros for CPU system
710 * instructions.
711 ******************************************************************************/
712
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700713#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000714#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
715#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
716
717/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100718 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
719 * system level implementation of the Generic Timer.
720 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100721#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700722#define CNTNSAR U(0x4)
723#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100724
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700725#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
726#define CNTACR_RPCT_SHIFT U(0x0)
727#define CNTACR_RVCT_SHIFT U(0x1)
728#define CNTACR_RFRQ_SHIFT U(0x2)
729#define CNTACR_RVOFF_SHIFT U(0x3)
730#define CNTACR_RWVT_SHIFT U(0x4)
731#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100732
Soby Mathew2d9f7952018-06-11 16:21:30 +0100733/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000734 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100735 * system level implementation of the Generic Timer.
736 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000737/* Physical Count register. */
738#define CNTPCT_LO U(0x0)
739/* Counter Frequency register. */
740#define CNTBASEN_CNTFRQ U(0x10)
741/* Physical Timer CompareValue register. */
742#define CNTP_CVAL_LO U(0x20)
743/* Physical Timer Control register. */
744#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100745
David Cunado5f55e282016-10-31 17:37:34 +0000746/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100747#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700748#define PMCR_EL0_N_SHIFT U(11)
749#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000750#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100751#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +0100752#define PMCR_EL0_LC_BIT (U(1) << 6)
753#define PMCR_EL0_DP_BIT (U(1) << 5)
754#define PMCR_EL0_X_BIT (U(1) << 4)
755#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100756#define PMCR_EL0_C_BIT (U(1) << 2)
757#define PMCR_EL0_P_BIT (U(1) << 1)
758#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +0000759
Isla Mitchell02c63072017-07-21 14:44:36 +0100760/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100761 * Definitions for system register interface to SVE
762 ******************************************************************************/
763#define ZCR_EL3 S3_6_C1_C2_0
764#define ZCR_EL2 S3_4_C1_C2_0
765
766/* ZCR_EL3 definitions */
767#define ZCR_EL3_LEN_MASK U(0xf)
768
769/* ZCR_EL2 definitions */
770#define ZCR_EL2_LEN_MASK U(0xf)
771
772/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100773 * Definitions of MAIR encodings for device and normal memory
774 ******************************************************************************/
775/*
776 * MAIR encodings for device memory attributes.
777 */
778#define MAIR_DEV_nGnRnE ULL(0x0)
779#define MAIR_DEV_nGnRE ULL(0x4)
780#define MAIR_DEV_nGRE ULL(0x8)
781#define MAIR_DEV_GRE ULL(0xc)
782
783/*
784 * MAIR encodings for normal memory attributes.
785 *
786 * Cache Policy
787 * WT: Write Through
788 * WB: Write Back
789 * NC: Non-Cacheable
790 *
791 * Transient Hint
792 * NTR: Non-Transient
793 * TR: Transient
794 *
795 * Allocation Policy
796 * RA: Read Allocate
797 * WA: Write Allocate
798 * RWA: Read and Write Allocate
799 * NA: No Allocation
800 */
801#define MAIR_NORM_WT_TR_WA ULL(0x1)
802#define MAIR_NORM_WT_TR_RA ULL(0x2)
803#define MAIR_NORM_WT_TR_RWA ULL(0x3)
804#define MAIR_NORM_NC ULL(0x4)
805#define MAIR_NORM_WB_TR_WA ULL(0x5)
806#define MAIR_NORM_WB_TR_RA ULL(0x6)
807#define MAIR_NORM_WB_TR_RWA ULL(0x7)
808#define MAIR_NORM_WT_NTR_NA ULL(0x8)
809#define MAIR_NORM_WT_NTR_WA ULL(0x9)
810#define MAIR_NORM_WT_NTR_RA ULL(0xa)
811#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
812#define MAIR_NORM_WB_NTR_NA ULL(0xc)
813#define MAIR_NORM_WB_NTR_WA ULL(0xd)
814#define MAIR_NORM_WB_NTR_RA ULL(0xe)
815#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
816
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100817#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100818
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100819#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
820 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100821
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100822/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100823#define PAR_F_SHIFT U(0)
824#define PAR_F_MASK ULL(0x1)
825#define PAR_ADDR_SHIFT U(12)
826#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100827
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100828/*******************************************************************************
829 * Definitions for system register interface to SPE
830 ******************************************************************************/
831#define PMBLIMITR_EL1 S3_0_C9_C10_0
832
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100833/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100834 * Definitions for system register interface to MPAM
835 ******************************************************************************/
836#define MPAMIDR_EL1 S3_0_C10_C4_4
837#define MPAM2_EL2 S3_4_C10_C5_0
838#define MPAMHCR_EL2 S3_4_C10_C4_0
839#define MPAM3_EL3 S3_6_C10_C5_0
840
841/*******************************************************************************
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100842 * Definitions for system register interface to AMU for ARMv8.4 onwards
843 ******************************************************************************/
844#define AMCR_EL0 S3_3_C13_C2_0
845#define AMCFGR_EL0 S3_3_C13_C2_1
846#define AMCGCR_EL0 S3_3_C13_C2_2
847#define AMUSERENR_EL0 S3_3_C13_C2_3
848#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
849#define AMCNTENSET0_EL0 S3_3_C13_C2_5
850#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
851#define AMCNTENSET1_EL0 S3_3_C13_C3_1
852
853/* Activity Monitor Group 0 Event Counter Registers */
854#define AMEVCNTR00_EL0 S3_3_C13_C4_0
855#define AMEVCNTR01_EL0 S3_3_C13_C4_1
856#define AMEVCNTR02_EL0 S3_3_C13_C4_2
857#define AMEVCNTR03_EL0 S3_3_C13_C4_3
858
859/* Activity Monitor Group 0 Event Type Registers */
860#define AMEVTYPER00_EL0 S3_3_C13_C6_0
861#define AMEVTYPER01_EL0 S3_3_C13_C6_1
862#define AMEVTYPER02_EL0 S3_3_C13_C6_2
863#define AMEVTYPER03_EL0 S3_3_C13_C6_3
864
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000865/* Activity Monitor Group 1 Event Counter Registers */
866#define AMEVCNTR10_EL0 S3_3_C13_C12_0
867#define AMEVCNTR11_EL0 S3_3_C13_C12_1
868#define AMEVCNTR12_EL0 S3_3_C13_C12_2
869#define AMEVCNTR13_EL0 S3_3_C13_C12_3
870#define AMEVCNTR14_EL0 S3_3_C13_C12_4
871#define AMEVCNTR15_EL0 S3_3_C13_C12_5
872#define AMEVCNTR16_EL0 S3_3_C13_C12_6
873#define AMEVCNTR17_EL0 S3_3_C13_C12_7
874#define AMEVCNTR18_EL0 S3_3_C13_C13_0
875#define AMEVCNTR19_EL0 S3_3_C13_C13_1
876#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
877#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
878#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
879#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
880#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
881#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
882
883/* Activity Monitor Group 1 Event Type Registers */
884#define AMEVTYPER10_EL0 S3_3_C13_C14_0
885#define AMEVTYPER11_EL0 S3_3_C13_C14_1
886#define AMEVTYPER12_EL0 S3_3_C13_C14_2
887#define AMEVTYPER13_EL0 S3_3_C13_C14_3
888#define AMEVTYPER14_EL0 S3_3_C13_C14_4
889#define AMEVTYPER15_EL0 S3_3_C13_C14_5
890#define AMEVTYPER16_EL0 S3_3_C13_C14_6
891#define AMEVTYPER17_EL0 S3_3_C13_C14_7
892#define AMEVTYPER18_EL0 S3_3_C13_C15_0
893#define AMEVTYPER19_EL0 S3_3_C13_C15_1
894#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
895#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
896#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
897#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
898#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
899#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
900
901/* AMCGCR_EL0 definitions */
902#define AMCGCR_EL0_CG1NC_SHIFT U(8)
903#define AMCGCR_EL0_CG1NC_LENGTH U(8)
904#define AMCGCR_EL0_CG1NC_MASK U(0xff)
905
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100906/* MPAM register definitions */
907#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +0000908#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
909
910#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
911#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100912
913#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
914
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100915/*******************************************************************************
916 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +0000917 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100918#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100919#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100920
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000921#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100922#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000923
924#define ERRSELR_EL1 S3_0_C5_C3_1
925
926/* System register access to Standard Error Record registers */
927#define ERXFR_EL1 S3_0_C5_C4_0
928#define ERXCTLR_EL1 S3_0_C5_C4_1
929#define ERXSTATUS_EL1 S3_0_C5_C4_2
930#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000931#define ERXPFGF_EL1 S3_0_C5_C4_4
932#define ERXPFGCTL_EL1 S3_0_C5_C4_5
933#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +0200934#define ERXMISC0_EL1 S3_0_C5_C5_0
935#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000936
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000937#define ERXCTLR_ED_BIT (U(1) << 0)
938#define ERXCTLR_UE_BIT (U(1) << 4)
939
940#define ERXPFGCTL_UC_BIT (U(1) << 1)
941#define ERXPFGCTL_UEU_BIT (U(1) << 2)
942#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
943
944/*******************************************************************************
945 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +0000946 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000947#define APIAKeyLo_EL1 S3_0_C2_C1_0
948#define APIAKeyHi_EL1 S3_0_C2_C1_1
949#define APIBKeyLo_EL1 S3_0_C2_C1_2
950#define APIBKeyHi_EL1 S3_0_C2_C1_3
951#define APDAKeyLo_EL1 S3_0_C2_C2_0
952#define APDAKeyHi_EL1 S3_0_C2_C2_1
953#define APDBKeyLo_EL1 S3_0_C2_C2_2
954#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000955#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000956#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000957
Sathees Balya0911df12018-12-06 13:33:24 +0000958/*******************************************************************************
959 * Armv8.4 Data Independent Timing Registers
960 ******************************************************************************/
961#define DIT S3_3_C4_C2_5
962#define DIT_BIT BIT(24)
963
John Tsichritzis1f9ff492019-03-04 16:41:26 +0000964/*******************************************************************************
965 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
966 ******************************************************************************/
967#define SSBS S3_3_C4_C2_6
968
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100969/*******************************************************************************
970 * Armv8.5 - Memory Tagging Extension Registers
971 ******************************************************************************/
972#define TFSRE0_EL1 S3_0_C5_C6_1
973#define TFSR_EL1 S3_0_C5_C6_0
974#define RGSR_EL1 S3_0_C1_C0_5
975#define GCR_EL1 S3_0_C1_C0_6
976
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500977/*******************************************************************************
978 * Definitions for DynamicIQ Shared Unit registers
979 ******************************************************************************/
980#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
981
982/* CLUSTERPWRDN_EL1 register definitions */
983#define DSU_CLUSTER_PWR_OFF 0
984#define DSU_CLUSTER_PWR_ON 1
985#define DSU_CLUSTER_PWR_MASK U(1)
986
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100987#endif /* ARCH_H */