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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Ambroise Vincent09a22e72019-05-29 14:04:16 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <errno.h>
9#include <stddef.h>
10#include <string.h>
11
12#include <platform_def.h>
13
Varun Wadekarb316e242015-05-19 16:48:04 +053014#include <arch.h>
15#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <bl31/bl31.h>
17#include <common/bl_common.h>
18#include <common/debug.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053019#include <cortex_a53.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010020#include <cortex_a57.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053021#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/console.h>
23#include <lib/mmio.h>
24#include <lib/utils.h>
25#include <lib/utils_def.h>
26#include <plat/common/platform.h>
27
Varun Wadekarb316e242015-05-19 16:48:04 +053028#include <memctrl.h>
Varun Wadekar4967c3d2017-07-21 13:34:16 -070029#include <profiler.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080030#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080031#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053032#include <tegra_private.h>
33
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080034/* length of Trusty's input parameters (in bytes) */
35#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
36
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010037extern void memcpy16(void *dest, const void *src, unsigned int length);
Varun Wadekarb41a4142016-05-23 15:56:14 -070038
Varun Wadekarb316e242015-05-19 16:48:04 +053039/*******************************************************************************
40 * Declarations of linker defined symbols which will help us find the layout
41 * of trusted SRAM
42 ******************************************************************************/
Joel Hutton5cc3bc82018-03-21 11:40:57 +000043
Varun Wadekarfda095f2019-01-02 10:48:18 -080044IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
45IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
46IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
47IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
48IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
49IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
Varun Wadekarb316e242015-05-19 16:48:04 +053050
Varun Wadekarb316e242015-05-19 16:48:04 +053051extern uint64_t tegra_bl31_phys_base;
52
Varun Wadekar52a15982015-06-05 12:57:27 +053053static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053054static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarfda095f2019-01-02 10:48:18 -080055 .tzdram_size = TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053056};
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080057static unsigned long bl32_mem_size;
58static unsigned long bl32_boot_params;
Varun Wadekarb316e242015-05-19 16:48:04 +053059
60/*******************************************************************************
61 * This variable holds the non-secure image entry address
62 ******************************************************************************/
63extern uint64_t ns_image_entrypoint;
64
65/*******************************************************************************
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070066 * The following platform setup functions are weakly defined. They
67 * provide typical implementations that will be overridden by a SoC.
68 ******************************************************************************/
69#pragma weak plat_early_platform_setup
Varun Wadekard22d4ad2016-05-23 11:41:07 -070070#pragma weak plat_get_bl31_params
71#pragma weak plat_get_bl31_plat_params
Dilan Lee1f66f3d2017-10-27 09:51:09 +080072#pragma weak plat_late_platform_setup
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070073
74void plat_early_platform_setup(void)
75{
76 ; /* do nothing */
77}
78
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010079struct tegra_bl31_params *plat_get_bl31_params(void)
Varun Wadekard22d4ad2016-05-23 11:41:07 -070080{
81 return NULL;
82}
83
84plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
85{
86 return NULL;
87}
88
Dilan Lee1f66f3d2017-10-27 09:51:09 +080089void plat_late_platform_setup(void)
90{
91 ; /* do nothing */
92}
93
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070094/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +053095 * Return a pointer to the 'entry_point_info' structure of the next image for
96 * security state specified. BL33 corresponds to the non-secure image type
97 * while BL32 corresponds to the secure image type.
98 ******************************************************************************/
99entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
100{
Varun Wadekarfda095f2019-01-02 10:48:18 -0800101 entry_point_info_t *ep = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530102
Varun Wadekar197a75f2016-06-06 10:46:28 -0700103 /* return BL32 entry point info if it is valid */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800104 if (type == NON_SECURE) {
105 ep = &bl33_image_ep_info;
106 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
107 ep = &bl32_image_ep_info;
108 }
Varun Wadekar52a15982015-06-05 12:57:27 +0530109
Varun Wadekarfda095f2019-01-02 10:48:18 -0800110 return ep;
Varun Wadekarb316e242015-05-19 16:48:04 +0530111}
112
113/*******************************************************************************
114 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
115 * passes this platform specific information.
116 ******************************************************************************/
117plat_params_from_bl2_t *bl31_get_plat_params(void)
118{
119 return &plat_bl31_params_from_bl2;
120}
121
122/*******************************************************************************
123 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
124 * info.
125 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100126void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
127 u_register_t arg2, u_register_t arg3)
Varun Wadekarb316e242015-05-19 16:48:04 +0530128{
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100129 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
130 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
Varun Wadekarb41a4142016-05-23 15:56:14 -0700131 image_info_t bl32_img_info = { {0} };
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100132 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base;
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800133 uint32_t console_clock;
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700134 int32_t ret;
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100135 static console_16550_t console;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530136
Varun Wadekarb316e242015-05-19 16:48:04 +0530137 /*
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700138 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
139 * there's no argument to relay from a previous bootloader. Platforms
140 * might use custom ways to get arguments, so provide handlers which
141 * they can override.
142 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800143 if (arg_from_bl2 == NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100144 arg_from_bl2 = plat_get_bl31_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800145 }
146 if (plat_params == NULL) {
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700147 plat_params = plat_get_bl31_plat_params();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800148 }
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700149
150 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530151 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530152 * They are stored in Secure RAM, in BL2's address space.
153 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800154 assert(arg_from_bl2 != NULL);
155 assert(arg_from_bl2->bl33_ep_info != NULL);
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100156 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530157
Varun Wadekarfda095f2019-01-02 10:48:18 -0800158 if (arg_from_bl2->bl32_ep_info != NULL) {
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100159 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
160 bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
161 bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800162 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530163
164 /*
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800165 * Parse platform specific parameters
Varun Wadekarb316e242015-05-19 16:48:04 +0530166 */
Anthony Zhou4408e882017-07-07 14:29:51 +0800167 assert(plat_params != NULL);
Varun Wadekar6bb62462015-10-06 12:49:31 +0530168 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
169 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530170 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800171 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800172 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
173 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
Varun Wadekard2014c62015-10-29 10:37:28 +0530174
175 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700176 * It is very important that we run either from TZDRAM or TZSRAM base.
177 * Add an explicit check here.
178 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800179 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
180 (TEGRA_TZRAM_BASE != BL31_BASE)) {
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700181 panic();
Varun Wadekarfda095f2019-01-02 10:48:18 -0800182 }
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700183
184 /*
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800185 * Reference clock used by the FPGAs is a lot slower.
186 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800187 if (tegra_platform_is_fpga()) {
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800188 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
189 } else {
190 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
191 }
192
193 /*
Varun Wadekard2014c62015-10-29 10:37:28 +0530194 * Get the base address of the UART controller to be used for the
195 * console
196 */
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100197 console_base = plat_get_console_from_id(plat_params->uart_id);
Varun Wadekard2014c62015-10-29 10:37:28 +0530198
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100199 if (console_base != 0U) {
Damon Duan777baa52016-11-07 19:37:50 +0800200 /*
201 * Configure the UART port to be used as the console
202 */
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100203 (void)console_16550_register(console_base,
204 console_clock,
205 TEGRA_CONSOLE_BAUDRATE,
206 &console);
207 console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
208 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
Damon Duan777baa52016-11-07 19:37:50 +0800209 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530210
Varun Wadekar5118b532016-06-04 22:08:50 -0700211 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700212 * The previous bootloader passes the base address of the shared memory
213 * location to store the boot profiler logs. Sanity check the
Andreas Färberd829cd42019-06-17 00:06:43 +0200214 * address and initialise the profiler library, if it looks ok.
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700215 */
216 if (plat_params->boot_profiler_shmem_base != 0ULL) {
217
218 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
219 PROFILER_SIZE_BYTES);
220 if (ret == (int32_t)0) {
221
222 /* store the membase for the profiler lib */
223 plat_bl31_params_from_bl2.boot_profiler_shmem_base =
224 plat_params->boot_profiler_shmem_base;
225
226 /* initialise the profiler library */
227 boot_profiler_init(plat_params->boot_profiler_shmem_base,
228 TEGRA_TMRUS_BASE);
229 }
230 }
231
232 /*
233 * Add timestamp for platform early setup entry.
234 */
235 boot_profiler_add_record("[TF] early setup entry");
236
237 /*
Steven Kao27e64312016-10-21 14:16:59 +0800238 * Initialize delay timer
239 */
240 tegra_delay_timer_init();
241
Varun Wadekardbe67c72017-09-20 15:09:38 -0700242 /* Early platform setup for Tegra SoCs */
243 plat_early_platform_setup();
244
Steven Kao27e64312016-10-21 14:16:59 +0800245 /*
Varun Wadekar5118b532016-06-04 22:08:50 -0700246 * Do initial security configuration to allow DRAM/device access.
247 */
248 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
Varun Wadekarfda095f2019-01-02 10:48:18 -0800249 (uint32_t)plat_bl31_params_from_bl2.tzdram_size);
Varun Wadekar5118b532016-06-04 22:08:50 -0700250
Varun Wadekarb41a4142016-05-23 15:56:14 -0700251 /*
252 * The previous bootloader might not have placed the BL32 image
253 * inside the TZDRAM. We check the BL32 image info to find out
254 * the base/PC values and relocate the image if necessary.
255 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800256 if (arg_from_bl2->bl32_image_info != NULL) {
Varun Wadekarb41a4142016-05-23 15:56:14 -0700257
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100258 bl32_img_info = *arg_from_bl2->bl32_image_info;
Varun Wadekarb41a4142016-05-23 15:56:14 -0700259
260 /* Relocate BL32 if it resides outside of the TZDRAM */
261 tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
262 tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
263 plat_bl31_params_from_bl2.tzdram_size;
264 bl32_start = bl32_img_info.image_base;
265 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
266
267 assert(tzdram_end > tzdram_start);
268 assert(bl32_end > bl32_start);
269 assert(bl32_image_ep_info.pc > tzdram_start);
270 assert(bl32_image_ep_info.pc < tzdram_end);
271
272 /* relocate BL32 */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800273 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
Varun Wadekarb41a4142016-05-23 15:56:14 -0700274
275 INFO("Relocate BL32 to TZDRAM\n");
276
Varun Wadekarfda095f2019-01-02 10:48:18 -0800277 (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
Varun Wadekarb41a4142016-05-23 15:56:14 -0700278 (void *)(uintptr_t)bl32_start,
279 bl32_img_info.image_size);
280
281 /* clean up non-secure intermediate buffer */
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100282 zeromem((void *)(uintptr_t)bl32_start,
Varun Wadekarb41a4142016-05-23 15:56:14 -0700283 bl32_img_info.image_size);
284 }
285 }
286
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700287 /*
288 * Add timestamp for platform early setup exit.
289 */
290 boot_profiler_add_record("[TF] early setup exit");
291
Sandrine Bailleuxfff61b62018-06-21 11:41:43 +0200292 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
293 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
294 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530295}
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800296
297#ifdef SPD_trusty
298void plat_trusty_set_boot_args(aapcs64_params_t *args)
299{
300 args->arg0 = bl32_mem_size;
301 args->arg1 = bl32_boot_params;
302 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
Varun Wadekarc2099802018-12-28 13:50:20 -0800303
304 /* update EKS size */
305 if (args->arg4 != 0U) {
306 args->arg2 = args->arg4;
307 }
Varun Wadekar7a1ba292019-01-02 16:30:01 -0800308
309 /* Profiler Carveout Base */
310 args->arg3 = args->arg5;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800311}
312#endif
Varun Wadekarb316e242015-05-19 16:48:04 +0530313
314/*******************************************************************************
315 * Initialize the gic, configure the SCR.
316 ******************************************************************************/
317void bl31_platform_setup(void)
318{
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700319 /*
320 * Add timestamp for platform setup entry.
321 */
322 boot_profiler_add_record("[TF] plat setup entry");
323
Varun Wadekarb7b45752015-12-28 14:55:41 -0800324 /* Initialize the gic cpu and distributor interfaces */
325 plat_gic_setup();
326
Varun Wadekarb316e242015-05-19 16:48:04 +0530327 /*
328 * Setup secondary CPU POR infrastructure.
329 */
330 plat_secondary_setup();
331
332 /*
333 * Initial Memory Controller configuration.
334 */
335 tegra_memctrl_setup();
336
337 /*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800338 * Set up the TZRAM memory aperture to allow only secure world
339 * access
340 */
341 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
342
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700343 /*
Dilan Lee1f66f3d2017-10-27 09:51:09 +0800344 * Late setup handler to allow platforms to performs additional
345 * functionality.
346 * This handler gets called with MMU enabled.
347 */
348 plat_late_platform_setup();
349
350 /*
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700351 * Add timestamp for platform setup exit.
352 */
353 boot_profiler_add_record("[TF] plat setup exit");
354
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530355 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530356}
357
358/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800359 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
360 ******************************************************************************/
361void bl31_plat_runtime_setup(void)
362{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700363 /*
Harvey Hsieh359be952017-08-21 15:01:53 +0800364 * During cold boot, it is observed that the arbitration
365 * bit is set in the Memory controller leading to false
366 * error interrupts in the non-secure world. To avoid
367 * this, clean the interrupt status register before
368 * booting into the non-secure world
369 */
370 tegra_memctrl_clear_pending_interrupts();
371
372 /*
Varun Wadekarc92050b2017-03-29 14:57:29 -0700373 * During boot, USB3 and flash media (SDMMC/SATA) devices need
374 * access to IRAM. Because these clients connect to the MC and
375 * do not have a direct path to the IRAM, the MC implements AHB
376 * redirection during boot to allow path to IRAM. In this mode
377 * accesses to a programmed memory address aperture are directed
378 * to the AHB bus, allowing access to the IRAM. This mode must be
379 * disabled before we jump to the non-secure world.
380 */
381 tegra_memctrl_disable_ahb_redirection();
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700382
383 /*
384 * Add final timestamp before exiting BL31.
385 */
386 boot_profiler_add_record("[TF] bl31 exit");
387 boot_profiler_deinit();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800388}
389
390/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530391 * Perform the very early platform specific architectural setup here. At the
392 * moment this only intializes the mmu in a quick and dirty way.
393 ******************************************************************************/
394void bl31_plat_arch_setup(void)
395{
Varun Wadekarfda095f2019-01-02 10:48:18 -0800396 uint64_t rw_start = BL31_RW_START;
397 uint64_t rw_size = BL31_RW_END - BL31_RW_START;
398 uint64_t rodata_start = BL31_RODATA_BASE;
399 uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
400 uint64_t code_base = TEXT_START;
401 uint64_t code_size = TEXT_END - TEXT_START;
Varun Wadekarb316e242015-05-19 16:48:04 +0530402 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530403#if USE_COHERENT_MEM
Varun Wadekarfda095f2019-01-02 10:48:18 -0800404 uint32_t coh_start, coh_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530405#endif
Varun Wadekarfda095f2019-01-02 10:48:18 -0800406 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530407
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700408 /*
409 * Add timestamp for arch setup entry.
410 */
411 boot_profiler_add_record("[TF] arch setup entry");
412
Varun Wadekar922550a2018-01-23 14:38:51 -0800413 /* add MMIO space */
414 plat_mmio_map = plat_get_mmio_map();
415 if (plat_mmio_map != NULL) {
416 mmap_add(plat_mmio_map);
417 } else {
418 WARN("MMIO map not available\n");
419 }
420
Varun Wadekarb316e242015-05-19 16:48:04 +0530421 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800422 mmap_add_region(rw_start, rw_start,
423 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530424 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800425 mmap_add_region(rodata_start, rodata_start,
426 rodata_size,
427 MT_RO_DATA | MT_SECURE);
428 mmap_add_region(code_base, code_base,
429 code_size,
430 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530431
Varun Wadekarb316e242015-05-19 16:48:04 +0530432#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900433 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
434 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
Varun Wadekar207cc732015-07-08 12:57:50 +0530435
Varun Wadekarb316e242015-05-19 16:48:04 +0530436 mmap_add_region(coh_start, coh_start,
437 coh_size,
Varun Wadekarfda095f2019-01-02 10:48:18 -0800438 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
Varun Wadekarb316e242015-05-19 16:48:04 +0530439#endif
440
Varun Wadekar922550a2018-01-23 14:38:51 -0800441 /* map TZDRAM used by BL31 as coherent memory */
442 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
443 mmap_add_region(params_from_bl2->tzdram_base,
444 params_from_bl2->tzdram_base,
445 BL31_SIZE,
446 MT_DEVICE | MT_RW | MT_SECURE);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800447 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530448
449 /* set up translation tables */
450 init_xlat_tables();
451
452 /* enable the MMU */
453 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530454
Varun Wadekar4967c3d2017-07-21 13:34:16 -0700455 /*
456 * Add timestamp for arch setup exit.
457 */
458 boot_profiler_add_record("[TF] arch setup exit");
459
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530460 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530461}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530462
463/*******************************************************************************
464 * Check if the given NS DRAM range is valid
465 ******************************************************************************/
Varun Wadekarfda095f2019-01-02 10:48:18 -0800466int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
Varun Wadekar7a269e22015-06-10 14:04:32 +0530467{
Varun Wadekarc74343c2017-07-20 09:43:28 -0700468 uint64_t end = base + size_in_bytes - U(1);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800469 int32_t ret = 0;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530470
471 /*
472 * Check if the NS DRAM address is valid
473 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700474 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
475 (end > TEGRA_DRAM_END)) {
476
Andreas Färber90bbade2019-06-16 23:32:20 +0200477 ERROR("NS address 0x%llx is out-of-bounds!\n", base);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800478 ret = -EFAULT;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530479 }
480
481 /*
482 * TZDRAM aperture contains the BL31 and BL32 images, so we need
483 * to check if the NS DRAM range overlaps the TZDRAM aperture.
484 */
Varun Wadekarc74343c2017-07-20 09:43:28 -0700485 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
Andreas Färber90bbade2019-06-16 23:32:20 +0200486 ERROR("NS address 0x%llx overlaps TZDRAM!\n", base);
Varun Wadekarfda095f2019-01-02 10:48:18 -0800487 ret = -ENOTSUP;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530488 }
489
490 /* valid NS address */
Varun Wadekarfda095f2019-01-02 10:48:18 -0800491 return ret;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530492}