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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Govindraj Rajab6709b02023-02-21 17:43:55 +00002 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
12#include <bl31/interrupt_mgmt.h>
Andre Przywarafa914d82022-11-21 17:04:10 +000013#include <bl31/sync_handle.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <common/runtime_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010015#include <context.h>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010016#include <el3_common_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/el3_runtime/cpu_data.h>
18#include <lib/smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
20 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010021
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000022 .globl sync_exception_sp_el0
23 .globl irq_sp_el0
24 .globl fiq_sp_el0
25 .globl serror_sp_el0
26
27 .globl sync_exception_sp_elx
28 .globl irq_sp_elx
29 .globl fiq_sp_elx
30 .globl serror_sp_elx
31
32 .globl sync_exception_aarch64
33 .globl irq_aarch64
34 .globl fiq_aarch64
35 .globl serror_aarch64
36
37 .globl sync_exception_aarch32
38 .globl irq_aarch32
39 .globl fiq_aarch32
40 .globl serror_aarch32
41
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000042 /*
Manish Pandey66a056e2023-01-11 21:41:07 +000043 * Save LR and make x30 available as most of the routines in vector entry
44 * need a free register
45 */
46 .macro save_x30
47 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
48 .endm
49
50 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010051 * Macro that prepares entry to EL3 upon taking an exception.
52 *
53 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
54 * instruction. When an error is thus synchronized, the handling is
55 * delegated to platform EA handler.
56 *
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050057 * Without RAS_EXTENSION, this macro synchronizes pending errors using
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +000058 * a DSB, unmasks Asynchronous External Aborts and saves X30 before
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050059 * setting the flag CTX_IS_IN_EL3.
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010060 */
61 .macro check_and_unmask_ea
62#if RAS_EXTENSION
63 /* Synchronize pending External Aborts */
64 esb
65
66 /* Unmask the SError interrupt */
67 msr daifclr, #DAIF_ABT_BIT
68
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010069 /* Check for SErrors synchronized by the ESB instruction */
70 mrs x30, DISR_EL1
71 tbz x30, #DISR_A_BIT, 1f
72
Alexei Fedorov503bbf32019-08-13 15:17:53 +010073 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +010074 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
75 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
76 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Daniel Boulby928747f2021-05-25 18:09:34 +010077 * Also set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +010078 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +000079 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +010080
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010081 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010082
Alexei Fedorovf41355c2019-09-13 14:11:59 +010083 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
84 bl restore_gp_pmcr_pauth_regs
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100851:
86#else
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050087 /*
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050088 * Note 1: The explicit DSB at the entry of various exception vectors
89 * for handling exceptions from lower ELs can inadvertently trigger an
90 * SError exception in EL3 due to pending asynchronous aborts in lower
91 * ELs. This will end up being handled by serror_sp_elx which will
92 * ultimately panic and die.
93 * The way to workaround is to update a flag to indicate if the exception
94 * truly came from EL3. This flag is allocated in the cpu_context
95 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
96 * This is not a bullet proof solution to the problem at hand because
97 * we assume the instructions following "isb" that help to update the
98 * flag execute without causing further exceptions.
99 */
100
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500101 /*
Manish Pandeyb3c61982023-01-06 13:38:03 +0000102 * For SoCs which do not implement RAS, use DSB as a barrier to
103 * synchronize pending external aborts.
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500104 */
105 dsb sy
106
107 /* Unmask the SError interrupt */
108 msr daifclr, #DAIF_ABT_BIT
109
110 /* Use ISB for the above unmask operation to take effect immediately */
111 isb
112
Manish Pandey66a056e2023-01-11 21:41:07 +0000113 /* Refer Note 1. */
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500114 mov x30, #1
115 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
116 dmb sy
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500117#endif
Manish Pandeyb3c61982023-01-06 13:38:03 +0000118 .endm
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500119
Douglas Raillard0980eed2016-11-09 17:48:27 +0000120 /* ---------------------------------------------------------------------
121 * This macro handles Synchronous exceptions.
122 * Only SMC exceptions are supported.
123 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100124 */
125 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +0100126#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +0100127 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000128 * Read the timestamp value and store it in per-cpu data. The value
129 * will be extracted from per-cpu data by the C level SMC handler and
130 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +0100131 */
132 mrs x30, cntpct_el0
133 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
134 mrs x29, tpidr_el3
135 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
136 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
137#endif
138
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100139 mrs x30, esr_el3
140 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
141
Douglas Raillard0980eed2016-11-09 17:48:27 +0000142 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100143 cmp x30, #EC_AARCH32_SMC
144 b.eq smc_handler32
145
146 cmp x30, #EC_AARCH64_SMC
Andre Przywarafa914d82022-11-21 17:04:10 +0000147 b.eq sync_handler64
148
149 cmp x30, #EC_AARCH64_SYS
150 b.eq sync_handler64
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100151
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100152 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700153 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Manish Pandeyc918c182023-01-11 21:53:02 +0000154 b handle_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100155 .endm
156
157
Douglas Raillard0980eed2016-11-09 17:48:27 +0000158 /* ---------------------------------------------------------------------
159 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
160 * interrupts.
161 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100162 */
163 .macro handle_interrupt_exception label
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000164
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100165 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100166 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
167 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
168 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Daniel Boulby928747f2021-05-25 18:09:34 +0100169 * Also set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100170 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000171 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100172
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000173#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100174 /* Load and program APIAKey firmware key */
175 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000176#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000177
Douglas Raillard0980eed2016-11-09 17:48:27 +0000178 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +0100179 mrs x0, spsr_el3
180 mrs x1, elr_el3
181 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
182
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100183 /* Switch to the runtime stack i.e. SP_EL0 */
184 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
185 mov x20, sp
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100186 msr spsel, #MODE_SP_EL0
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100187 mov sp, x2
188
189 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000190 * Find out whether this is a valid interrupt type.
191 * If the interrupt controller reports a spurious interrupt then return
192 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100193 */
Dan Handley701fea72014-05-27 16:17:21 +0100194 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100195 cmp x0, #INTR_TYPE_INVAL
196 b.eq interrupt_exit_\label
197
198 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000199 * Get the registered handler for this interrupt type.
200 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100201 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000202 * a. An interrupt of a type was routed correctly but a handler for its
203 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100204 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000205 * b. An interrupt of a type was not routed correctly so a handler for
206 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100207 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000208 * c. An interrupt of a type was routed correctly to EL3, but was
209 * deasserted before its pending state could be read. Another
210 * interrupt of a different type pended at the same time and its
211 * type was reported as pending instead. However, a handler for this
212 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100213 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000214 * a. and b. can only happen due to a programming error. The
215 * occurrence of c. could be beyond the control of Trusted Firmware.
216 * It makes sense to return from this exception instead of reporting an
217 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100218 */
219 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100220 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100221 mov x21, x0
222
223 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100224
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100225 /* Set the current security state in the 'flags' parameter */
226 mrs x2, scr_el3
227 ubfx x1, x2, #0, #1
228
229 /* Restore the reference to the 'handle' i.e. SP_EL3 */
230 mov x2, x20
231
Douglas Raillard0980eed2016-11-09 17:48:27 +0000232 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100233 mov x3, xzr
234
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100235 /* Call the interrupt type handler */
236 blr x21
237
238interrupt_exit_\label:
239 /* Return from exception, possibly in a different security state */
240 b el3_exit
241
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100242 .endm
243
244
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100245vector_base runtime_exceptions
246
Douglas Raillard0980eed2016-11-09 17:48:27 +0000247 /* ---------------------------------------------------------------------
248 * Current EL with SP_EL0 : 0x0 - 0x200
249 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100250 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100251vector_entry sync_exception_sp_el0
Justin Chadwell83e04882019-08-20 11:01:52 +0100252#ifdef MONITOR_TRAPS
253 stp x29, x30, [sp, #-16]!
254
255 mrs x30, esr_el3
256 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
257
258 /* Check for BRK */
259 cmp x30, #EC_BRK
260 b.eq brk_handler
261
262 ldp x29, x30, [sp], #16
263#endif /* MONITOR_TRAPS */
264
Douglas Raillard0980eed2016-11-09 17:48:27 +0000265 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700266 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100267end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100269vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000270 /*
271 * EL3 code is non-reentrant. Any asynchronous exception is a serious
272 * error. Loop infinitely.
273 */
Julius Werner67ebde72017-07-27 14:59:34 -0700274 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100275end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100277
278vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700279 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100280end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100281
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100282
283vector_entry serror_sp_el0
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100284 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100285end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286
Douglas Raillard0980eed2016-11-09 17:48:27 +0000287 /* ---------------------------------------------------------------------
288 * Current EL with SP_ELx: 0x200 - 0x400
289 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100290 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100291vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000292 /*
293 * This exception will trigger if anything went wrong during a previous
294 * exception entry or exit or while handling an earlier unexpected
295 * synchronous exception. There is a high probability that SP_EL3 is
296 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000297 */
Julius Werner67ebde72017-07-27 14:59:34 -0700298 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100299end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100300
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100301vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700302 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100303end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000304
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100305vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700306 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100307end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000308
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100309vector_entry serror_sp_elx
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500310#if !RAS_EXTENSION
Manish Pandeyb3c61982023-01-06 13:38:03 +0000311 /*
312 * This will trigger if the exception was taken due to SError in EL3 or
313 * because of pending asynchronous external aborts from lower EL that got
314 * triggered due to explicit synchronization in EL3. Refer Note 1.
315 */
316 /* Assumes SP_EL3 on entry */
Manish Pandey66a056e2023-01-11 21:41:07 +0000317 save_x30
Manish Pandeyb3c61982023-01-06 13:38:03 +0000318 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
319 cbnz x30, 1f
320
321 /* Handle asynchronous external abort from lower EL */
322 b handle_lower_el_async_ea
3231:
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500324#endif
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100325 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100326end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327
Douglas Raillard0980eed2016-11-09 17:48:27 +0000328 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100329 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000330 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100331 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100332vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000333 /*
334 * This exception vector will be the entry point for SMCs and traps
335 * that are unhandled at lower ELs most commonly. SP_EL3 should point
336 * to a valid cpu context where the general purpose and system register
337 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000338 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000339 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100340 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100341 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000342 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100343end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100344
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100345vector_entry irq_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000346 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100347 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100348 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100349 handle_interrupt_exception irq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100350end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100352vector_entry fiq_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000353 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100354 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100355 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100356 handle_interrupt_exception fiq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100357end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100358
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100359vector_entry serror_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000360 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100361 apply_at_speculative_wa
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500362#if RAS_EXTENSION
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000363 msr daifclr, #DAIF_ABT_BIT
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500364#else
Manish Pandeyb3c61982023-01-06 13:38:03 +0000365 check_and_unmask_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500366#endif
Manish Pandeyc918c182023-01-11 21:53:02 +0000367 b handle_lower_el_async_ea
368
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100369end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100370
Douglas Raillard0980eed2016-11-09 17:48:27 +0000371 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100372 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000373 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100374 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100375vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000376 /*
377 * This exception vector will be the entry point for SMCs and traps
378 * that are unhandled at lower ELs most commonly. SP_EL3 should point
379 * to a valid cpu context where the general purpose and system register
380 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000381 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000382 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100383 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100384 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000385 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100386end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100387
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100388vector_entry irq_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000389 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100390 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100391 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100392 handle_interrupt_exception irq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100393end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100394
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100395vector_entry fiq_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000396 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100397 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100398 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100399 handle_interrupt_exception fiq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100400end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100402vector_entry serror_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000403 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100404 apply_at_speculative_wa
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500405#if RAS_EXTENSION
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000406 msr daifclr, #DAIF_ABT_BIT
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500407#else
Manish Pandeyb3c61982023-01-06 13:38:03 +0000408 check_and_unmask_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500409#endif
Manish Pandeyc918c182023-01-11 21:53:02 +0000410 b handle_lower_el_async_ea
411
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100412end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000413
Justin Chadwell83e04882019-08-20 11:01:52 +0100414#ifdef MONITOR_TRAPS
415 .section .rodata.brk_string, "aS"
416brk_location:
417 .asciz "Error at instruction 0x"
418brk_message:
419 .asciz "Unexpected BRK instruction with value 0x"
420#endif /* MONITOR_TRAPS */
421
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100422 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000423 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000424 * Depending upon the execution state from where the SMC has been
425 * invoked, it frees some general purpose registers to perform the
426 * remaining tasks. They involve finding the runtime service handler
427 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
428 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000429 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000430 * Note that x30 has been explicitly saved and can be used here
431 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000432 */
Andre Przywarafa914d82022-11-21 17:04:10 +0000433func sync_exception_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000434smc_handler32:
435 /* Check whether aarch32 issued an SMC64 */
436 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
437
Andre Przywarafa914d82022-11-21 17:04:10 +0000438sync_handler64:
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000439 /* NOTE: The code below must preserve x0-x4 */
440
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100441 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100442 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
443 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
444 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Daniel Boulby928747f2021-05-25 18:09:34 +0100445 * Also set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100446 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000447 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100448
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000449#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100450 /* Load and program APIAKey firmware key */
451 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000452#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000453
Douglas Raillard0980eed2016-11-09 17:48:27 +0000454 /*
455 * Populate the parameters for the SMC handler.
456 * We already have x0-x4 in place. x5 will point to a cookie (not used
457 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000458 * contain flags we need to pass to the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000459 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000460 mov x5, xzr
461 mov x6, sp
462
Douglas Raillard0980eed2016-11-09 17:48:27 +0000463 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100464 * Restore the saved C runtime stack value which will become the new
465 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
466 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000467 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100468 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
469
470 /* Switch to SP_EL0 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100471 msr spsel, #MODE_SP_EL0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000472
Douglas Raillard0980eed2016-11-09 17:48:27 +0000473 /*
Manish Pandey70bbdbd2022-12-07 13:04:20 +0000474 * Save the SPSR_EL3 and ELR_EL3 in case there is a world
Douglas Raillard0980eed2016-11-09 17:48:27 +0000475 * switch during SMC handling.
476 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000477 */
478 mrs x16, spsr_el3
479 mrs x17, elr_el3
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000480 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Manish Pandey70bbdbd2022-12-07 13:04:20 +0000481
482 /* Load SCR_EL3 */
483 mrs x18, scr_el3
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000484
Andre Przywarafa914d82022-11-21 17:04:10 +0000485 /* check for system register traps */
486 mrs x16, esr_el3
487 ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH
488 cmp x17, #EC_AARCH64_SYS
489 b.eq sysreg_handler64
490
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500491 /* Clear flag register */
492 mov x7, xzr
493
494#if ENABLE_RME
495 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */
496 ubfx x7, x18, #SCR_NSE_SHIFT, 1
497
498 /*
499 * Shift copied SCR_EL3.NSE bit by 5 to create space for
Olivier Deprez33dd8452022-10-11 15:38:27 +0200500 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500501 * the SCR_EL3.NSE bit.
502 */
503 lsl x7, x7, #5
504#endif /* ENABLE_RME */
505
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000506 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
507 bfi x7, x18, #0, #1
508
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +0000509 mov sp, x12
510
511 /*
512 * Per SMCCC documentation, bits [23:17] must be zero for Fast
513 * SMCs. Other values are reserved for future use. Ensure that
514 * these bits are zeroes, if not report as unknown SMC.
515 */
516 tbz x0, #FUNCID_TYPE_SHIFT, 2f /* Skip check if its a Yield Call*/
517 tst x0, #(FUNCID_FC_RESERVED_MASK << FUNCID_FC_RESERVED_SHIFT)
518 b.ne smc_unknown
519
Olivier Deprez33dd8452022-10-11 15:38:27 +0200520 /*
521 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID
522 * passed through x0. Copy the SVE hint bit to flags and mask the
523 * bit in smc_fid passed to the standard service dispatcher.
524 * A service/dispatcher can retrieve the SVE hint bit state from
525 * flags using the appropriate helper.
526 */
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +00005272:
Olivier Deprez33dd8452022-10-11 15:38:27 +0200528 bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK
529 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT)
530
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500531 /* Get the unique owning entity number */
532 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
533 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
534 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
535
536 /* Load descriptor index from array of indices */
Madhukar Pappireddyf4e6ea62020-01-27 15:32:15 -0600537 adrp x14, rt_svc_descs_indices
538 add x14, x14, :lo12:rt_svc_descs_indices
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500539 ldrb w15, [x14, x16]
540
541 /* Any index greater than 127 is invalid. Check bit 7. */
542 tbnz w15, 7, smc_unknown
543
Douglas Raillard0980eed2016-11-09 17:48:27 +0000544 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500545 * Get the descriptor using the index
546 * x11 = (base + off), w15 = index
547 *
548 * handler = (base + off) + (index << log2(size))
549 */
550 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
551 lsl w10, w15, #RT_SVC_SIZE_LOG2
552 ldr x15, [x11, w10, uxtw]
553
554 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000555 * Call the Secure Monitor Call handler and then drop directly into
556 * el3_exit() which will program any remaining architectural state
557 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000558 */
559#if DEBUG
560 cbz x15, rt_svc_fw_critical_error
561#endif
562 blr x15
563
Andre Przywarafa914d82022-11-21 17:04:10 +0000564 b el3_exit
565
566sysreg_handler64:
567 mov x0, x16 /* ESR_EL3, containing syndrome information */
568 mov x1, x6 /* lower EL's context */
569 mov x19, x6 /* save context pointer for after the call */
570 mov sp, x12 /* EL3 runtime stack, as loaded above */
571
572 /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */
573 bl handle_sysreg_trap
574 /*
575 * returns:
576 * -1: unhandled trap, panic
577 * 0: handled trap, return to the trapping instruction (repeating it)
578 * 1: handled trap, return to the next instruction
579 */
580
581 tst w0, w0
Govindraj Rajab6709b02023-02-21 17:43:55 +0000582 b.mi elx_panic /* negative return value: panic */
Andre Przywarafa914d82022-11-21 17:04:10 +0000583 b.eq 1f /* zero: do not change ELR_EL3 */
584
585 /* advance the PC to continue after the instruction */
586 ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
587 add x1, x1, #4
588 str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
5891:
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100590 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100591
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000592smc_unknown:
593 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500594 * Unknown SMC call. Populate return value with SMC_UNK and call
595 * el3_exit() which will restore the remaining architectural state
596 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +0000597 * to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000598 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000599 mov x0, #SMC_UNK
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500600 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
601 b el3_exit
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000602
603smc_prohibited:
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100604 restore_ptw_el1_sys_regs
605 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100606 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000607 mov x0, #SMC_UNK
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800608 exception_return
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000609
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100610#if DEBUG
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000611rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000612 /* Switch to SP_ELx */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100613 msr spsel, #MODE_SP_ELX
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000614 no_ret report_unhandled_exception
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100615#endif
Andre Przywarafa914d82022-11-21 17:04:10 +0000616endfunc sync_exception_handler
Justin Chadwell83e04882019-08-20 11:01:52 +0100617
618 /* ---------------------------------------------------------------------
619 * The following code handles exceptions caused by BRK instructions.
620 * Following a BRK instruction, the only real valid cause of action is
621 * to print some information and panic, as the code that caused it is
622 * likely in an inconsistent internal state.
623 *
624 * This is initially intended to be used in conjunction with
625 * __builtin_trap.
626 * ---------------------------------------------------------------------
627 */
628#ifdef MONITOR_TRAPS
629func brk_handler
630 /* Extract the ISS */
631 mrs x10, esr_el3
632 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
633
634 /* Ensure the console is initialized */
635 bl plat_crash_console_init
636
637 adr x4, brk_location
638 bl asm_print_str
639 mrs x4, elr_el3
640 bl asm_print_hex
641 bl asm_print_newline
642
643 adr x4, brk_message
644 bl asm_print_str
645 mov x4, x10
646 mov x5, #28
647 bl asm_print_hex_bits
648 bl asm_print_newline
649
650 no_ret plat_panic_handler
651endfunc brk_handler
652#endif /* MONITOR_TRAPS */